stm32l4xx_hal_adc.h 115 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32l4xx_hal_adc.h
  4. * @author MCD Application Team
  5. * @brief Header file of ADC HAL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  10. *
  11. * Redistribution and use in source and binary forms, with or without modification,
  12. * are permitted provided that the following conditions are met:
  13. * 1. Redistributions of source code must retain the above copyright notice,
  14. * this list of conditions and the following disclaimer.
  15. * 2. Redistributions in binary form must reproduce the above copyright notice,
  16. * this list of conditions and the following disclaimer in the documentation
  17. * and/or other materials provided with the distribution.
  18. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  19. * may be used to endorse or promote products derived from this software
  20. * without specific prior written permission.
  21. *
  22. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32. *
  33. ******************************************************************************
  34. */
  35. /* Define to prevent recursive inclusion -------------------------------------*/
  36. #ifndef __STM32L4xx_HAL_ADC_H
  37. #define __STM32L4xx_HAL_ADC_H
  38. #ifdef __cplusplus
  39. extern "C" {
  40. #endif
  41. /* Includes ------------------------------------------------------------------*/
  42. #include "stm32l4xx_hal_def.h"
  43. /* Include low level driver */
  44. #include "stm32l4xx_ll_adc.h"
  45. /** @addtogroup STM32L4xx_HAL_Driver
  46. * @{
  47. */
  48. /** @addtogroup ADC
  49. * @{
  50. */
  51. /* Exported types ------------------------------------------------------------*/
  52. /** @defgroup ADC_Exported_Types ADC Exported Types
  53. * @{
  54. */
  55. /**
  56. * @brief ADC group regular oversampling structure definition
  57. */
  58. typedef struct
  59. {
  60. uint32_t Ratio; /*!< Configures the oversampling ratio.
  61. This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
  62. uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
  63. This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
  64. uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
  65. This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
  66. uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
  67. The oversampling is either temporary stopped or reset upon an injected
  68. sequence interruption.
  69. If oversampling is enabled on both regular and injected groups, this parameter
  70. is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
  71. (the oversampling buffer is zeroed during injection sequence).
  72. This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
  73. }ADC_OversamplingTypeDef;
  74. /**
  75. * @brief Structure definition of ADC instance and ADC group regular.
  76. * @note Parameters of this structure are shared within 2 scopes:
  77. * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
  78. * ScanConvMode, EOCSelection, LowPowerAutoWait.
  79. * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
  80. * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
  81. * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
  82. * ADC state can be either:
  83. * - For all parameters: ADC disabled
  84. * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
  85. * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
  86. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
  87. * without error reporting (as it can be the expected behavior in case of intended action to update another parameter
  88. * (which fulfills the ADC state condition) on the fly).
  89. */
  90. typedef struct
  91. {
  92. uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
  93. This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
  94. Note: The ADC clock configuration is common to all ADC instances.
  95. Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
  96. AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
  97. Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
  98. if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
  99. must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
  100. Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
  101. Note: This parameter can be modified only if all ADC instances are disabled. */
  102. uint32_t Resolution; /*!< Configure the ADC resolution.
  103. This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
  104. uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
  105. Refer to reference manual for alignments formats versus resolutions.
  106. This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
  107. uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
  108. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
  109. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
  110. Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
  111. If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
  112. Scan direction is upward: from rank 1 to rank 'n'.
  113. This parameter can be a value of @ref ADC_Scan_mode */
  114. uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
  115. This parameter can be a value of @ref ADC_EOCSelection. */
  116. uint32_t LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
  117. conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
  118. using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
  119. This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
  120. for low frequency applications.
  121. This parameter can be set to ENABLE or DISABLE.
  122. Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
  123. to free the IRQ vector sequencer.
  124. Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
  125. use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
  126. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
  127. uint32_t ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
  128. after the first ADC conversion start trigger occurred (software start or external trigger).
  129. This parameter can be set to ENABLE or DISABLE. */
  130. uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.
  131. To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
  132. This parameter must be a number between Min_Data = 1 and Max_Data = 16.
  133. Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
  134. continuous mode or external trigger that could launch a conversion). */
  135. uint32_t DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
  136. (main sequence subdivided in successive parts).
  137. Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
  138. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
  139. This parameter can be set to ENABLE or DISABLE. */
  140. uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
  141. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
  142. This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
  143. uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
  144. If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
  145. This parameter can be a value of @ref ADC_regular_external_trigger_source.
  146. Caution: external trigger source is common to all ADC instances. */
  147. uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
  148. If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
  149. This parameter can be a value of @ref ADC_regular_external_trigger_edge */
  150. uint32_t DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
  151. or in continuous mode (DMA transfer unlimited, whatever number of conversions).
  152. This parameter can be set to ENABLE or DISABLE.
  153. Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
  154. uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
  155. This parameter applies to ADC group regular only.
  156. This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
  157. Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
  158. end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
  159. HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
  160. Note: Error reporting with respect to the conversion mode:
  161. - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
  162. overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
  163. - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
  164. uint32_t OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
  165. This parameter can be set to ENABLE or DISABLE.
  166. Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
  167. ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
  168. Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
  169. #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
  170. uint32_t DFSDMConfig; /*!< Specify whether ADC conversion data is sent directly to DFSDM.
  171. This parameter can be a value of @ref ADC_HAL_EC_REG_DFSDM_TRANSFER.
  172. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
  173. #endif
  174. }ADC_InitTypeDef;
  175. /**
  176. * @brief Structure definition of ADC channel for regular group
  177. * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
  178. * ADC state can be either:
  179. * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
  180. * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
  181. * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
  182. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
  183. * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
  184. * on the fly).
  185. */
  186. typedef struct
  187. {
  188. uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
  189. This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
  190. Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
  191. uint32_t Rank; /*!< Specify the rank in the regular group sequencer.
  192. This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
  193. Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
  194. the new channel setting (or parameter number of conversions adjusted) */
  195. uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
  196. Unit: ADC clock cycles
  197. Conversion time is the addition of sampling time and processing time
  198. (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
  199. This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
  200. Caution: This parameter applies to a channel that can be used into regular and/or injected group.
  201. It overwrites the last setting.
  202. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
  203. sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
  204. Refer to device datasheet for timings values. */
  205. uint32_t SingleDiff; /*!< Select single-ended or differential input.
  206. In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
  207. Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
  208. This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
  209. Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
  210. It overwrites the last setting.
  211. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
  212. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
  213. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
  214. If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
  215. of another parameter update on the fly) */
  216. uint32_t OffsetNumber; /*!< Select the offset number
  217. This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
  218. Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
  219. uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data.
  220. Offset value must be a positive number.
  221. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
  222. 0x3FF, 0xFF or 0x3F respectively.
  223. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
  224. without continuous mode or external trigger that could launch a conversion). */
  225. }ADC_ChannelConfTypeDef;
  226. /**
  227. * @brief Structure definition of ADC analog watchdog
  228. * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
  229. * ADC state can be either:
  230. * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
  231. */
  232. typedef struct
  233. {
  234. uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
  235. For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
  236. For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
  237. This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
  238. uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
  239. For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected.
  240. For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.
  241. This parameter can be a value of @ref ADC_analog_watchdog_mode. */
  242. uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
  243. For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
  244. For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
  245. This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
  246. uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
  247. This parameter can be set to ENABLE or DISABLE */
  248. uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
  249. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
  250. between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
  251. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
  252. the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
  253. uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
  254. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
  255. between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
  256. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
  257. the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
  258. }ADC_AnalogWDGConfTypeDef;
  259. /**
  260. * @brief ADC group injected contexts queue configuration
  261. * @note Structure intended to be used only through structure "ADC_HandleTypeDef"
  262. */
  263. typedef struct
  264. {
  265. uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
  266. HAL_ADCEx_InjectedConfigChannel() call to finally initialize
  267. JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
  268. uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
  269. }ADC_InjectionConfigTypeDef;
  270. /** @defgroup ADC_States ADC States
  271. * @{
  272. */
  273. /**
  274. * @brief HAL ADC state machine: ADC states definition (bitfields)
  275. * @note ADC state machine is managed by bitfields, state must be compared
  276. * with bit by bit.
  277. * For example:
  278. * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
  279. * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
  280. */
  281. /* States of ADC global scope */
  282. #define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */
  283. #define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */
  284. #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy due to an internal process (initialization, calibration) */
  285. #define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */
  286. /* States of ADC errors */
  287. #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */
  288. #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */
  289. #define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */
  290. /* States of ADC group regular */
  291. #define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
  292. external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
  293. #define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */
  294. #define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */
  295. #define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on this STM32 serie: End Of Sampling flag raised */
  296. /* States of ADC group injected */
  297. #define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
  298. external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
  299. #define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */
  300. #define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Injected queue overflow occurrence */
  301. /* States of ADC analog watchdogs */
  302. #define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
  303. #define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Out-of-window occurrence of ADC analog watchdog 2 */
  304. #define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
  305. /* States of ADC multi-mode */
  306. #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
  307. /**
  308. * @}
  309. */
  310. /**
  311. * @brief ADC handle Structure definition
  312. */
  313. typedef struct
  314. {
  315. ADC_TypeDef *Instance; /*!< Register base address */
  316. ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
  317. DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
  318. HAL_LockTypeDef Lock; /*!< ADC locking object */
  319. __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
  320. __IO uint32_t ErrorCode; /*!< ADC Error code */
  321. ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
  322. }ADC_HandleTypeDef;
  323. /**
  324. * @}
  325. */
  326. /* Exported constants --------------------------------------------------------*/
  327. /** @defgroup ADC_Exported_Constants ADC Exported Constants
  328. * @{
  329. */
  330. /** @defgroup ADC_Error_Code ADC Error Code
  331. * @{
  332. */
  333. #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
  334. #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error (problem of clocking,
  335. enable/disable, erroneous state, ...) */
  336. #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
  337. #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
  338. #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */
  339. /**
  340. * @}
  341. */
  342. /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
  343. * @{
  344. */
  345. #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */
  346. #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
  347. #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
  348. #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */
  349. #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */
  350. #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */
  351. #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */
  352. #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */
  353. #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */
  354. #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */
  355. #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */
  356. #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */
  357. #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */
  358. #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */
  359. #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */
  360. #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 /*!< Obsolete naming, kept for compatibility with some other devices */
  361. #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /*!< Obsolete naming, kept for compatibility with some other devices */
  362. #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /*!< Obsolete naming, kept for compatibility with some other devices */
  363. /**
  364. * @}
  365. */
  366. /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
  367. * @{
  368. */
  369. #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */
  370. #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */
  371. #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */
  372. #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */
  373. /**
  374. * @}
  375. */
  376. /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
  377. * @{
  378. */
  379. #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
  380. #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
  381. /**
  382. * @}
  383. */
  384. /** @defgroup ADC_Scan_mode ADC sequencer scan mode
  385. * @{
  386. */
  387. #define ADC_SCAN_DISABLE (0x00000000U) /*!< Scan mode disabled */
  388. #define ADC_SCAN_ENABLE (0x00000001U) /*!< Scan mode enabled */
  389. /**
  390. * @}
  391. */
  392. /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
  393. * @{
  394. */
  395. /* ADC group regular trigger sources for all ADC instances */
  396. #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
  397. #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
  398. #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
  399. #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  400. #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  401. #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  402. #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
  403. #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  404. #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
  405. #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  406. #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
  407. #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
  408. #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
  409. #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
  410. #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
  411. #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
  412. #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
  413. /**
  414. * @}
  415. */
  416. /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
  417. * @{
  418. */
  419. #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000) /*!< Regular conversions hardware trigger detection disabled */
  420. #define ADC_EXTERNALTRIGCONVEDGE_RISING (ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */
  421. #define ADC_EXTERNALTRIGCONVEDGE_FALLING (ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */
  422. #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */
  423. /**
  424. * @}
  425. */
  426. /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
  427. * @{
  428. */
  429. #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */
  430. #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */
  431. /**
  432. * @}
  433. */
  434. /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
  435. * @{
  436. */
  437. #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */
  438. #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */
  439. /**
  440. * @}
  441. */
  442. /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
  443. * @{
  444. */
  445. #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
  446. #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
  447. #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
  448. #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
  449. #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
  450. #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
  451. #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
  452. #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
  453. #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */
  454. #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
  455. #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
  456. #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
  457. #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
  458. #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
  459. #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
  460. #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
  461. /**
  462. * @}
  463. */
  464. /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
  465. * @{
  466. */
  467. #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */
  468. #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */
  469. #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
  470. #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */
  471. #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */
  472. #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */
  473. #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */
  474. #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */
  475. #if defined(ADC_SMPR1_SMPPLUS)
  476. #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */
  477. #endif
  478. /**
  479. * @}
  480. */
  481. /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
  482. * @{
  483. */
  484. /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */
  485. /* all ADC instances (refer to Reference Manual). */
  486. #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
  487. #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
  488. #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
  489. #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
  490. #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
  491. #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
  492. #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
  493. #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
  494. #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
  495. #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
  496. #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
  497. #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
  498. #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
  499. #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
  500. #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
  501. #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
  502. #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
  503. #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
  504. #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
  505. #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
  506. #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */
  507. #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
  508. #if defined(ADC1) && !defined(ADC2)
  509. #define ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_DAC1CH1) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
  510. #define ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_DAC1CH2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
  511. #elif defined(ADC2)
  512. #define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
  513. #define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
  514. #if defined(ADC3)
  515. #define ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_DAC1CH1_ADC3) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */
  516. #define ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_DAC1CH2_ADC3) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */
  517. #endif
  518. #endif
  519. /**
  520. * @}
  521. */
  522. /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
  523. * @{
  524. */
  525. #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
  526. #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
  527. #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
  528. /**
  529. * @}
  530. */
  531. /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
  532. * @{
  533. */
  534. #define ADC_ANALOGWATCHDOG_NONE (0x00000000U) /*!< No analog watchdog selected */
  535. #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */
  536. #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */
  537. #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */
  538. #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
  539. #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */
  540. #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */
  541. /**
  542. * @}
  543. */
  544. /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
  545. * @{
  546. */
  547. #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
  548. #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
  549. #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
  550. #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
  551. #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
  552. #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
  553. #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
  554. #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
  555. /**
  556. * @}
  557. */
  558. /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
  559. * @{
  560. */
  561. #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
  562. #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
  563. #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
  564. #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
  565. #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
  566. #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
  567. #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
  568. #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
  569. #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
  570. /**
  571. * @}
  572. */
  573. /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
  574. * @{
  575. */
  576. #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
  577. #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
  578. /**
  579. * @}
  580. */
  581. /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular
  582. * @{
  583. */
  584. #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */
  585. #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */
  586. /**
  587. * @}
  588. */
  589. /** @defgroup ADC_Event_type ADC Event type
  590. * @{
  591. */
  592. #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
  593. #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
  594. #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
  595. #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
  596. #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
  597. #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
  598. /**
  599. * @}
  600. */
  601. #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
  602. /** @defgroup ADC_interrupts_definition ADC interrupts definition
  603. * @{
  604. */
  605. #define ADC_IT_RDY ADC_IER_ADRDY /*!< ADC Ready interrupt source */
  606. #define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of sampling interrupt source */
  607. #define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of regular conversion interrupt source */
  608. #define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of regular sequence of conversions interrupt source */
  609. #define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */
  610. #define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of injected conversion interrupt source */
  611. #define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of injected sequence of conversions interrupt source */
  612. #define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
  613. #define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
  614. #define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
  615. #define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */
  616. #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
  617. /**
  618. * @}
  619. */
  620. /** @defgroup ADC_flags_definition ADC flags definition
  621. * @{
  622. */
  623. #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
  624. #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
  625. #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
  626. #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
  627. #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
  628. #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
  629. #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
  630. #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
  631. #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
  632. #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
  633. #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
  634. #define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */
  635. #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
  636. ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
  637. ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) /*!< ADC all flags */
  638. /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */
  639. #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
  640. ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
  641. ADC_FLAG_JQOVF) /*!< ADC post-conversion all flags */
  642. /**
  643. * @}
  644. */
  645. /**
  646. * @}
  647. */
  648. /* Private macro -------------------------------------------------------------*/
  649. /** @defgroup ADC_Private_Macros ADC Private Macros
  650. * @{
  651. */
  652. /* Macro reserved for internal HAL driver usage, not intended to be used in */
  653. /* code of final user. */
  654. /**
  655. * @brief Test if conversion trigger of regular group is software start
  656. * or external trigger.
  657. * @param __HANDLE__ ADC handle
  658. * @retval SET (software start) or RESET (external trigger)
  659. */
  660. #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
  661. (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
  662. /**
  663. * @brief Return resolution bits in CFGR register RES[1:0] field.
  664. * @param __HANDLE__ ADC handle
  665. * @retval Value of bitfield RES in CFGR register.
  666. */
  667. #define ADC_GET_RESOLUTION(__HANDLE__) \
  668. (LL_ADC_GetResolution((__HANDLE__)->Instance))
  669. /**
  670. * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
  671. * @param __HANDLE__ ADC handle
  672. * @retval None
  673. */
  674. #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
  675. /**
  676. * @brief Verification of ADC state: enabled or disabled.
  677. * @param __HANDLE__ ADC handle
  678. * @retval SET (ADC enabled) or RESET (ADC disabled)
  679. */
  680. #define ADC_IS_ENABLE(__HANDLE__) \
  681. (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
  682. ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
  683. ) ? SET : RESET)
  684. /**
  685. * @brief Check if conversion is on going on regular group.
  686. * @param __HANDLE__ ADC handle
  687. * @retval SET (conversion is on going) or RESET (no conversion is on going)
  688. */
  689. #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
  690. (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))
  691. /**
  692. * @brief Simultaneously clear and set specific bits of the handle State.
  693. * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
  694. * the first parameter is the ADC handle State, the second parameter is the
  695. * bit field to clear, the third and last parameter is the bit field to set.
  696. * @retval None
  697. */
  698. #define ADC_STATE_CLR_SET MODIFY_REG
  699. /**
  700. * @brief Verify that a given value is aligned with the ADC resolution range.
  701. * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
  702. * @param __ADC_VALUE__ value checked against the resolution.
  703. * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
  704. */
  705. #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
  706. ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= (0x0FFF))) || \
  707. (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= (0x03FF))) || \
  708. (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= (0x00FF))) || \
  709. (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= (0x003F))) )
  710. /**
  711. * @brief Verify the length of the scheduled regular conversions group.
  712. * @param __LENGTH__ number of programmed conversions.
  713. * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
  714. */
  715. #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (16U)))
  716. /**
  717. * @brief Verify the number of scheduled regular conversions in discontinuous mode.
  718. * @param NUMBER number of scheduled regular conversions in discontinuous mode.
  719. * @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large)
  720. */
  721. #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
  722. /**
  723. * @brief Verify the ADC clock setting.
  724. * @param __ADC_CLOCK__ programmed ADC clock.
  725. * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
  726. */
  727. #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
  728. ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
  729. ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
  730. ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \
  731. ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \
  732. ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \
  733. ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \
  734. ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \
  735. ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \
  736. ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \
  737. ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \
  738. ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \
  739. ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \
  740. ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \
  741. ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
  742. /**
  743. * @brief Verify the ADC resolution setting.
  744. * @param __RESOLUTION__ programmed ADC resolution.
  745. * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
  746. */
  747. #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
  748. ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
  749. ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
  750. ((__RESOLUTION__) == ADC_RESOLUTION_6B) )
  751. /**
  752. * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
  753. * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
  754. * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
  755. */
  756. #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
  757. ((__RESOLUTION__) == ADC_RESOLUTION_6B) )
  758. /**
  759. * @brief Verify the ADC converted data alignment.
  760. * @param __ALIGN__ programmed ADC converted data alignment.
  761. * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
  762. */
  763. #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
  764. ((__ALIGN__) == ADC_DATAALIGN_LEFT) )
  765. /**
  766. * @brief Verify the ADC scan mode.
  767. * @param __SCAN_MODE__ programmed ADC scan mode.
  768. * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
  769. */
  770. #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
  771. ((__SCAN_MODE__) == ADC_SCAN_ENABLE) )
  772. /**
  773. * @brief Verify the ADC edge trigger setting for regular group.
  774. * @param __EDGE__ programmed ADC edge trigger setting.
  775. * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
  776. */
  777. #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
  778. ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
  779. ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
  780. ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
  781. /**
  782. * @brief Verify the ADC regular conversions external trigger.
  783. * @param __HANDLE__ ADC handle
  784. * @param __REGTRIG__ programmed ADC regular conversions external trigger.
  785. * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
  786. */
  787. #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
  788. ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
  789. ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
  790. ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
  791. ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
  792. ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
  793. ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
  794. ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
  795. ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
  796. ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
  797. ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
  798. ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
  799. ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
  800. ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
  801. ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
  802. ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
  803. ((__REGTRIG__) == ADC_SOFTWARE_START) )
  804. /**
  805. * @brief Verify the ADC regular conversions check for converted data availability.
  806. * @param __EOC_SELECTION__ converted data availability check.
  807. * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
  808. */
  809. #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \
  810. ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) )
  811. /**
  812. * @brief Verify the ADC regular conversions overrun handling.
  813. * @param __OVR__ ADC regular conversions overrun handling.
  814. * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
  815. */
  816. #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
  817. ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )
  818. /**
  819. * @brief Verify the ADC conversions sampling time.
  820. * @param __TIME__ ADC conversions sampling time.
  821. * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
  822. */
  823. #if defined(ADC_SMPR1_SMPPLUS)
  824. #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
  825. ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \
  826. ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \
  827. ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \
  828. ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \
  829. ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \
  830. ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \
  831. ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
  832. ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) )
  833. #else
  834. #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
  835. ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \
  836. ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \
  837. ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \
  838. ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \
  839. ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \
  840. ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
  841. ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) )
  842. #endif
  843. /**
  844. * @brief Verify the ADC regular channel setting.
  845. * @param __CHANNEL__ programmed ADC regular channel.
  846. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
  847. */
  848. #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
  849. ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
  850. ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
  851. ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
  852. ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
  853. ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
  854. ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
  855. ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
  856. ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
  857. ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
  858. ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
  859. ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
  860. ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
  861. ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
  862. ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
  863. ((__CHANNEL__) == ADC_REGULAR_RANK_16) )
  864. /**
  865. * @}
  866. */
  867. /* Private constants ---------------------------------------------------------*/
  868. /** @defgroup ADC_Private_Constants ADC Private Constants
  869. * @{
  870. */
  871. /* Fixed timeout values for ADC conversion (including sampling time) */
  872. /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */
  873. /* Maximum conversion time is 12.5 + Maximum sampling time */
  874. /* or 12.5 + 640.5 = 653 ADC clock cycles */
  875. /* Minimum ADC Clock frequency is 0.14 MHz */
  876. /* Maximum conversion time is */
  877. /* 653 / 0.14 MHz = 4.66 ms */
  878. #define ADC_STOP_CONVERSION_TIMEOUT ( 5U) /*!< ADC stop time-out value */
  879. /* Delay for temperature sensor stabilization time. */
  880. /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
  881. /* Unit: us */
  882. #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
  883. /**
  884. * @}
  885. */
  886. /* Exported macro ------------------------------------------------------------*/
  887. /** @defgroup ADC_Exported_Macros ADC Exported Macros
  888. * @{
  889. */
  890. /* Macro for internal HAL driver usage, and possibly can be used into code of */
  891. /* final user. */
  892. /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
  893. * @{
  894. */
  895. /** @brief Reset ADC handle state.
  896. * @param __HANDLE__ ADC handle
  897. * @retval None
  898. */
  899. #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
  900. ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
  901. /**
  902. * @brief Enable ADC interrupt.
  903. * @param __HANDLE__ ADC handle
  904. * @param __INTERRUPT__ ADC Interrupt
  905. * This parameter can be one of the following values:
  906. * @arg @ref ADC_IT_RDY ADC Ready interrupt source
  907. * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
  908. * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
  909. * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  910. * @arg @ref ADC_IT_OVR ADC overrun interrupt source
  911. * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  912. * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  913. * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  914. * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  915. * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  916. * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
  917. * @retval None
  918. */
  919. #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
  920. (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
  921. /**
  922. * @brief Disable ADC interrupt.
  923. * @param __HANDLE__ ADC handle
  924. * @param __INTERRUPT__ ADC Interrupt
  925. * This parameter can be one of the following values:
  926. * @arg @ref ADC_IT_RDY ADC Ready interrupt source
  927. * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
  928. * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
  929. * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  930. * @arg @ref ADC_IT_OVR ADC overrun interrupt source
  931. * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  932. * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  933. * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  934. * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  935. * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  936. * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
  937. * @retval None
  938. */
  939. #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
  940. (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
  941. /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
  942. * @param __HANDLE__ ADC handle
  943. * @param __INTERRUPT__ ADC interrupt source to check
  944. * This parameter can be one of the following values:
  945. * @arg @ref ADC_IT_RDY ADC Ready interrupt source
  946. * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
  947. * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
  948. * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  949. * @arg @ref ADC_IT_OVR ADC overrun interrupt source
  950. * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  951. * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  952. * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  953. * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  954. * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  955. * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
  956. * @retval State of interruption (SET or RESET)
  957. */
  958. #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
  959. (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
  960. /**
  961. * @brief Check whether the specified ADC flag is set or not.
  962. * @param __HANDLE__ ADC handle
  963. * @param __FLAG__ ADC flag
  964. * This parameter can be one of the following values:
  965. * @arg @ref ADC_FLAG_RDY ADC Ready flag
  966. * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
  967. * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
  968. * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
  969. * @arg @ref ADC_FLAG_OVR ADC overrun flag
  970. * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
  971. * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
  972. * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
  973. * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
  974. * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
  975. * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
  976. * @retval State of flag (TRUE or FALSE).
  977. */
  978. #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
  979. ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
  980. /**
  981. * @brief Clear the specified ADC flag.
  982. * @param __HANDLE__ ADC handle
  983. * @param __FLAG__ ADC flag
  984. * This parameter can be one of the following values:
  985. * @arg @ref ADC_FLAG_RDY ADC Ready flag
  986. * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
  987. * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
  988. * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
  989. * @arg @ref ADC_FLAG_OVR ADC overrun flag
  990. * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
  991. * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
  992. * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
  993. * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
  994. * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
  995. * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
  996. * @retval None
  997. */
  998. /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
  999. #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
  1000. (((__HANDLE__)->Instance->ISR) = (__FLAG__))
  1001. /**
  1002. * @}
  1003. */
  1004. /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
  1005. * @{
  1006. */
  1007. /**
  1008. * @brief Helper macro to get ADC channel number in decimal format
  1009. * from literals ADC_CHANNEL_x.
  1010. * @note Example:
  1011. * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
  1012. * will return decimal number "4".
  1013. * @note The input can be a value from functions where a channel
  1014. * number is returned, either defined with number
  1015. * or with bitfield (only one bit must be set).
  1016. * @param __CHANNEL__ This parameter can be one of the following values:
  1017. * @arg @ref ADC_CHANNEL_0
  1018. * @arg @ref ADC_CHANNEL_1 (7)
  1019. * @arg @ref ADC_CHANNEL_2 (7)
  1020. * @arg @ref ADC_CHANNEL_3 (7)
  1021. * @arg @ref ADC_CHANNEL_4 (7)
  1022. * @arg @ref ADC_CHANNEL_5 (7)
  1023. * @arg @ref ADC_CHANNEL_6
  1024. * @arg @ref ADC_CHANNEL_7
  1025. * @arg @ref ADC_CHANNEL_8
  1026. * @arg @ref ADC_CHANNEL_9
  1027. * @arg @ref ADC_CHANNEL_10
  1028. * @arg @ref ADC_CHANNEL_11
  1029. * @arg @ref ADC_CHANNEL_12
  1030. * @arg @ref ADC_CHANNEL_13
  1031. * @arg @ref ADC_CHANNEL_14
  1032. * @arg @ref ADC_CHANNEL_15
  1033. * @arg @ref ADC_CHANNEL_16
  1034. * @arg @ref ADC_CHANNEL_17
  1035. * @arg @ref ADC_CHANNEL_18
  1036. * @arg @ref ADC_CHANNEL_VREFINT (1)
  1037. * @arg @ref ADC_CHANNEL_TEMPSENSOR (4)
  1038. * @arg @ref ADC_CHANNEL_VBAT (4)
  1039. * @arg @ref ADC_CHANNEL_DAC1CH1 (5)
  1040. * @arg @ref ADC_CHANNEL_DAC1CH2 (5)
  1041. * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  1042. * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  1043. * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  1044. * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
  1045. *
  1046. * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
  1047. * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
  1048. * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
  1049. * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
  1050. * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
  1051. * (6) On STM32L4, parameter available on devices with several ADC instances.\n
  1052. * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
  1053. * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
  1054. * @retval Value between Min_Data=0 and Max_Data=18
  1055. */
  1056. #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
  1057. __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
  1058. /**
  1059. * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
  1060. * from number in decimal format.
  1061. * @note Example:
  1062. * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
  1063. * will return a data equivalent to "ADC_CHANNEL_4".
  1064. * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
  1065. * @retval Returned value can be one of the following values:
  1066. * @arg @ref ADC_CHANNEL_0
  1067. * @arg @ref ADC_CHANNEL_1 (7)
  1068. * @arg @ref ADC_CHANNEL_2 (7)
  1069. * @arg @ref ADC_CHANNEL_3 (7)
  1070. * @arg @ref ADC_CHANNEL_4 (7)
  1071. * @arg @ref ADC_CHANNEL_5 (7)
  1072. * @arg @ref ADC_CHANNEL_6
  1073. * @arg @ref ADC_CHANNEL_7
  1074. * @arg @ref ADC_CHANNEL_8
  1075. * @arg @ref ADC_CHANNEL_9
  1076. * @arg @ref ADC_CHANNEL_10
  1077. * @arg @ref ADC_CHANNEL_11
  1078. * @arg @ref ADC_CHANNEL_12
  1079. * @arg @ref ADC_CHANNEL_13
  1080. * @arg @ref ADC_CHANNEL_14
  1081. * @arg @ref ADC_CHANNEL_15
  1082. * @arg @ref ADC_CHANNEL_16
  1083. * @arg @ref ADC_CHANNEL_17
  1084. * @arg @ref ADC_CHANNEL_18
  1085. * @arg @ref ADC_CHANNEL_VREFINT (1)
  1086. * @arg @ref ADC_CHANNEL_TEMPSENSOR (4)
  1087. * @arg @ref ADC_CHANNEL_VBAT (4)
  1088. * @arg @ref ADC_CHANNEL_DAC1CH1 (5)
  1089. * @arg @ref ADC_CHANNEL_DAC1CH2 (5)
  1090. * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  1091. * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  1092. * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  1093. * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
  1094. *
  1095. * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
  1096. * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
  1097. * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
  1098. * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
  1099. * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
  1100. * (6) On STM32L4, parameter available on devices with several ADC instances.\n
  1101. * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
  1102. * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
  1103. * (1, 2, 3, 4) For ADC channel read back from ADC register,
  1104. * comparison with internal channel parameter to be done
  1105. * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
  1106. */
  1107. #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
  1108. __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
  1109. /**
  1110. * @brief Helper macro to determine whether the selected channel
  1111. * corresponds to literal definitions of driver.
  1112. * @note The different literal definitions of ADC channels are:
  1113. * - ADC internal channel:
  1114. * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
  1115. * - ADC external channel (channel connected to a GPIO pin):
  1116. * ADC_CHANNEL_1, ADC_CHANNEL_2, ...
  1117. * @note The channel parameter must be a value defined from literal
  1118. * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
  1119. * ADC_CHANNEL_TEMPSENSOR, ...),
  1120. * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
  1121. * must not be a value from functions where a channel number is
  1122. * returned from ADC registers,
  1123. * because internal and external channels share the same channel
  1124. * number in ADC registers. The differentiation is made only with
  1125. * parameters definitions of driver.
  1126. * @param __CHANNEL__ This parameter can be one of the following values:
  1127. * @arg @ref ADC_CHANNEL_0
  1128. * @arg @ref ADC_CHANNEL_1 (7)
  1129. * @arg @ref ADC_CHANNEL_2 (7)
  1130. * @arg @ref ADC_CHANNEL_3 (7)
  1131. * @arg @ref ADC_CHANNEL_4 (7)
  1132. * @arg @ref ADC_CHANNEL_5 (7)
  1133. * @arg @ref ADC_CHANNEL_6
  1134. * @arg @ref ADC_CHANNEL_7
  1135. * @arg @ref ADC_CHANNEL_8
  1136. * @arg @ref ADC_CHANNEL_9
  1137. * @arg @ref ADC_CHANNEL_10
  1138. * @arg @ref ADC_CHANNEL_11
  1139. * @arg @ref ADC_CHANNEL_12
  1140. * @arg @ref ADC_CHANNEL_13
  1141. * @arg @ref ADC_CHANNEL_14
  1142. * @arg @ref ADC_CHANNEL_15
  1143. * @arg @ref ADC_CHANNEL_16
  1144. * @arg @ref ADC_CHANNEL_17
  1145. * @arg @ref ADC_CHANNEL_18
  1146. * @arg @ref ADC_CHANNEL_VREFINT (1)
  1147. * @arg @ref ADC_CHANNEL_TEMPSENSOR (4)
  1148. * @arg @ref ADC_CHANNEL_VBAT (4)
  1149. * @arg @ref ADC_CHANNEL_DAC1CH1 (5)
  1150. * @arg @ref ADC_CHANNEL_DAC1CH2 (5)
  1151. * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  1152. * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  1153. * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  1154. * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
  1155. *
  1156. * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
  1157. * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
  1158. * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
  1159. * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
  1160. * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
  1161. * (6) On STM32L4, parameter available on devices with several ADC instances.\n
  1162. * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
  1163. * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
  1164. * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
  1165. * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
  1166. */
  1167. #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
  1168. __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
  1169. /**
  1170. * @brief Helper macro to convert a channel defined from parameter
  1171. * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
  1172. * ADC_CHANNEL_TEMPSENSOR, ...),
  1173. * to its equivalent parameter definition of a ADC external channel
  1174. * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
  1175. * @note The channel parameter can be, additionally to a value
  1176. * defined from parameter definition of a ADC internal channel
  1177. * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
  1178. * a value defined from parameter definition of
  1179. * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
  1180. * or a value from functions where a channel number is returned
  1181. * from ADC registers.
  1182. * @param __CHANNEL__ This parameter can be one of the following values:
  1183. * @arg @ref ADC_CHANNEL_0
  1184. * @arg @ref ADC_CHANNEL_1 (7)
  1185. * @arg @ref ADC_CHANNEL_2 (7)
  1186. * @arg @ref ADC_CHANNEL_3 (7)
  1187. * @arg @ref ADC_CHANNEL_4 (7)
  1188. * @arg @ref ADC_CHANNEL_5 (7)
  1189. * @arg @ref ADC_CHANNEL_6
  1190. * @arg @ref ADC_CHANNEL_7
  1191. * @arg @ref ADC_CHANNEL_8
  1192. * @arg @ref ADC_CHANNEL_9
  1193. * @arg @ref ADC_CHANNEL_10
  1194. * @arg @ref ADC_CHANNEL_11
  1195. * @arg @ref ADC_CHANNEL_12
  1196. * @arg @ref ADC_CHANNEL_13
  1197. * @arg @ref ADC_CHANNEL_14
  1198. * @arg @ref ADC_CHANNEL_15
  1199. * @arg @ref ADC_CHANNEL_16
  1200. * @arg @ref ADC_CHANNEL_17
  1201. * @arg @ref ADC_CHANNEL_18
  1202. * @arg @ref ADC_CHANNEL_VREFINT (1)
  1203. * @arg @ref ADC_CHANNEL_TEMPSENSOR (4)
  1204. * @arg @ref ADC_CHANNEL_VBAT (4)
  1205. * @arg @ref ADC_CHANNEL_DAC1CH1 (5)
  1206. * @arg @ref ADC_CHANNEL_DAC1CH2 (5)
  1207. * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  1208. * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  1209. * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  1210. * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
  1211. *
  1212. * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
  1213. * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
  1214. * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
  1215. * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
  1216. * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
  1217. * (6) On STM32L4, parameter available on devices with several ADC instances.\n
  1218. * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
  1219. * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
  1220. * @retval Returned value can be one of the following values:
  1221. * @arg @ref ADC_CHANNEL_0
  1222. * @arg @ref ADC_CHANNEL_1
  1223. * @arg @ref ADC_CHANNEL_2
  1224. * @arg @ref ADC_CHANNEL_3
  1225. * @arg @ref ADC_CHANNEL_4
  1226. * @arg @ref ADC_CHANNEL_5
  1227. * @arg @ref ADC_CHANNEL_6
  1228. * @arg @ref ADC_CHANNEL_7
  1229. * @arg @ref ADC_CHANNEL_8
  1230. * @arg @ref ADC_CHANNEL_9
  1231. * @arg @ref ADC_CHANNEL_10
  1232. * @arg @ref ADC_CHANNEL_11
  1233. * @arg @ref ADC_CHANNEL_12
  1234. * @arg @ref ADC_CHANNEL_13
  1235. * @arg @ref ADC_CHANNEL_14
  1236. * @arg @ref ADC_CHANNEL_15
  1237. * @arg @ref ADC_CHANNEL_16
  1238. * @arg @ref ADC_CHANNEL_17
  1239. * @arg @ref ADC_CHANNEL_18
  1240. */
  1241. #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
  1242. __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
  1243. /**
  1244. * @brief Helper macro to determine whether the internal channel
  1245. * selected is available on the ADC instance selected.
  1246. * @note The channel parameter must be a value defined from parameter
  1247. * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
  1248. * ADC_CHANNEL_TEMPSENSOR, ...),
  1249. * must not be a value defined from parameter definition of
  1250. * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
  1251. * or a value from functions where a channel number is
  1252. * returned from ADC registers,
  1253. * because internal and external channels share the same channel
  1254. * number in ADC registers. The differentiation is made only with
  1255. * parameters definitions of driver.
  1256. * @param __ADC_INSTANCE__ ADC instance
  1257. * @param __CHANNEL__ This parameter can be one of the following values:
  1258. * @arg @ref ADC_CHANNEL_VREFINT (1)
  1259. * @arg @ref ADC_CHANNEL_TEMPSENSOR (4)
  1260. * @arg @ref ADC_CHANNEL_VBAT (4)
  1261. * @arg @ref ADC_CHANNEL_DAC1CH1 (5)
  1262. * @arg @ref ADC_CHANNEL_DAC1CH2 (5)
  1263. * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  1264. * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  1265. * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  1266. * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
  1267. *
  1268. * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
  1269. * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
  1270. * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
  1271. * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
  1272. * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
  1273. * (6) On STM32L4, parameter available on devices with several ADC instances.
  1274. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
  1275. * Value "1" if the internal channel selected is available on the ADC instance selected.
  1276. */
  1277. #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
  1278. __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
  1279. #if defined(ADC_MULTIMODE_SUPPORT)
  1280. /**
  1281. * @brief Helper macro to get the ADC multimode conversion data of ADC master
  1282. * or ADC slave from raw value with both ADC conversion data concatenated.
  1283. * @note This macro is intended to be used when multimode transfer by DMA
  1284. * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
  1285. * In this case the transferred data need to processed with this macro
  1286. * to separate the conversion data of ADC master and ADC slave.
  1287. * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
  1288. * @arg @ref LL_ADC_MULTI_MASTER
  1289. * @arg @ref LL_ADC_MULTI_SLAVE
  1290. * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
  1291. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
  1292. */
  1293. #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
  1294. __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
  1295. #endif
  1296. /**
  1297. * @brief Helper macro to select the ADC common instance
  1298. * to which is belonging the selected ADC instance.
  1299. * @note ADC common register instance can be used for:
  1300. * - Set parameters common to several ADC instances
  1301. * - Multimode (for devices with several ADC instances)
  1302. * Refer to functions having argument "ADCxy_COMMON" as parameter.
  1303. * @param __ADCx__ ADC instance
  1304. * @retval ADC common register instance
  1305. */
  1306. #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \
  1307. __LL_ADC_COMMON_INSTANCE((__ADCx__))
  1308. /**
  1309. * @brief Helper macro to check if all ADC instances sharing the same
  1310. * ADC common instance are disabled.
  1311. * @note This check is required by functions with setting conditioned to
  1312. * ADC state:
  1313. * All ADC instances of the ADC common group must be disabled.
  1314. * Refer to functions having argument "ADCxy_COMMON" as parameter.
  1315. * @note On devices with only 1 ADC common instance, parameter of this macro
  1316. * is useless and can be ignored (parameter kept for compatibility
  1317. * with devices featuring several ADC common instances).
  1318. * @param __ADCXY_COMMON__ ADC common instance
  1319. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  1320. * @retval Value "0" if all ADC instances sharing the same ADC common instance
  1321. * are disabled.
  1322. * Value "1" if at least one ADC instance sharing the same ADC common instance
  1323. * is enabled.
  1324. */
  1325. #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
  1326. __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
  1327. /**
  1328. * @brief Helper macro to define the ADC conversion data full-scale digital
  1329. * value corresponding to the selected ADC resolution.
  1330. * @note ADC conversion data full-scale corresponds to voltage range
  1331. * determined by analog voltage references Vref+ and Vref-
  1332. * (refer to reference manual).
  1333. * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
  1334. * @arg @ref ADC_RESOLUTION_12B
  1335. * @arg @ref ADC_RESOLUTION_10B
  1336. * @arg @ref ADC_RESOLUTION_8B
  1337. * @arg @ref ADC_RESOLUTION_6B
  1338. * @retval ADC conversion data equivalent voltage value (unit: mVolt)
  1339. */
  1340. #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
  1341. __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
  1342. /**
  1343. * @brief Helper macro to convert the ADC conversion data from
  1344. * a resolution to another resolution.
  1345. * @param __DATA__ ADC conversion data to be converted
  1346. * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
  1347. * This parameter can be one of the following values:
  1348. * @arg @ref ADC_RESOLUTION_12B
  1349. * @arg @ref ADC_RESOLUTION_10B
  1350. * @arg @ref ADC_RESOLUTION_8B
  1351. * @arg @ref ADC_RESOLUTION_6B
  1352. * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
  1353. * This parameter can be one of the following values:
  1354. * @arg @ref ADC_RESOLUTION_12B
  1355. * @arg @ref ADC_RESOLUTION_10B
  1356. * @arg @ref ADC_RESOLUTION_8B
  1357. * @arg @ref ADC_RESOLUTION_6B
  1358. * @retval ADC conversion data to the requested resolution
  1359. */
  1360. #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
  1361. __ADC_RESOLUTION_CURRENT__,\
  1362. __ADC_RESOLUTION_TARGET__) \
  1363. __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
  1364. (__ADC_RESOLUTION_CURRENT__),\
  1365. (__ADC_RESOLUTION_TARGET__))
  1366. /**
  1367. * @brief Helper macro to calculate the voltage (unit: mVolt)
  1368. * corresponding to a ADC conversion data (unit: digital value).
  1369. * @note Analog reference voltage (Vref+) must be either known from
  1370. * user board environment or can be calculated using ADC measurement
  1371. * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
  1372. * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
  1373. * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
  1374. * (unit: digital value).
  1375. * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
  1376. * @arg @ref ADC_RESOLUTION_12B
  1377. * @arg @ref ADC_RESOLUTION_10B
  1378. * @arg @ref ADC_RESOLUTION_8B
  1379. * @arg @ref ADC_RESOLUTION_6B
  1380. * @retval ADC conversion data equivalent voltage value (unit: mVolt)
  1381. */
  1382. #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
  1383. __ADC_DATA__,\
  1384. __ADC_RESOLUTION__) \
  1385. __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
  1386. (__ADC_DATA__),\
  1387. (__ADC_RESOLUTION__))
  1388. /**
  1389. * @brief Helper macro to calculate analog reference voltage (Vref+)
  1390. * (unit: mVolt) from ADC conversion data of internal voltage
  1391. * reference VrefInt.
  1392. * @note Computation is using VrefInt calibration value
  1393. * stored in system memory for each device during production.
  1394. * @note This voltage depends on user board environment: voltage level
  1395. * connected to pin Vref+.
  1396. * On devices with small package, the pin Vref+ is not present
  1397. * and internally bonded to pin Vdda.
  1398. * @note On this STM32 serie, calibration data of internal voltage reference
  1399. * VrefInt corresponds to a resolution of 12 bits,
  1400. * this is the recommended ADC resolution to convert voltage of
  1401. * internal voltage reference VrefInt.
  1402. * Otherwise, this macro performs the processing to scale
  1403. * ADC conversion data to 12 bits.
  1404. * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
  1405. * of internal voltage reference VrefInt (unit: digital value).
  1406. * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
  1407. * @arg @ref ADC_RESOLUTION_12B
  1408. * @arg @ref ADC_RESOLUTION_10B
  1409. * @arg @ref ADC_RESOLUTION_8B
  1410. * @arg @ref ADC_RESOLUTION_6B
  1411. * @retval Analog reference voltage (unit: mV)
  1412. */
  1413. #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
  1414. __ADC_RESOLUTION__) \
  1415. __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
  1416. (__ADC_RESOLUTION__))
  1417. /**
  1418. * @brief Helper macro to calculate the temperature (unit: degree Celsius)
  1419. * from ADC conversion data of internal temperature sensor.
  1420. * @note Computation is using temperature sensor calibration values
  1421. * stored in system memory for each device during production.
  1422. * @note Calculation formula:
  1423. * Temperature = ((TS_ADC_DATA - TS_CAL1)
  1424. * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
  1425. * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
  1426. * with TS_ADC_DATA = temperature sensor raw data measured by ADC
  1427. * Avg_Slope = (TS_CAL2 - TS_CAL1)
  1428. * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
  1429. * TS_CAL1 = equivalent TS_ADC_DATA at temperature
  1430. * TEMP_DEGC_CAL1 (calibrated in factory)
  1431. * TS_CAL2 = equivalent TS_ADC_DATA at temperature
  1432. * TEMP_DEGC_CAL2 (calibrated in factory)
  1433. * Caution: Calculation relevancy under reserve that calibration
  1434. * parameters are correct (address and data).
  1435. * To calculate temperature using temperature sensor
  1436. * datasheet typical values (generic values less, therefore
  1437. * less accurate than calibrated values),
  1438. * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
  1439. * @note As calculation input, the analog reference voltage (Vref+) must be
  1440. * defined as it impacts the ADC LSB equivalent voltage.
  1441. * @note Analog reference voltage (Vref+) must be either known from
  1442. * user board environment or can be calculated using ADC measurement
  1443. * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
  1444. * @note On this STM32 serie, calibration data of temperature sensor
  1445. * corresponds to a resolution of 12 bits,
  1446. * this is the recommended ADC resolution to convert voltage of
  1447. * temperature sensor.
  1448. * Otherwise, this macro performs the processing to scale
  1449. * ADC conversion data to 12 bits.
  1450. * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
  1451. * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
  1452. * temperature sensor (unit: digital value).
  1453. * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
  1454. * sensor voltage has been measured.
  1455. * This parameter can be one of the following values:
  1456. * @arg @ref ADC_RESOLUTION_12B
  1457. * @arg @ref ADC_RESOLUTION_10B
  1458. * @arg @ref ADC_RESOLUTION_8B
  1459. * @arg @ref ADC_RESOLUTION_6B
  1460. * @retval Temperature (unit: degree Celsius)
  1461. */
  1462. #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
  1463. __TEMPSENSOR_ADC_DATA__,\
  1464. __ADC_RESOLUTION__) \
  1465. __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
  1466. (__TEMPSENSOR_ADC_DATA__),\
  1467. (__ADC_RESOLUTION__))
  1468. /**
  1469. * @brief Helper macro to calculate the temperature (unit: degree Celsius)
  1470. * from ADC conversion data of internal temperature sensor.
  1471. * @note Computation is using temperature sensor typical values
  1472. * (refer to device datasheet).
  1473. * @note Calculation formula:
  1474. * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
  1475. * / Avg_Slope + CALx_TEMP
  1476. * with TS_ADC_DATA = temperature sensor raw data measured by ADC
  1477. * (unit: digital value)
  1478. * Avg_Slope = temperature sensor slope
  1479. * (unit: uV/Degree Celsius)
  1480. * TS_TYP_CALx_VOLT = temperature sensor digital value at
  1481. * temperature CALx_TEMP (unit: mV)
  1482. * Caution: Calculation relevancy under reserve the temperature sensor
  1483. * of the current device has characteristics in line with
  1484. * datasheet typical values.
  1485. * If temperature sensor calibration values are available on
  1486. * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
  1487. * temperature calculation will be more accurate using
  1488. * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
  1489. * @note As calculation input, the analog reference voltage (Vref+) must be
  1490. * defined as it impacts the ADC LSB equivalent voltage.
  1491. * @note Analog reference voltage (Vref+) must be either known from
  1492. * user board environment or can be calculated using ADC measurement
  1493. * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
  1494. * @note ADC measurement data must correspond to a resolution of 12bits
  1495. * (full scale digital value 4095). If not the case, the data must be
  1496. * preliminarily rescaled to an equivalent resolution of 12 bits.
  1497. * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
  1498. * On STM32L4, refer to device datasheet parameter "Avg_Slope".
  1499. * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
  1500. * On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
  1501. * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
  1502. * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
  1503. * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
  1504. * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
  1505. * This parameter can be one of the following values:
  1506. * @arg @ref ADC_RESOLUTION_12B
  1507. * @arg @ref ADC_RESOLUTION_10B
  1508. * @arg @ref ADC_RESOLUTION_8B
  1509. * @arg @ref ADC_RESOLUTION_6B
  1510. * @retval Temperature (unit: degree Celsius)
  1511. */
  1512. #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
  1513. __TEMPSENSOR_TYP_CALX_V__,\
  1514. __TEMPSENSOR_CALX_TEMP__,\
  1515. __VREFANALOG_VOLTAGE__,\
  1516. __TEMPSENSOR_ADC_DATA__,\
  1517. __ADC_RESOLUTION__) \
  1518. __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
  1519. (__TEMPSENSOR_TYP_CALX_V__),\
  1520. (__TEMPSENSOR_CALX_TEMP__),\
  1521. (__VREFANALOG_VOLTAGE__),\
  1522. (__TEMPSENSOR_ADC_DATA__),\
  1523. (__ADC_RESOLUTION__))
  1524. /**
  1525. * @}
  1526. */
  1527. /**
  1528. * @}
  1529. */
  1530. /* Include ADC HAL Extended module */
  1531. #include "stm32l4xx_hal_adc_ex.h"
  1532. /* Exported functions --------------------------------------------------------*/
  1533. /** @addtogroup ADC_Exported_Functions
  1534. * @{
  1535. */
  1536. /** @addtogroup ADC_Exported_Functions_Group1
  1537. * @brief Initialization and Configuration functions
  1538. * @{
  1539. */
  1540. /* Initialization and de-initialization functions ****************************/
  1541. HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
  1542. HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
  1543. void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
  1544. void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
  1545. /**
  1546. * @}
  1547. */
  1548. /** @addtogroup ADC_Exported_Functions_Group2
  1549. * @brief IO operation functions
  1550. * @{
  1551. */
  1552. /* IO operation functions *****************************************************/
  1553. /* Blocking mode: Polling */
  1554. HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
  1555. HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
  1556. HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
  1557. HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
  1558. /* Non-blocking mode: Interruption */
  1559. HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
  1560. HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
  1561. /* Non-blocking mode: DMA */
  1562. HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
  1563. HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
  1564. /* ADC retrieve conversion value intended to be used with polling or interruption */
  1565. uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
  1566. /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
  1567. void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
  1568. void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
  1569. void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
  1570. void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
  1571. void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
  1572. /**
  1573. * @}
  1574. */
  1575. /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
  1576. * @brief Peripheral Control functions
  1577. * @{
  1578. */
  1579. /* Peripheral Control functions ***********************************************/
  1580. HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
  1581. HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
  1582. /**
  1583. * @}
  1584. */
  1585. /* Peripheral State functions *************************************************/
  1586. /** @addtogroup ADC_Exported_Functions_Group4
  1587. * @{
  1588. */
  1589. uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
  1590. uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
  1591. /**
  1592. * @}
  1593. */
  1594. /**
  1595. * @}
  1596. */
  1597. /* Private functions -----------------------------------------------------------*/
  1598. /** @addtogroup ADC_Private_Functions ADC Private Functions
  1599. * @{
  1600. */
  1601. HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
  1602. HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
  1603. HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
  1604. void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
  1605. void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
  1606. void ADC_DMAError(DMA_HandleTypeDef *hdma);
  1607. /**
  1608. * @}
  1609. */
  1610. /**
  1611. * @}
  1612. */
  1613. /**
  1614. * @}
  1615. */
  1616. #ifdef __cplusplus
  1617. }
  1618. #endif
  1619. #endif /* __STM32L4xx_HAL_ADC_H */
  1620. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/