nixie.rs 22 KB

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  1. use core::ops::DerefMut;
  2. use cortex_m::interrupt::free;
  3. use stm32l4xx_hal::{
  4. prelude::{
  5. _embedded_hal_blocking_i2c_Read, _embedded_hal_blocking_i2c_Write,
  6. _embedded_hal_blocking_i2c_WriteRead,
  7. },
  8. timer::Event,
  9. };
  10. use crate::{ds3231, pca9685};
  11. pub const DS3231_ADDR: u8 = 0x68;
  12. pub const TUSB322_ADDR: u8 = 0x47;
  13. pub const PCA9685_ADDR_1: u8 = 0x41;
  14. pub const PCA9685_ADDR_2: u8 = 0x42;
  15. pub const PCA9685_ADDR_3: u8 = 0x43;
  16. pub const PCA9685_ALL_CALL: u8 = 0x70; // Default enabled
  17. pub const PCA9685_SUB_CALL_1: u8 = 0x71; // Default disabled
  18. pub const PCA9685_SUB_CALL_2: u8 = 0x72; // Default disabled
  19. pub const PCA9685_SUB_CALL_3: u8 = 0x73; // Default disabled
  20. pub const REFRESH_RATE_HZ: u32 = 1000;
  21. const DIGIT_FADE_DURATION_US: u32 = 1_000_000;
  22. const DIGIT_RNG_FADE_DURATION_US: u32 = 200_000;
  23. const DIGIT_RNG_FADE_ITERATIONS: usize = 20;
  24. const DIGIT_RNG_REFRESH_INTERVAL: usize = 60;
  25. const DIGIT_RNG_REFRESH_VARIANCE: usize = 30;
  26. const DOT_MIN_BRIGHTNESS: u32 = 256;
  27. const DOT_MAX_BRIGHTNESS: u32 = 640;
  28. const DOT_FADE_DURATION_US: u32 = 1_000_000;
  29. const DIGIT_MAX_BRIGHTNESS: u32 = 4096;
  30. const DIGIT_MIN_BRIGHTNESS: u32 = 0;
  31. const NUM_TUBES: usize = 4;
  32. const NUM_DIGITS: usize = 10;
  33. const MAP_DOT_ADDR: u8 = PCA9685_ADDR_2;
  34. const MAP_DOT_PIN: u8 = 15;
  35. const MAP_ADDR: usize = 0;
  36. const MAP_PIN: usize = 1;
  37. struct DigitToPin {
  38. address: u8,
  39. pin: usize,
  40. }
  41. struct PwmDriver {
  42. digit: [DigitToPin; 10],
  43. }
  44. struct PwmOutputMap {
  45. driver: [PwmDriver; 4],
  46. dot_address: u8,
  47. dot_pin: usize,
  48. }
  49. static TUBE_MAPPING: PwmOutputMap = {
  50. PwmOutputMap {
  51. driver: [
  52. PwmDriver {
  53. digit: [
  54. DigitToPin {
  55. address: PCA9685_ADDR_1,
  56. pin: 8,
  57. }, // Tube 0 Digit 0
  58. DigitToPin {
  59. address: PCA9685_ADDR_1,
  60. pin: 9,
  61. }, // Tube 0 Digit 1
  62. DigitToPin {
  63. address: PCA9685_ADDR_1,
  64. pin: 10,
  65. }, // Tube 0 Digit 2
  66. DigitToPin {
  67. address: PCA9685_ADDR_1,
  68. pin: 12,
  69. }, // Tube 0 Digit 3
  70. DigitToPin {
  71. address: PCA9685_ADDR_1,
  72. pin: 15,
  73. }, // Tube 0 Digit 4
  74. DigitToPin {
  75. address: PCA9685_ADDR_1,
  76. pin: 14,
  77. }, // Tube 0 Digit 5
  78. DigitToPin {
  79. address: PCA9685_ADDR_1,
  80. pin: 11,
  81. }, // Tube 0 Digit 6
  82. DigitToPin {
  83. address: PCA9685_ADDR_1,
  84. pin: 0,
  85. }, // Tube 0 Digit 7
  86. DigitToPin {
  87. address: PCA9685_ADDR_1,
  88. pin: 1,
  89. }, // Tube 0 Digit 8
  90. DigitToPin {
  91. address: PCA9685_ADDR_1,
  92. pin: 13,
  93. }, // Tube 0 Digit 9
  94. ],
  95. },
  96. PwmDriver {
  97. digit: [
  98. DigitToPin {
  99. address: PCA9685_ADDR_1,
  100. pin: 5,
  101. }, // Tube 1 Digit 0
  102. DigitToPin {
  103. address: PCA9685_ADDR_1,
  104. pin: 6,
  105. }, // Tube 1 Digit 1
  106. DigitToPin {
  107. address: PCA9685_ADDR_1,
  108. pin: 7,
  109. }, // Tube 1 Digit 2
  110. DigitToPin {
  111. address: PCA9685_ADDR_1,
  112. pin: 2,
  113. }, // Tube 1 Digit 3
  114. DigitToPin {
  115. address: PCA9685_ADDR_2,
  116. pin: 4,
  117. }, // Tube 1 Digit 4
  118. DigitToPin {
  119. address: PCA9685_ADDR_2,
  120. pin: 1,
  121. }, // Tube 1 Digit 5
  122. DigitToPin {
  123. address: PCA9685_ADDR_1,
  124. pin: 4,
  125. }, // Tube 1 Digit 6
  126. DigitToPin {
  127. address: PCA9685_ADDR_2,
  128. pin: 2,
  129. }, // Tube 1 Digit 7
  130. DigitToPin {
  131. address: PCA9685_ADDR_2,
  132. pin: 3,
  133. }, // Tube 1 Digit 8
  134. DigitToPin {
  135. address: PCA9685_ADDR_1,
  136. pin: 3,
  137. }, // Tube 1 Digit 9
  138. ],
  139. },
  140. PwmDriver {
  141. digit: [
  142. DigitToPin {
  143. address: PCA9685_ADDR_3,
  144. pin: 8,
  145. }, // Tube 2 Digit 0
  146. DigitToPin {
  147. address: PCA9685_ADDR_3,
  148. pin: 9,
  149. }, // Tube 2 Digit 1
  150. DigitToPin {
  151. address: PCA9685_ADDR_3,
  152. pin: 10,
  153. }, // Tube 2 Digit 2
  154. DigitToPin {
  155. address: PCA9685_ADDR_3,
  156. pin: 12,
  157. }, // Tube 2 Digit 3
  158. DigitToPin {
  159. address: PCA9685_ADDR_2,
  160. pin: 12,
  161. }, // Tube 2 Digit 4
  162. DigitToPin {
  163. address: PCA9685_ADDR_2,
  164. pin: 13,
  165. }, // Tube 2 Digit 5
  166. DigitToPin {
  167. address: PCA9685_ADDR_3,
  168. pin: 11,
  169. }, // Tube 2 Digit 6
  170. DigitToPin {
  171. address: PCA9685_ADDR_2,
  172. pin: 14,
  173. }, // Tube 2 Digit 7
  174. DigitToPin {
  175. address: PCA9685_ADDR_2,
  176. pin: 11,
  177. }, // Tube 2 Digit 8
  178. DigitToPin {
  179. address: PCA9685_ADDR_3,
  180. pin: 13,
  181. }, // Tube 2 Digit 9
  182. ],
  183. },
  184. PwmDriver {
  185. digit: [
  186. DigitToPin {
  187. address: PCA9685_ADDR_3,
  188. pin: 5,
  189. }, // Tube 3 Digit 0
  190. DigitToPin {
  191. address: PCA9685_ADDR_3,
  192. pin: 6,
  193. }, // Tube 3 Digit 1
  194. DigitToPin {
  195. address: PCA9685_ADDR_3,
  196. pin: 7,
  197. }, // Tube 3 Digit 2
  198. DigitToPin {
  199. address: PCA9685_ADDR_3,
  200. pin: 2,
  201. }, // Tube 3 Digit 3
  202. DigitToPin {
  203. address: PCA9685_ADDR_3,
  204. pin: 14,
  205. }, // Tube 3 Digit 4
  206. DigitToPin {
  207. address: PCA9685_ADDR_3,
  208. pin: 15,
  209. }, // Tube 3 Digit 5
  210. DigitToPin {
  211. address: PCA9685_ADDR_3,
  212. pin: 4,
  213. }, // Tube 3 Digit 6
  214. DigitToPin {
  215. address: PCA9685_ADDR_3,
  216. pin: 1,
  217. }, // Tube 3 Digit 7
  218. DigitToPin {
  219. address: PCA9685_ADDR_3,
  220. pin: 0,
  221. }, // Tube 3 Digit 8
  222. DigitToPin {
  223. address: PCA9685_ADDR_3,
  224. pin: 3,
  225. }, // Tube 3 Digit 9
  226. ],
  227. },
  228. ],
  229. dot_address: PCA9685_ADDR_2,
  230. dot_pin: 15,
  231. }
  232. };
  233. #[derive(PartialEq)]
  234. enum State {
  235. Idle,
  236. Incrementing,
  237. Decrementing,
  238. }
  239. struct Digit {
  240. state: State,
  241. value: u32,
  242. pwm_start: u32,
  243. pwm_end: u32,
  244. updated: bool,
  245. }
  246. impl Digit {
  247. const fn default() -> Self {
  248. Self {
  249. state: State::Idle,
  250. value: 0,
  251. pwm_start: 0,
  252. pwm_end: 0,
  253. updated: false,
  254. }
  255. }
  256. }
  257. struct Tube {
  258. digits: [Digit; NUM_DIGITS],
  259. last_active_digit: Option<usize>,
  260. refresh_last_digit: Option<usize>,
  261. refresh_active: bool,
  262. }
  263. impl Tube {
  264. const fn default() -> Self {
  265. const DIGIT_INIT: Digit = Digit::default();
  266. Self {
  267. digits: [DIGIT_INIT; 10],
  268. last_active_digit: None,
  269. refresh_last_digit: None,
  270. refresh_active: false,
  271. }
  272. }
  273. }
  274. struct Clock {
  275. tubes: [Tube; NUM_TUBES],
  276. dot: Digit,
  277. fade_duration: u32,
  278. }
  279. impl Clock {
  280. const fn default() -> Self {
  281. const TUBE_INIT: Tube = Tube::default();
  282. Self {
  283. tubes: [TUBE_INIT; NUM_TUBES],
  284. dot: Digit::default(),
  285. fade_duration: 0,
  286. }
  287. }
  288. }
  289. static mut CLOCK: Clock = Clock::default();
  290. pub fn fade_in_out_digit(tube: usize, digit: Option<usize>, fade_duration: u32, refresh_cmd: bool) {
  291. unsafe {
  292. // If the tube is in the middle of a refresh sequence and a call comes
  293. // in to update the tube digit (for time), override the last value of
  294. // the refresh sequence with the new digit.
  295. if CLOCK.tubes[tube].refresh_active && !refresh_cmd {
  296. CLOCK.tubes[tube].refresh_last_digit = digit;
  297. }
  298. // Dont update if actively refreshing tube unless RngUpdate is set
  299. if (!CLOCK.tubes[tube].refresh_active && !refresh_cmd) || refresh_cmd {
  300. // Fade out all digits
  301. for digit in 0..NUM_DIGITS {
  302. if CLOCK.tubes[tube].digits[digit].value != DIGIT_MIN_BRIGHTNESS {
  303. CLOCK.tubes[tube].digits[digit].state = State::Decrementing;
  304. }
  305. }
  306. // Fade in the specified digit
  307. if let Some(digit) = digit {
  308. if CLOCK.tubes[tube].digits[digit].value != DIGIT_MAX_BRIGHTNESS {
  309. CLOCK.tubes[tube].digits[digit].state = State::Incrementing;
  310. }
  311. }
  312. CLOCK.tubes[tube].last_active_digit = digit;
  313. CLOCK.fade_duration = fade_duration;
  314. }
  315. }
  316. }
  317. pub fn rtc_tick<T>(i2c: &mut T)
  318. where
  319. T: _embedded_hal_blocking_i2c_WriteRead
  320. + _embedded_hal_blocking_i2c_Read
  321. + _embedded_hal_blocking_i2c_Write,
  322. {
  323. static mut STARTUP: bool = true;
  324. static mut PREV_MINUTE: u32 = 0;
  325. static mut PREV_HOUR: u32 = 0;
  326. let (second, minute, hour) = ds3231::get_time(DS3231_ADDR, i2c);
  327. let (weekday, day, month, _, _) = ds3231::get_date(DS3231_ADDR, i2c);
  328. let hour = if ds3231::in_dst(weekday, day, month, hour) {
  329. (hour + 1) % 12
  330. } else {
  331. hour % 12
  332. };
  333. let hour = if hour == 0 { 12 } else { hour };
  334. unsafe {
  335. if STARTUP || PREV_HOUR / 10 != hour / 10 {
  336. fade_in_out_digit(
  337. 0,
  338. if hour / 10 != 0 {
  339. Some((hour / 10) as usize)
  340. } else {
  341. None
  342. },
  343. DIGIT_FADE_DURATION_US,
  344. false,
  345. )
  346. }
  347. if STARTUP || PREV_HOUR % 10 != hour % 10 {
  348. fade_in_out_digit(
  349. 1,
  350. Some((hour % 10) as usize),
  351. DIGIT_FADE_DURATION_US,
  352. false
  353. );
  354. }
  355. if STARTUP || PREV_MINUTE / 10 != minute / 10 {
  356. fade_in_out_digit(
  357. 2,
  358. Some((minute / 10) as usize),
  359. DIGIT_FADE_DURATION_US,
  360. false,
  361. );
  362. }
  363. if STARTUP || PREV_MINUTE % 10 != minute % 10 {
  364. fade_in_out_digit(
  365. 3,
  366. Some((minute % 10) as usize),
  367. DIGIT_FADE_DURATION_US,
  368. false,
  369. );
  370. }
  371. CLOCK.dot.state = match second % 2 {
  372. 0 => State::Incrementing,
  373. 1 => State::Decrementing,
  374. _ => State::Idle,
  375. };
  376. PREV_MINUTE = minute;
  377. PREV_HOUR = hour;
  378. STARTUP = false;
  379. free(|cs| {
  380. let mut timer_ref = super::REFRESH_TIMER.borrow(cs).borrow_mut();
  381. if let Some(ref mut timer) = timer_ref.deref_mut() {
  382. timer.listen(Event::TimeOut);
  383. }
  384. })
  385. }
  386. }
  387. pub fn refresh_tick<T>(i2c: &mut T)
  388. where
  389. T: _embedded_hal_blocking_i2c_WriteRead
  390. + _embedded_hal_blocking_i2c_Read
  391. + _embedded_hal_blocking_i2c_Write,
  392. {
  393. let mut pending_refresh: bool = false;
  394. unsafe {
  395. let ticks = CLOCK.fade_duration / REFRESH_RATE_HZ;
  396. let steps = ((DIGIT_MAX_BRIGHTNESS - DIGIT_MIN_BRIGHTNESS) + ticks - 1) / ticks;
  397. CLOCK.tubes.iter_mut().for_each(|tube| {
  398. tube.digits.iter_mut().for_each(|digit| {
  399. match digit.state {
  400. State::Incrementing => {
  401. if digit.value >= DIGIT_MAX_BRIGHTNESS {
  402. digit.value = DIGIT_MAX_BRIGHTNESS;
  403. digit.state = State::Idle;
  404. } else {
  405. digit.value = digit
  406. .value
  407. .saturating_add(steps)
  408. .clamp(DIGIT_MIN_BRIGHTNESS, DIGIT_MAX_BRIGHTNESS);
  409. digit.updated = true;
  410. pending_refresh = true;
  411. }
  412. }
  413. State::Decrementing => {
  414. if digit.value <= DIGIT_MIN_BRIGHTNESS {
  415. digit.value = DIGIT_MIN_BRIGHTNESS;
  416. digit.state = State::Idle;
  417. } else {
  418. digit.value = digit
  419. .value
  420. .saturating_sub(steps)
  421. .clamp(DIGIT_MIN_BRIGHTNESS, DIGIT_MAX_BRIGHTNESS);
  422. digit.updated = true;
  423. pending_refresh = true;
  424. }
  425. }
  426. State::Idle => (),
  427. };
  428. });
  429. });
  430. // Handle dot
  431. let steps = ((DOT_MAX_BRIGHTNESS - DOT_MIN_BRIGHTNESS) + ticks - 1) / ticks;
  432. match CLOCK.dot.state {
  433. State::Incrementing => {
  434. CLOCK.dot.value = CLOCK
  435. .dot
  436. .value
  437. .saturating_add(steps)
  438. .clamp(DOT_MIN_BRIGHTNESS, DOT_MAX_BRIGHTNESS);
  439. if CLOCK.dot.value >= DOT_MAX_BRIGHTNESS {
  440. CLOCK.dot.value = DOT_MAX_BRIGHTNESS;
  441. CLOCK.dot.state = State::Idle;
  442. }
  443. CLOCK.dot.updated = true;
  444. pending_refresh = true;
  445. }
  446. State::Decrementing => {
  447. CLOCK.dot.value = CLOCK
  448. .dot
  449. .value
  450. .saturating_sub(steps)
  451. .clamp(DOT_MIN_BRIGHTNESS, DOT_MAX_BRIGHTNESS);
  452. if CLOCK.dot.value <= DOT_MIN_BRIGHTNESS {
  453. CLOCK.dot.value = DOT_MIN_BRIGHTNESS;
  454. CLOCK.dot.state = State::Idle;
  455. }
  456. CLOCK.dot.updated = true;
  457. pending_refresh = true;
  458. }
  459. State::Idle => (),
  460. }
  461. }
  462. if !pending_refresh {
  463. free(|cs| {
  464. let mut timer_ref = super::REFRESH_TIMER.borrow(cs).borrow_mut();
  465. if let Some(ref mut timer) = timer_ref.deref_mut() {
  466. timer.unlisten(Event::TimeOut);
  467. }
  468. })
  469. } else {
  470. compute_pwm_offset();
  471. unsafe {
  472. for (t, tube) in CLOCK.tubes.iter().enumerate() {
  473. for (d, digit) in tube.digits.iter().enumerate() {
  474. if digit.updated {
  475. pca9685::set_digit(
  476. TUBE_MAPPING.driver[t].digit[d].address,
  477. i2c,
  478. TUBE_MAPPING.driver[t].digit[d].pin,
  479. digit.pwm_start,
  480. digit.pwm_end,
  481. );
  482. }
  483. }
  484. }
  485. if CLOCK.dot.updated {
  486. pca9685::set_digit(
  487. TUBE_MAPPING.dot_address,
  488. i2c,
  489. TUBE_MAPPING.dot_pin,
  490. CLOCK.dot.pwm_start,
  491. CLOCK.dot.pwm_end,
  492. );
  493. }
  494. }
  495. free(|cs| {
  496. let mut timer_ref = super::REFRESH_TIMER.borrow(cs).borrow_mut();
  497. if let Some(ref mut timer) = timer_ref.deref_mut() {
  498. timer.clear_interrupt(Event::TimeOut);
  499. }
  500. })
  501. }
  502. }
  503. pub fn rng_tick<T>(_i2c: &mut T)
  504. where
  505. T: _embedded_hal_blocking_i2c_WriteRead
  506. + _embedded_hal_blocking_i2c_Read
  507. + _embedded_hal_blocking_i2c_Write,
  508. {
  509. }
  510. // In the event that there are multiple PWM outputs at less than 100% duty cycle,
  511. // stagger the start time of each PWM to reduce the switch on surge current.
  512. fn compute_pwm_offset() {
  513. // let mut active_digits: u32 = 0;
  514. // let mut total_on_time: u32 = 0;
  515. // let mut last_pwm_end: u32 = 0;
  516. unsafe {
  517. CLOCK.tubes.iter_mut().for_each(|tube| {
  518. tube.digits.iter_mut().for_each(|digit| {
  519. digit.pwm_start = 0;
  520. digit.pwm_end = digit.value;
  521. });
  522. });
  523. CLOCK.dot.pwm_start = 0;
  524. CLOCK.dot.pwm_end = CLOCK.dot.value;
  525. }
  526. // Determine the number of active outputs as well as the total on-time across all outputs.
  527. // Ignore outputs that are off (min) or fully on (max) as they have no surge impact.
  528. // unsafe {
  529. // CLOCK.tubes.iter().for_each(|tube| {
  530. // tube.digits.iter().for_each(|digit| {
  531. // if digit.value != DIGIT_MAX_BRIGHTNESS && digit.value != DIGIT_MIN_BRIGHTNESS {
  532. // active_digits = active_digits + 1;
  533. // total_on_time = total_on_time + digit.value;
  534. // }
  535. // });
  536. // });
  537. // if CLOCK.dot.value != DIGIT_MAX_BRIGHTNESS && CLOCK.dot.value != DIGIT_MIN_BRIGHTNESS {
  538. // active_digits = active_digits + 1;
  539. // total_on_time = total_on_time + CLOCK.dot.value;
  540. // }
  541. // // If the total on-time across all outputs is less than one PWM period, stagger each
  542. // // output such that the rise of one pulse begins at the end of the previous pulse.
  543. // if total_on_time <= DIGIT_MAX_BRIGHTNESS {
  544. // CLOCK.tubes.iter_mut().for_each(|tube| {
  545. // tube.digits.iter_mut().for_each(|digit| {
  546. // if digit.value == DIGIT_MIN_BRIGHTNESS {
  547. // digit.pwm_start = 0;
  548. // digit.pwm_end = 0;
  549. // } else if digit.value == DIGIT_MAX_BRIGHTNESS {
  550. // digit.pwm_start = 0;
  551. // digit.pwm_end = DIGIT_MAX_BRIGHTNESS;
  552. // } else {
  553. // digit.pwm_start = last_pwm_end;
  554. // digit.pwm_end = last_pwm_end + digit.value;
  555. // last_pwm_end = digit.pwm_end;
  556. // digit.updated = true;
  557. // }
  558. // });
  559. // });
  560. // if CLOCK.dot.value == DIGIT_MIN_BRIGHTNESS {
  561. // CLOCK.dot.pwm_start = 0;
  562. // CLOCK.dot.pwm_end = 0;
  563. // } else if CLOCK.dot.value == DIGIT_MAX_BRIGHTNESS {
  564. // CLOCK.dot.pwm_start = 0;
  565. // CLOCK.dot.pwm_end = DIGIT_MAX_BRIGHTNESS;
  566. // } else {
  567. // CLOCK.dot.pwm_start = last_pwm_end;
  568. // CLOCK.dot.pwm_end = last_pwm_end + CLOCK.dot.value;
  569. // CLOCK.dot.updated = true;
  570. // }
  571. // } else {
  572. // // Compute the amount of overlap between all outputs
  573. // let overlap = (total_on_time - DIGIT_MAX_BRIGHTNESS) / (active_digits - 1);
  574. // // Compute the staggered output period for each output
  575. // CLOCK.tubes.iter_mut().for_each(|tube| {
  576. // tube.digits.iter_mut().for_each(|digit| {
  577. // if digit.value == DIGIT_MIN_BRIGHTNESS {
  578. // digit.pwm_start = 0;
  579. // digit.pwm_end = 0;
  580. // } else if digit.value == DIGIT_MAX_BRIGHTNESS {
  581. // digit.pwm_start = 0;
  582. // digit.pwm_end = DIGIT_MAX_BRIGHTNESS;
  583. // } else {
  584. // digit.pwm_start = last_pwm_end.saturating_sub(overlap);
  585. // digit.pwm_end = digit.pwm_start + digit.value;
  586. // last_pwm_end = digit.pwm_end;
  587. // digit.updated = true;
  588. // }
  589. // });
  590. // });
  591. // if CLOCK.dot.value == DIGIT_MIN_BRIGHTNESS {
  592. // CLOCK.dot.pwm_start = 0;
  593. // CLOCK.dot.pwm_end = 0;
  594. // } else if CLOCK.dot.value == DIGIT_MAX_BRIGHTNESS {
  595. // CLOCK.dot.pwm_start = 0;
  596. // CLOCK.dot.pwm_end = DIGIT_MAX_BRIGHTNESS;
  597. // } else {
  598. // CLOCK.dot.pwm_start = last_pwm_end.saturating_sub(overlap);
  599. // CLOCK.dot.pwm_end = CLOCK.dot.pwm_start + CLOCK.dot.value;
  600. // CLOCK.dot.updated = true;
  601. // }
  602. // }
  603. // }
  604. }