stm32l4xx_hal_dsi.c 74 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32l4xx_hal_dsi.c
  4. * @author MCD Application Team
  5. * @brief DSI HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the DSI peripheral:
  8. * + Initialization and de-initialization functions
  9. * + IO operation functions
  10. * + Peripheral Control functions
  11. * + Peripheral State and Errors functions
  12. ******************************************************************************
  13. * @attention
  14. *
  15. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  16. *
  17. * Redistribution and use in source and binary forms, with or without modification,
  18. * are permitted provided that the following conditions are met:
  19. * 1. Redistributions of source code must retain the above copyright notice,
  20. * this list of conditions and the following disclaimer.
  21. * 2. Redistributions in binary form must reproduce the above copyright notice,
  22. * this list of conditions and the following disclaimer in the documentation
  23. * and/or other materials provided with the distribution.
  24. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  25. * may be used to endorse or promote products derived from this software
  26. * without specific prior written permission.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  29. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  32. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  34. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. *
  39. ******************************************************************************
  40. */
  41. /* Includes ------------------------------------------------------------------*/
  42. #include "stm32l4xx_hal.h"
  43. /** @addtogroup STM32L4xx_HAL_Driver
  44. * @{
  45. */
  46. #ifdef HAL_DSI_MODULE_ENABLED
  47. #if defined(DSI)
  48. /** @addtogroup DSI
  49. * @{
  50. */
  51. /* Private types -------------------------------------------------------------*/
  52. /* Private defines -----------------------------------------------------------*/
  53. /** @addtogroup DSI_Private_Constants
  54. * @{
  55. */
  56. #define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
  57. #define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
  58. DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
  59. DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
  60. DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
  61. #define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
  62. #define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
  63. #define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
  64. #define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
  65. #define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
  66. #define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
  67. #define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
  68. #define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
  69. #define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
  70. /**
  71. * @}
  72. */
  73. /* Private variables ---------------------------------------------------------*/
  74. /* Private constants ---------------------------------------------------------*/
  75. /* Private macros ------------------------------------------------------------*/
  76. /* Private function prototypes -----------------------------------------------*/
  77. static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
  78. /* Private functions ---------------------------------------------------------*/
  79. /**
  80. * @brief Generic DSI packet header configuration
  81. * @param DSIx: Pointer to DSI register base
  82. * @param ChannelID: Virtual channel ID of the header packet
  83. * @param DataType: Packet data type of the header packet
  84. * This parameter can be any value of :
  85. * @ref DSI_SHORT_WRITE_PKT_Data_Type
  86. * or @ref DSI_LONG_WRITE_PKT_Data_Type
  87. * or @ref DSI_SHORT_READ_PKT_Data_Type
  88. * or DSI_MAX_RETURN_PKT_SIZE
  89. * @param Data0: Word count LSB
  90. * @param Data1: Word count MSB
  91. * @retval None
  92. */
  93. static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
  94. uint32_t ChannelID,
  95. uint32_t DataType,
  96. uint32_t Data0,
  97. uint32_t Data1)
  98. {
  99. /* Update the DSI packet header with new information */
  100. DSIx->GHCR = (DataType | (ChannelID<<6U) | (Data0<<8U) | (Data1<<16U));
  101. }
  102. /* Exported functions --------------------------------------------------------*/
  103. /** @addtogroup DSI_Exported_Functions
  104. * @{
  105. */
  106. /** @defgroup DSI_Group1 Initialization and Configuration functions
  107. * @brief Initialization and Configuration functions
  108. *
  109. @verbatim
  110. ===============================================================================
  111. ##### Initialization and Configuration functions #####
  112. ===============================================================================
  113. [..] This section provides functions allowing to:
  114. (+) Initialize and configure the DSI
  115. (+) De-initialize the DSI
  116. @endverbatim
  117. * @{
  118. */
  119. /**
  120. * @brief Initializes the DSI according to the specified
  121. * parameters in the DSI_InitTypeDef and create the associated handle.
  122. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  123. * the configuration information for the DSI.
  124. * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains
  125. * the PLL Clock structure definition for the DSI.
  126. * @retval HAL status
  127. */
  128. HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
  129. {
  130. uint32_t tickstart;
  131. uint32_t unitIntervalx4;
  132. uint32_t tempIDF;
  133. /* Check the DSI handle allocation */
  134. if(hdsi == NULL)
  135. {
  136. return HAL_ERROR;
  137. }
  138. /* Check function parameters */
  139. assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
  140. assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
  141. assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
  142. assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
  143. assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
  144. if(hdsi->State == HAL_DSI_STATE_RESET)
  145. {
  146. /* Initialize the low level hardware */
  147. HAL_DSI_MspInit(hdsi);
  148. }
  149. /* Change DSI peripheral state */
  150. hdsi->State = HAL_DSI_STATE_BUSY;
  151. /**************** Turn on the regulator and enable the DSI PLL ****************/
  152. /* Enable the regulator */
  153. __HAL_DSI_REG_ENABLE(hdsi);
  154. /* Get tick */
  155. tickstart = HAL_GetTick();
  156. /* Wait until the regulator is ready */
  157. while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
  158. {
  159. /* Check for the Timeout */
  160. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  161. {
  162. return HAL_TIMEOUT;
  163. }
  164. }
  165. /* Set the PLL division factors */
  166. hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
  167. hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U));
  168. /* Enable the DSI PLL */
  169. __HAL_DSI_PLL_ENABLE(hdsi);
  170. /* Get tick */
  171. tickstart = HAL_GetTick();
  172. /* Wait for the lock of the PLL */
  173. while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
  174. {
  175. /* Check for the Timeout */
  176. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  177. {
  178. return HAL_TIMEOUT;
  179. }
  180. }
  181. /*************************** Set the PHY parameters ***************************/
  182. /* D-PHY clock and digital enable*/
  183. hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
  184. /* Clock lane configuration */
  185. hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
  186. hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
  187. /* Configure the number of active data lanes */
  188. hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
  189. hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
  190. /************************ Set the DSI clock parameters ************************/
  191. /* Set the TX escape clock division factor */
  192. hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
  193. hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
  194. /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
  195. /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
  196. /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
  197. tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
  198. unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV);
  199. /* Set the bit period in high-speed mode */
  200. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
  201. hdsi->Instance->WPCR[0U] |= unitIntervalx4;
  202. /****************************** Error management *****************************/
  203. /* Disable all error interrupts and reset the Error Mask */
  204. hdsi->Instance->IER[0U] = 0U;
  205. hdsi->Instance->IER[1U] = 0U;
  206. hdsi->ErrorMsk = 0U;
  207. /* Initialise the error code */
  208. hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
  209. /* Initialize the DSI state*/
  210. hdsi->State = HAL_DSI_STATE_READY;
  211. return HAL_OK;
  212. }
  213. /**
  214. * @brief De-initializes the DSI peripheral registers to their default reset
  215. * values.
  216. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  217. * the configuration information for the DSI.
  218. * @retval HAL status
  219. */
  220. HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
  221. {
  222. /* Check the DSI handle allocation */
  223. if(hdsi == NULL)
  224. {
  225. return HAL_ERROR;
  226. }
  227. /* Change DSI peripheral state */
  228. hdsi->State = HAL_DSI_STATE_BUSY;
  229. /* Disable the DSI wrapper */
  230. __HAL_DSI_WRAPPER_DISABLE(hdsi);
  231. /* Disable the DSI host */
  232. __HAL_DSI_DISABLE(hdsi);
  233. /* D-PHY clock and digital disable */
  234. hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
  235. /* Turn off the DSI PLL */
  236. __HAL_DSI_PLL_DISABLE(hdsi);
  237. /* Disable the regulator */
  238. __HAL_DSI_REG_DISABLE(hdsi);
  239. /* DeInit the low level hardware */
  240. HAL_DSI_MspDeInit(hdsi);
  241. /* Initialise the error code */
  242. hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
  243. /* Initialize the DSI state*/
  244. hdsi->State = HAL_DSI_STATE_RESET;
  245. /* Release Lock */
  246. __HAL_UNLOCK(hdsi);
  247. return HAL_OK;
  248. }
  249. /**
  250. * @brief Enable the error monitor flags
  251. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  252. * the configuration information for the DSI.
  253. * @param ActiveErrors: indicates which error interrupts will be enabled.
  254. * This parameter can be any combination of @ref DSI_Error_Data_Type.
  255. * @retval HAL status
  256. */
  257. HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
  258. {
  259. /* Process locked */
  260. __HAL_LOCK(hdsi);
  261. hdsi->Instance->IER[0U] = 0U;
  262. hdsi->Instance->IER[1U] = 0U;
  263. /* Store active errors to the handle */
  264. hdsi->ErrorMsk = ActiveErrors;
  265. if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET)
  266. {
  267. /* Enable the interrupt generation on selected errors */
  268. hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
  269. }
  270. if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET)
  271. {
  272. /* Enable the interrupt generation on selected errors */
  273. hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
  274. }
  275. if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET)
  276. {
  277. /* Enable the interrupt generation on selected errors */
  278. hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
  279. }
  280. if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET)
  281. {
  282. /* Enable the interrupt generation on selected errors */
  283. hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
  284. }
  285. if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET)
  286. {
  287. /* Enable the interrupt generation on selected errors */
  288. hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
  289. }
  290. if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET)
  291. {
  292. /* Enable the interrupt generation on selected errors */
  293. hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
  294. }
  295. if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET)
  296. {
  297. /* Enable the interrupt generation on selected errors */
  298. hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
  299. }
  300. if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET)
  301. {
  302. /* Enable the interrupt generation on selected errors */
  303. hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
  304. }
  305. if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET)
  306. {
  307. /* Enable the interrupt generation on selected errors */
  308. hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
  309. }
  310. if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET)
  311. {
  312. /* Enable the interrupt generation on selected errors */
  313. hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
  314. }
  315. /* Process Unlocked */
  316. __HAL_UNLOCK(hdsi);
  317. return HAL_OK;
  318. }
  319. /**
  320. * @brief Initializes the DSI MSP.
  321. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  322. * the configuration information for the DSI.
  323. * @retval None
  324. */
  325. __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
  326. {
  327. /* Prevent unused argument(s) compilation warning */
  328. UNUSED(hdsi);
  329. /* NOTE : This function Should not be modified, when the callback is needed,
  330. the HAL_DSI_MspInit could be implemented in the user file
  331. */
  332. }
  333. /**
  334. * @brief De-initializes the DSI MSP.
  335. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  336. * the configuration information for the DSI.
  337. * @retval None
  338. */
  339. __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
  340. {
  341. /* Prevent unused argument(s) compilation warning */
  342. UNUSED(hdsi);
  343. /* NOTE : This function Should not be modified, when the callback is needed,
  344. the HAL_DSI_MspDeInit could be implemented in the user file
  345. */
  346. }
  347. /**
  348. * @}
  349. */
  350. /** @defgroup DSI_Group2 IO operation functions
  351. * @brief IO operation functions
  352. *
  353. @verbatim
  354. ===============================================================================
  355. ##### IO operation functions #####
  356. ===============================================================================
  357. [..] This section provides function allowing to:
  358. (+) Handle DSI interrupt request
  359. @endverbatim
  360. * @{
  361. */
  362. /**
  363. * @brief Handles DSI interrupt request.
  364. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  365. * the configuration information for the DSI.
  366. * @retval HAL status
  367. */
  368. void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
  369. {
  370. uint32_t ErrorStatus0, ErrorStatus1;
  371. /* Tearing Effect Interrupt management ***************************************/
  372. if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
  373. {
  374. if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)
  375. {
  376. /* Clear the Tearing Effect Interrupt Flag */
  377. __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
  378. /* Tearing Effect Callback */
  379. HAL_DSI_TearingEffectCallback(hdsi);
  380. }
  381. }
  382. /* End of Refresh Interrupt management ***************************************/
  383. if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
  384. {
  385. if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)
  386. {
  387. /* Clear the End of Refresh Interrupt Flag */
  388. __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
  389. /* End of Refresh Callback */
  390. HAL_DSI_EndOfRefreshCallback(hdsi);
  391. }
  392. }
  393. /* Error Interrupts management ***********************************************/
  394. if(hdsi->ErrorMsk != 0U)
  395. {
  396. ErrorStatus0 = hdsi->Instance->ISR[0U];
  397. ErrorStatus0 &= hdsi->Instance->IER[0U];
  398. ErrorStatus1 = hdsi->Instance->ISR[1U];
  399. ErrorStatus1 &= hdsi->Instance->IER[1U];
  400. if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET)
  401. {
  402. hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
  403. }
  404. if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET)
  405. {
  406. hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
  407. }
  408. if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET)
  409. {
  410. hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
  411. }
  412. if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET)
  413. {
  414. hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
  415. }
  416. if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET)
  417. {
  418. hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
  419. }
  420. if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET)
  421. {
  422. hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
  423. }
  424. if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET)
  425. {
  426. hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
  427. }
  428. if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET)
  429. {
  430. hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
  431. }
  432. if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET)
  433. {
  434. hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
  435. }
  436. if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET)
  437. {
  438. hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
  439. }
  440. /* Check only selected errors */
  441. if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
  442. {
  443. /* DSI error interrupt user callback */
  444. HAL_DSI_ErrorCallback(hdsi);
  445. }
  446. }
  447. }
  448. /**
  449. * @brief Tearing Effect DSI callback.
  450. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  451. * the configuration information for the DSI.
  452. * @retval None
  453. */
  454. __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
  455. {
  456. /* Prevent unused argument(s) compilation warning */
  457. UNUSED(hdsi);
  458. /* NOTE : This function Should not be modified, when the callback is needed,
  459. the HAL_DSI_TearingEffectCallback could be implemented in the user file
  460. */
  461. }
  462. /**
  463. * @brief End of Refresh DSI callback.
  464. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  465. * the configuration information for the DSI.
  466. * @retval None
  467. */
  468. __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
  469. {
  470. /* Prevent unused argument(s) compilation warning */
  471. UNUSED(hdsi);
  472. /* NOTE : This function Should not be modified, when the callback is needed,
  473. the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
  474. */
  475. }
  476. /**
  477. * @brief Operation Error DSI callback.
  478. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  479. * the configuration information for the DSI.
  480. * @retval None
  481. */
  482. __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
  483. {
  484. /* Prevent unused argument(s) compilation warning */
  485. UNUSED(hdsi);
  486. /* NOTE : This function Should not be modified, when the callback is needed,
  487. the HAL_DSI_ErrorCallback could be implemented in the user file
  488. */
  489. }
  490. /**
  491. * @}
  492. */
  493. /** @defgroup DSI_Group3 Peripheral Control functions
  494. * @brief Peripheral Control functions
  495. *
  496. @verbatim
  497. ===============================================================================
  498. ##### Peripheral Control functions #####
  499. ===============================================================================
  500. [..] This section provides functions allowing to:
  501. (+) Configure the Generic interface read-back Virtual Channel ID
  502. (+) Select video mode and configure the corresponding parameters
  503. (+) Configure command transmission mode: High-speed or Low-power
  504. (+) Configure the flow control
  505. (+) Configure the DSI PHY timer
  506. (+) Configure the DSI HOST timeout
  507. (+) Configure the DSI HOST timeout
  508. (+) Start/Stop the DSI module
  509. (+) Refresh the display in command mode
  510. (+) Controls the display color mode in Video mode
  511. (+) Control the display shutdown in Video mode
  512. (+) write short DCS or short Generic command
  513. (+) write long DCS or long Generic command
  514. (+) Read command (DCS or generic)
  515. (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running)
  516. (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off)
  517. (+) Start/Stop test pattern generation
  518. (+) Slew-Rate And Delay Tuning
  519. (+) Low-Power Reception Filter Tuning
  520. (+) Activate an additional current path on all lanes to meet the SDDTx parameter
  521. (+) Custom lane pins configuration
  522. (+) Set custom timing for the PHY
  523. (+) Force the Clock/Data Lane in TX Stop Mode
  524. (+) Force LP Receiver in Low-Power Mode
  525. (+) Force Data Lanes in RX Mode after a BTA
  526. (+) Enable a pull-down on the lanes to prevent from floating states when unused
  527. (+) Switch off the contention detection on data lanes
  528. @endverbatim
  529. * @{
  530. */
  531. /**
  532. * @brief Configure the Generic interface read-back Virtual Channel ID.
  533. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  534. * the configuration information for the DSI.
  535. * @param VirtualChannelID: Virtual channel ID
  536. * @retval HAL status
  537. */
  538. HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
  539. {
  540. /* Process locked */
  541. __HAL_LOCK(hdsi);
  542. /* Update the GVCID register */
  543. hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
  544. hdsi->Instance->GVCIDR |= VirtualChannelID;
  545. /* Process unlocked */
  546. __HAL_UNLOCK(hdsi);
  547. return HAL_OK;
  548. }
  549. /**
  550. * @brief Select video mode and configure the corresponding parameters
  551. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  552. * the configuration information for the DSI.
  553. * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
  554. * the DSI video mode configuration parameters
  555. * @retval HAL status
  556. */
  557. HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
  558. {
  559. /* Process locked */
  560. __HAL_LOCK(hdsi);
  561. /* Check the parameters */
  562. assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
  563. assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
  564. assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
  565. assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
  566. assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
  567. assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
  568. assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
  569. assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
  570. assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
  571. assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
  572. assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
  573. assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
  574. assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
  575. /* Check the LooselyPacked variant only in 18-bit mode */
  576. if(VidCfg->ColorCoding == DSI_RGB666)
  577. {
  578. assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
  579. }
  580. /* Select video mode by resetting CMDM and DSIM bits */
  581. hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
  582. hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
  583. /* Configure the video mode transmission type */
  584. hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
  585. hdsi->Instance->VMCR |= VidCfg->Mode;
  586. /* Configure the video packet size */
  587. hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
  588. hdsi->Instance->VPCR |= VidCfg->PacketSize;
  589. /* Set the chunks number to be transmitted through the DSI link */
  590. hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
  591. hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
  592. /* Set the size of the null packet */
  593. hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
  594. hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
  595. /* Select the virtual channel for the LTDC interface traffic */
  596. hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
  597. hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
  598. /* Configure the polarity of control signals */
  599. hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
  600. hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
  601. /* Select the color coding for the host */
  602. hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
  603. hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
  604. /* Select the color coding for the wrapper */
  605. hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
  606. hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1U);
  607. /* Enable/disable the loosely packed variant to 18-bit configuration */
  608. if(VidCfg->ColorCoding == DSI_RGB666)
  609. {
  610. hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
  611. hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
  612. }
  613. /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
  614. hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
  615. hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
  616. /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
  617. hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
  618. hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
  619. /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
  620. hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
  621. hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
  622. /* Set the Vertical Synchronization Active (VSA) */
  623. hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
  624. hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
  625. /* Set the Vertical Back Porch (VBP)*/
  626. hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
  627. hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
  628. /* Set the Vertical Front Porch (VFP)*/
  629. hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
  630. hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
  631. /* Set the Vertical Active period*/
  632. hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
  633. hdsi->Instance->VVACR |= VidCfg->VerticalActive;
  634. /* Configure the command transmission mode */
  635. hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
  636. hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
  637. /* Low power largest packet size */
  638. hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
  639. hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16U);
  640. /* Low power VACT largest packet size */
  641. hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
  642. hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
  643. /* Enable LP transition in HFP period */
  644. hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
  645. hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
  646. /* Enable LP transition in HBP period */
  647. hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
  648. hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
  649. /* Enable LP transition in VACT period */
  650. hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
  651. hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
  652. /* Enable LP transition in VFP period */
  653. hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
  654. hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
  655. /* Enable LP transition in VBP period */
  656. hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
  657. hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
  658. /* Enable LP transition in vertical sync period */
  659. hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
  660. hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
  661. /* Enable the request for an acknowledge response at the end of a frame */
  662. hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
  663. hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
  664. /* Process unlocked */
  665. __HAL_UNLOCK(hdsi);
  666. return HAL_OK;
  667. }
  668. /**
  669. * @brief Select adapted command mode and configure the corresponding parameters
  670. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  671. * the configuration information for the DSI.
  672. * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
  673. * the DSI command mode configuration parameters
  674. * @retval HAL status
  675. */
  676. HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
  677. {
  678. /* Process locked */
  679. __HAL_LOCK(hdsi);
  680. /* Check the parameters */
  681. assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
  682. assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
  683. assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
  684. assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
  685. assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
  686. assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
  687. assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
  688. assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
  689. assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
  690. /* Select command mode by setting CMDM and DSIM bits */
  691. hdsi->Instance->MCR |= DSI_MCR_CMDM;
  692. hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
  693. hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
  694. /* Select the virtual channel for the LTDC interface traffic */
  695. hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
  696. hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
  697. /* Configure the polarity of control signals */
  698. hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
  699. hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
  700. /* Select the color coding for the host */
  701. hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
  702. hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
  703. /* Select the color coding for the wrapper */
  704. hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
  705. hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1U);
  706. /* Configure the maximum allowed size for write memory command */
  707. hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
  708. hdsi->Instance->LCCR |= CmdCfg->CommandSize;
  709. /* Configure the tearing effect source and polarity and select the refresh mode */
  710. hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
  711. hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
  712. /* Configure the tearing effect acknowledge request */
  713. hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
  714. hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
  715. /* Enable the Tearing Effect interrupt */
  716. __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
  717. /* Enable the End of Refresh interrupt */
  718. __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
  719. /* Process unlocked */
  720. __HAL_UNLOCK(hdsi);
  721. return HAL_OK;
  722. }
  723. /**
  724. * @brief Configure command transmission mode: High-speed or Low-power
  725. * and enable/disable acknowledge request after packet transmission
  726. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  727. * the configuration information for the DSI.
  728. * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains
  729. * the DSI command transmission mode configuration parameters
  730. * @retval HAL status
  731. */
  732. HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
  733. {
  734. /* Process locked */
  735. __HAL_LOCK(hdsi);
  736. assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
  737. assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
  738. assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
  739. assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
  740. assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
  741. assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
  742. assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
  743. assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
  744. assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
  745. assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
  746. assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
  747. assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
  748. assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
  749. /* Select High-speed or Low-power for command transmission */
  750. hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\
  751. DSI_CMCR_GSW1TX |\
  752. DSI_CMCR_GSW2TX |\
  753. DSI_CMCR_GSR0TX |\
  754. DSI_CMCR_GSR1TX |\
  755. DSI_CMCR_GSR2TX |\
  756. DSI_CMCR_GLWTX |\
  757. DSI_CMCR_DSW0TX |\
  758. DSI_CMCR_DSW1TX |\
  759. DSI_CMCR_DSR0TX |\
  760. DSI_CMCR_DLWTX |\
  761. DSI_CMCR_MRDPS);
  762. hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\
  763. LPCmd->LPGenShortWriteOneP |\
  764. LPCmd->LPGenShortWriteTwoP |\
  765. LPCmd->LPGenShortReadNoP |\
  766. LPCmd->LPGenShortReadOneP |\
  767. LPCmd->LPGenShortReadTwoP |\
  768. LPCmd->LPGenLongWrite |\
  769. LPCmd->LPDcsShortWriteNoP |\
  770. LPCmd->LPDcsShortWriteOneP |\
  771. LPCmd->LPDcsShortReadNoP |\
  772. LPCmd->LPDcsLongWrite |\
  773. LPCmd->LPMaxReadPacket);
  774. /* Configure the acknowledge request after each packet transmission */
  775. hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
  776. hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
  777. /* Process unlocked */
  778. __HAL_UNLOCK(hdsi);
  779. return HAL_OK;
  780. }
  781. /**
  782. * @brief Configure the flow control parameters
  783. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  784. * the configuration information for the DSI.
  785. * @param FlowControl: flow control feature(s) to be enabled.
  786. * This parameter can be any combination of @ref DSI_FlowControl.
  787. * @retval HAL status
  788. */
  789. HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
  790. {
  791. /* Process locked */
  792. __HAL_LOCK(hdsi);
  793. /* Check the parameters */
  794. assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
  795. /* Set the DSI Host Protocol Configuration Register */
  796. hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
  797. hdsi->Instance->PCR |= FlowControl;
  798. /* Process unlocked */
  799. __HAL_UNLOCK(hdsi);
  800. return HAL_OK;
  801. }
  802. /**
  803. * @brief Configure the DSI PHY timer parameters
  804. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  805. * the configuration information for the DSI.
  806. * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains
  807. * the DSI PHY timing parameters
  808. * @retval HAL status
  809. */
  810. HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
  811. {
  812. uint32_t maxTime;
  813. /* Process locked */
  814. __HAL_LOCK(hdsi);
  815. maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
  816. /* Clock lane timer configuration */
  817. /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
  818. High-Speed transmission.
  819. To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
  820. to Low-Power and from Low-Power to High-Speed.
  821. This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
  822. But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
  823. Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
  824. */
  825. hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
  826. hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16U));
  827. /* Data lane timer configuration */
  828. hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
  829. hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16U) | ((PhyTimers->DataLaneHS2LPTime)<<24U));
  830. /* Configure the wait period to request HS transmission after a stop state */
  831. hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
  832. hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8U);
  833. /* Process unlocked */
  834. __HAL_UNLOCK(hdsi);
  835. return HAL_OK;
  836. }
  837. /**
  838. * @brief Configure the DSI HOST timeout parameters
  839. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  840. * the configuration information for the DSI.
  841. * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains
  842. * the DSI host timeout parameters
  843. * @retval HAL status
  844. */
  845. HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
  846. {
  847. /* Process locked */
  848. __HAL_LOCK(hdsi);
  849. /* Set the timeout clock division factor */
  850. hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
  851. hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8U);
  852. /* High-speed transmission timeout */
  853. hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
  854. hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U);
  855. /* Low-power reception timeout */
  856. hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
  857. hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout;
  858. /* High-speed read timeout */
  859. hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
  860. hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout;
  861. /* Low-power read timeout */
  862. hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
  863. hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout;
  864. /* High-speed write timeout */
  865. hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
  866. hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout;
  867. /* High-speed write presp mode */
  868. hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
  869. hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode;
  870. /* Low-speed write timeout */
  871. hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
  872. hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout;
  873. /* BTA timeout */
  874. hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
  875. hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout;
  876. /* Process unlocked */
  877. __HAL_UNLOCK(hdsi);
  878. return HAL_OK;
  879. }
  880. /**
  881. * @brief Start the DSI module
  882. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  883. * the configuration information for the DSI.
  884. * @retval HAL status
  885. */
  886. HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
  887. {
  888. /* Process locked */
  889. __HAL_LOCK(hdsi);
  890. /* Enable the DSI host */
  891. __HAL_DSI_ENABLE(hdsi);
  892. /* Enable the DSI wrapper */
  893. __HAL_DSI_WRAPPER_ENABLE(hdsi);
  894. /* Process unlocked */
  895. __HAL_UNLOCK(hdsi);
  896. return HAL_OK;
  897. }
  898. /**
  899. * @brief Stop the DSI module
  900. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  901. * the configuration information for the DSI.
  902. * @retval HAL status
  903. */
  904. HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
  905. {
  906. /* Process locked */
  907. __HAL_LOCK(hdsi);
  908. /* Disable the DSI host */
  909. __HAL_DSI_DISABLE(hdsi);
  910. /* Disable the DSI wrapper */
  911. __HAL_DSI_WRAPPER_DISABLE(hdsi);
  912. /* Process unlocked */
  913. __HAL_UNLOCK(hdsi);
  914. return HAL_OK;
  915. }
  916. /**
  917. * @brief Refresh the display in command mode
  918. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  919. * the configuration information for the DSI.
  920. * @retval HAL status
  921. */
  922. HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
  923. {
  924. /* Process locked */
  925. __HAL_LOCK(hdsi);
  926. /* Update the display */
  927. hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
  928. /* Process unlocked */
  929. __HAL_UNLOCK(hdsi);
  930. return HAL_OK;
  931. }
  932. /**
  933. * @brief Controls the display color mode in Video mode
  934. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  935. * the configuration information for the DSI.
  936. * @param ColorMode: Color mode (full or 8-colors).
  937. * This parameter can be any value of @ref DSI_Color_Mode
  938. * @retval HAL status
  939. */
  940. HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
  941. {
  942. /* Process locked */
  943. __HAL_LOCK(hdsi);
  944. /* Check the parameters */
  945. assert_param(IS_DSI_COLOR_MODE(ColorMode));
  946. /* Update the display color mode */
  947. hdsi->Instance->WCR &= ~DSI_WCR_COLM;
  948. hdsi->Instance->WCR |= ColorMode;
  949. /* Process unlocked */
  950. __HAL_UNLOCK(hdsi);
  951. return HAL_OK;
  952. }
  953. /**
  954. * @brief Control the display shutdown in Video mode
  955. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  956. * the configuration information for the DSI.
  957. * @param Shutdown: Shut-down (Display-ON or Display-OFF).
  958. * This parameter can be any value of @ref DSI_ShutDown
  959. * @retval HAL status
  960. */
  961. HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
  962. {
  963. /* Process locked */
  964. __HAL_LOCK(hdsi);
  965. /* Check the parameters */
  966. assert_param(IS_DSI_SHUT_DOWN(Shutdown));
  967. /* Update the display Shutdown */
  968. hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
  969. hdsi->Instance->WCR |= Shutdown;
  970. /* Process unlocked */
  971. __HAL_UNLOCK(hdsi);
  972. return HAL_OK;
  973. }
  974. /**
  975. * @brief write short DCS or short Generic command
  976. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  977. * the configuration information for the DSI.
  978. * @param ChannelID: Virtual channel ID.
  979. * @param Mode: DSI short packet data type.
  980. * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
  981. * @param Param1: DSC command or first generic parameter.
  982. * This parameter can be any value of @ref DSI_DCS_Command or a
  983. * generic command code.
  984. * @param Param2: DSC parameter or second generic parameter.
  985. * @retval HAL status
  986. */
  987. HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
  988. uint32_t ChannelID,
  989. uint32_t Mode,
  990. uint32_t Param1,
  991. uint32_t Param2)
  992. {
  993. uint32_t tickstart;
  994. /* Process locked */
  995. __HAL_LOCK(hdsi);
  996. /* Check the parameters */
  997. assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
  998. /* Get tick */
  999. tickstart = HAL_GetTick();
  1000. /* Wait for Command FIFO Empty */
  1001. while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
  1002. {
  1003. /* Check for the Timeout */
  1004. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1005. {
  1006. /* Process Unlocked */
  1007. __HAL_UNLOCK(hdsi);
  1008. return HAL_TIMEOUT;
  1009. }
  1010. }
  1011. /* Configure the packet to send a short DCS command with 0 or 1 parameter */
  1012. DSI_ConfigPacketHeader(hdsi->Instance,
  1013. ChannelID,
  1014. Mode,
  1015. Param1,
  1016. Param2);
  1017. /* Process unlocked */
  1018. __HAL_UNLOCK(hdsi);
  1019. return HAL_OK;
  1020. }
  1021. /**
  1022. * @brief write long DCS or long Generic command
  1023. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1024. * the configuration information for the DSI.
  1025. * @param ChannelID: Virtual channel ID.
  1026. * @param Mode: DSI long packet data type.
  1027. * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
  1028. * @param NbParams: Number of parameters.
  1029. * @param Param1: DSC command or first generic parameter.
  1030. * This parameter can be any value of @ref DSI_DCS_Command or a
  1031. * generic command code
  1032. * @param ParametersTable: Pointer to parameter values table.
  1033. * @retval HAL status
  1034. */
  1035. HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
  1036. uint32_t ChannelID,
  1037. uint32_t Mode,
  1038. uint32_t NbParams,
  1039. uint32_t Param1,
  1040. uint8_t* ParametersTable)
  1041. {
  1042. uint32_t uicounter, nbBytes, count;
  1043. uint32_t tickstart;
  1044. uint32_t fifoword;
  1045. uint8_t* pparams = ParametersTable;
  1046. /* Process locked */
  1047. __HAL_LOCK(hdsi);
  1048. /* Check the parameters */
  1049. assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
  1050. /* Get tick */
  1051. tickstart = HAL_GetTick();
  1052. /* Wait for Command FIFO Empty */
  1053. while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
  1054. {
  1055. /* Check for the Timeout */
  1056. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1057. {
  1058. /* Process Unlocked */
  1059. __HAL_UNLOCK(hdsi);
  1060. return HAL_TIMEOUT;
  1061. }
  1062. }
  1063. /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/
  1064. fifoword = Param1;
  1065. nbBytes = (NbParams < 3U) ? NbParams : 3U;
  1066. for(count = 0U; count < nbBytes; count++)
  1067. {
  1068. fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U*count)));
  1069. }
  1070. hdsi->Instance->GPDR = fifoword;
  1071. uicounter = NbParams - nbBytes;
  1072. pparams += nbBytes;
  1073. /* Set the Next parameters on the write FIFO command*/
  1074. while(uicounter != 0U)
  1075. {
  1076. nbBytes = (uicounter < 4U) ? uicounter : 4U;
  1077. fifoword = 0U;
  1078. for(count = 0U; count < nbBytes; count++)
  1079. {
  1080. fifoword |= (((uint32_t)(*(pparams + count))) << (8U*count));
  1081. }
  1082. hdsi->Instance->GPDR = fifoword;
  1083. uicounter -= nbBytes;
  1084. pparams += nbBytes;
  1085. }
  1086. /* Configure the packet to send a long DCS command */
  1087. DSI_ConfigPacketHeader(hdsi->Instance,
  1088. ChannelID,
  1089. Mode,
  1090. ((NbParams+1U)&0x00FFU),
  1091. (((NbParams+1U)&0xFF00U)>>8U));
  1092. /* Process unlocked */
  1093. __HAL_UNLOCK(hdsi);
  1094. return HAL_OK;
  1095. }
  1096. /**
  1097. * @brief Read command (DCS or generic)
  1098. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1099. * the configuration information for the DSI.
  1100. * @param ChannelNbr: Virtual channel ID
  1101. * @param Array: pointer to a buffer to store the payload of a read back operation.
  1102. * @param Size: Data size to be read (in byte).
  1103. * @param Mode: DSI read packet data type.
  1104. * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
  1105. * @param DCSCmd: DCS get/read command.
  1106. * @param ParametersTable: Pointer to parameter values table.
  1107. * @retval HAL status
  1108. */
  1109. HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
  1110. uint32_t ChannelNbr,
  1111. uint8_t* Array,
  1112. uint32_t Size,
  1113. uint32_t Mode,
  1114. uint32_t DCSCmd,
  1115. uint8_t* ParametersTable)
  1116. {
  1117. uint32_t tickstart;
  1118. uint8_t* pdata = Array;
  1119. uint32_t datasize = Size;
  1120. /* Process locked */
  1121. __HAL_LOCK(hdsi);
  1122. /* Check the parameters */
  1123. assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
  1124. if(datasize > 2U)
  1125. {
  1126. /* set max return packet size */
  1127. if (HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize)&0xFFU), (((datasize)>>8U)&0xFFU)) != HAL_OK)
  1128. {
  1129. /* Process Unlocked */
  1130. __HAL_UNLOCK(hdsi);
  1131. return HAL_ERROR;
  1132. }
  1133. }
  1134. /* Configure the packet to read command */
  1135. if (Mode == DSI_DCS_SHORT_PKT_READ)
  1136. {
  1137. DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);
  1138. }
  1139. else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
  1140. {
  1141. DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);
  1142. }
  1143. else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
  1144. {
  1145. DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);
  1146. }
  1147. else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
  1148. {
  1149. DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
  1150. }
  1151. else
  1152. {
  1153. /* Process Unlocked */
  1154. __HAL_UNLOCK(hdsi);
  1155. return HAL_ERROR;
  1156. }
  1157. /* Get tick */
  1158. tickstart = HAL_GetTick();
  1159. /* Check that the payload read FIFO is not empty */
  1160. while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
  1161. {
  1162. /* Check for the Timeout */
  1163. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1164. {
  1165. /* Process Unlocked */
  1166. __HAL_UNLOCK(hdsi);
  1167. return HAL_TIMEOUT;
  1168. }
  1169. }
  1170. /* Get the first byte */
  1171. *((uint32_t *)pdata) = (hdsi->Instance->GPDR);
  1172. if (datasize > 4U)
  1173. {
  1174. datasize -= 4U;
  1175. pdata += 4U;
  1176. }
  1177. else
  1178. {
  1179. /* Process unlocked */
  1180. __HAL_UNLOCK(hdsi);
  1181. return HAL_OK;
  1182. }
  1183. /* Get tick */
  1184. tickstart = HAL_GetTick();
  1185. /* Get the remaining bytes if any */
  1186. while(((int)(datasize)) > 0U)
  1187. {
  1188. if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
  1189. {
  1190. *((uint32_t *)pdata) = (hdsi->Instance->GPDR);
  1191. datasize -= 4U;
  1192. pdata += 4U;
  1193. }
  1194. /* Check for the Timeout */
  1195. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1196. {
  1197. /* Process Unlocked */
  1198. __HAL_UNLOCK(hdsi);
  1199. return HAL_TIMEOUT;
  1200. }
  1201. }
  1202. /* Process unlocked */
  1203. __HAL_UNLOCK(hdsi);
  1204. return HAL_OK;
  1205. }
  1206. /**
  1207. * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
  1208. * (only data lanes are in ULPM)
  1209. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1210. * the configuration information for the DSI.
  1211. * @retval HAL status
  1212. */
  1213. HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
  1214. {
  1215. uint32_t tickstart;
  1216. /* Process locked */
  1217. __HAL_LOCK(hdsi);
  1218. /* ULPS Request on Data Lanes */
  1219. hdsi->Instance->PUCR |= DSI_PUCR_URDL;
  1220. /* Get tick */
  1221. tickstart = HAL_GetTick();
  1222. /* Wait until the D-PHY active lanes enter into ULPM */
  1223. if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
  1224. {
  1225. while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
  1226. {
  1227. /* Check for the Timeout */
  1228. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1229. {
  1230. /* Process Unlocked */
  1231. __HAL_UNLOCK(hdsi);
  1232. return HAL_TIMEOUT;
  1233. }
  1234. }
  1235. }
  1236. else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
  1237. {
  1238. while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
  1239. {
  1240. /* Check for the Timeout */
  1241. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1242. {
  1243. /* Process Unlocked */
  1244. __HAL_UNLOCK(hdsi);
  1245. return HAL_TIMEOUT;
  1246. }
  1247. }
  1248. }
  1249. else
  1250. {
  1251. /* Process unlocked */
  1252. __HAL_UNLOCK(hdsi);
  1253. return HAL_ERROR;
  1254. }
  1255. /* Process unlocked */
  1256. __HAL_UNLOCK(hdsi);
  1257. return HAL_OK;
  1258. }
  1259. /**
  1260. * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
  1261. * (only data lanes are in ULPM)
  1262. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1263. * the configuration information for the DSI.
  1264. * @retval HAL status
  1265. */
  1266. HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
  1267. {
  1268. uint32_t tickstart;
  1269. /* Process locked */
  1270. __HAL_LOCK(hdsi);
  1271. /* Exit ULPS on Data Lanes */
  1272. hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
  1273. /* Get tick */
  1274. tickstart = HAL_GetTick();
  1275. /* Wait until all active lanes exit ULPM */
  1276. if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
  1277. {
  1278. while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
  1279. {
  1280. /* Check for the Timeout */
  1281. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1282. {
  1283. /* Process Unlocked */
  1284. __HAL_UNLOCK(hdsi);
  1285. return HAL_TIMEOUT;
  1286. }
  1287. }
  1288. }
  1289. else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
  1290. {
  1291. while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
  1292. {
  1293. /* Check for the Timeout */
  1294. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1295. {
  1296. /* Process Unlocked */
  1297. __HAL_UNLOCK(hdsi);
  1298. return HAL_TIMEOUT;
  1299. }
  1300. }
  1301. }
  1302. else
  1303. {
  1304. /* Process unlocked */
  1305. __HAL_UNLOCK(hdsi);
  1306. return HAL_ERROR;
  1307. }
  1308. /* wait for 1 ms*/
  1309. HAL_Delay(1U);
  1310. /* De-assert the ULPM requests and the ULPM exit bits */
  1311. hdsi->Instance->PUCR = 0U;
  1312. /* Process unlocked */
  1313. __HAL_UNLOCK(hdsi);
  1314. return HAL_OK;
  1315. }
  1316. /**
  1317. * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
  1318. * (both data and clock lanes are in ULPM)
  1319. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1320. * the configuration information for the DSI.
  1321. * @retval HAL status
  1322. */
  1323. HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
  1324. {
  1325. uint32_t tickstart;
  1326. /* Process locked */
  1327. __HAL_LOCK(hdsi);
  1328. /* Clock lane configuration: no more HS request */
  1329. hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
  1330. /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
  1331. __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLSAI2);
  1332. /* ULPS Request on Clock and Data Lanes */
  1333. hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
  1334. /* Get tick */
  1335. tickstart = HAL_GetTick();
  1336. /* Wait until all active lanes exit ULPM */
  1337. if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
  1338. {
  1339. while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
  1340. {
  1341. /* Check for the Timeout */
  1342. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1343. {
  1344. /* Process Unlocked */
  1345. __HAL_UNLOCK(hdsi);
  1346. return HAL_TIMEOUT;
  1347. }
  1348. }
  1349. }
  1350. else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
  1351. {
  1352. while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
  1353. {
  1354. /* Check for the Timeout */
  1355. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1356. {
  1357. /* Process Unlocked */
  1358. __HAL_UNLOCK(hdsi);
  1359. return HAL_TIMEOUT;
  1360. }
  1361. }
  1362. }
  1363. else
  1364. {
  1365. /* Process unlocked */
  1366. __HAL_UNLOCK(hdsi);
  1367. return HAL_ERROR;
  1368. }
  1369. /* Turn off the DSI PLL */
  1370. __HAL_DSI_PLL_DISABLE(hdsi);
  1371. /* Process unlocked */
  1372. __HAL_UNLOCK(hdsi);
  1373. return HAL_OK;
  1374. }
  1375. /**
  1376. * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
  1377. * (both data and clock lanes are in ULPM)
  1378. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1379. * the configuration information for the DSI.
  1380. * @retval HAL status
  1381. */
  1382. HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
  1383. {
  1384. uint32_t tickstart;
  1385. /* Process locked */
  1386. __HAL_LOCK(hdsi);
  1387. /* Turn on the DSI PLL */
  1388. __HAL_DSI_PLL_ENABLE(hdsi);
  1389. /* Get tick */
  1390. tickstart = HAL_GetTick();
  1391. /* Wait for the lock of the PLL */
  1392. while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
  1393. {
  1394. /* Check for the Timeout */
  1395. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1396. {
  1397. /* Process Unlocked */
  1398. __HAL_UNLOCK(hdsi);
  1399. return HAL_TIMEOUT;
  1400. }
  1401. }
  1402. /* Exit ULPS on Clock and Data Lanes */
  1403. hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
  1404. /* Get tick */
  1405. tickstart = HAL_GetTick();
  1406. /* Wait until all active lanes exit ULPM */
  1407. if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
  1408. {
  1409. while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
  1410. {
  1411. /* Check for the Timeout */
  1412. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1413. {
  1414. /* Process Unlocked */
  1415. __HAL_UNLOCK(hdsi);
  1416. return HAL_TIMEOUT;
  1417. }
  1418. }
  1419. }
  1420. else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
  1421. {
  1422. while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
  1423. {
  1424. /* Check for the Timeout */
  1425. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1426. {
  1427. /* Process Unlocked */
  1428. __HAL_UNLOCK(hdsi);
  1429. return HAL_TIMEOUT;
  1430. }
  1431. }
  1432. }
  1433. else
  1434. {
  1435. /* Process unlocked */
  1436. __HAL_UNLOCK(hdsi);
  1437. return HAL_ERROR;
  1438. }
  1439. /* wait for 1 ms */
  1440. HAL_Delay(1U);
  1441. /* De-assert the ULPM requests and the ULPM exit bits */
  1442. hdsi->Instance->PUCR = 0U;
  1443. /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
  1444. __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
  1445. /* Restore clock lane configuration to HS */
  1446. hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
  1447. /* Process unlocked */
  1448. __HAL_UNLOCK(hdsi);
  1449. return HAL_OK;
  1450. }
  1451. /**
  1452. * @brief Start test pattern generation
  1453. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1454. * the configuration information for the DSI.
  1455. * @param Mode: Pattern generator mode
  1456. * This parameter can be one of the following values:
  1457. * 0 : Color bars (horizontal or vertical)
  1458. * 1 : BER pattern (vertical only)
  1459. * @param Orientation: Pattern generator orientation
  1460. * This parameter can be one of the following values:
  1461. * 0 : Vertical color bars
  1462. * 1 : Horizontal color bars
  1463. * @retval HAL status
  1464. */
  1465. HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
  1466. {
  1467. /* Process locked */
  1468. __HAL_LOCK(hdsi);
  1469. /* Configure pattern generator mode and orientation */
  1470. hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
  1471. hdsi->Instance->VMCR |= ((Mode<<20U) | (Orientation<<24U));
  1472. /* Enable pattern generator by setting PGE bit */
  1473. hdsi->Instance->VMCR |= DSI_VMCR_PGE;
  1474. /* Process unlocked */
  1475. __HAL_UNLOCK(hdsi);
  1476. return HAL_OK;
  1477. }
  1478. /**
  1479. * @brief Stop test pattern generation
  1480. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1481. * the configuration information for the DSI.
  1482. * @retval HAL status
  1483. */
  1484. HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
  1485. {
  1486. /* Process locked */
  1487. __HAL_LOCK(hdsi);
  1488. /* Disable pattern generator by clearing PGE bit */
  1489. hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
  1490. /* Process unlocked */
  1491. __HAL_UNLOCK(hdsi);
  1492. return HAL_OK;
  1493. }
  1494. /**
  1495. * @brief Set Slew-Rate And Delay Tuning
  1496. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1497. * the configuration information for the DSI.
  1498. * @param CommDelay: Communication delay to be adjusted.
  1499. * This parameter can be any value of @ref DSI_Communication_Delay
  1500. * @param Lane: select between clock or data lanes.
  1501. * This parameter can be any value of @ref DSI_Lane_Group
  1502. * @param Value: Custom value of the slew-rate or delay
  1503. * @retval HAL status
  1504. */
  1505. HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
  1506. {
  1507. /* Process locked */
  1508. __HAL_LOCK(hdsi);
  1509. /* Check function parameters */
  1510. assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
  1511. assert_param(IS_DSI_LANE_GROUP(Lane));
  1512. switch(CommDelay)
  1513. {
  1514. case DSI_SLEW_RATE_HSTX:
  1515. if(Lane == DSI_CLOCK_LANE)
  1516. {
  1517. /* High-Speed Transmission Slew Rate Control on Clock Lane */
  1518. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
  1519. hdsi->Instance->WPCR[1U] |= Value<<16U;
  1520. }
  1521. else if(Lane == DSI_DATA_LANES)
  1522. {
  1523. /* High-Speed Transmission Slew Rate Control on Data Lanes */
  1524. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
  1525. hdsi->Instance->WPCR[1U] |= Value<<18U;
  1526. }
  1527. else
  1528. {
  1529. /* Process unlocked */
  1530. __HAL_UNLOCK(hdsi);
  1531. return HAL_ERROR;
  1532. }
  1533. break;
  1534. case DSI_SLEW_RATE_LPTX:
  1535. if(Lane == DSI_CLOCK_LANE)
  1536. {
  1537. /* Low-Power transmission Slew Rate Compensation on Clock Lane */
  1538. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
  1539. hdsi->Instance->WPCR[1U] |= Value<<6U;
  1540. }
  1541. else if(Lane == DSI_DATA_LANES)
  1542. {
  1543. /* Low-Power transmission Slew Rate Compensation on Data Lanes */
  1544. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
  1545. hdsi->Instance->WPCR[1U] |= Value<<8U;
  1546. }
  1547. else
  1548. {
  1549. /* Process unlocked */
  1550. __HAL_UNLOCK(hdsi);
  1551. return HAL_ERROR;
  1552. }
  1553. break;
  1554. case DSI_HS_DELAY:
  1555. if(Lane == DSI_CLOCK_LANE)
  1556. {
  1557. /* High-Speed Transmission Delay on Clock Lane */
  1558. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
  1559. hdsi->Instance->WPCR[1U] |= Value;
  1560. }
  1561. else if(Lane == DSI_DATA_LANES)
  1562. {
  1563. /* High-Speed Transmission Delay on Data Lanes */
  1564. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
  1565. hdsi->Instance->WPCR[1U] |= Value<<2U;
  1566. }
  1567. else
  1568. {
  1569. /* Process unlocked */
  1570. __HAL_UNLOCK(hdsi);
  1571. return HAL_ERROR;
  1572. }
  1573. break;
  1574. default:
  1575. break;
  1576. }
  1577. /* Process unlocked */
  1578. __HAL_UNLOCK(hdsi);
  1579. return HAL_OK;
  1580. }
  1581. /**
  1582. * @brief Low-Power Reception Filter Tuning
  1583. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1584. * the configuration information for the DSI.
  1585. * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX
  1586. * @retval HAL status
  1587. */
  1588. HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
  1589. {
  1590. /* Process locked */
  1591. __HAL_LOCK(hdsi);
  1592. /* Low-Power RX low-pass Filtering Tuning */
  1593. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
  1594. hdsi->Instance->WPCR[1U] |= Frequency<<25U;
  1595. /* Process unlocked */
  1596. __HAL_UNLOCK(hdsi);
  1597. return HAL_OK;
  1598. }
  1599. /**
  1600. * @brief Activate an additional current path on all lanes to meet the SDDTx parameter
  1601. * defined in the MIPI D-PHY specification
  1602. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1603. * the configuration information for the DSI.
  1604. * @param State: ENABLE or DISABLE
  1605. * @retval HAL status
  1606. */
  1607. HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
  1608. {
  1609. /* Process locked */
  1610. __HAL_LOCK(hdsi);
  1611. /* Check function parameters */
  1612. assert_param(IS_FUNCTIONAL_STATE(State));
  1613. /* Activate/Disactivate additional current path on all lanes */
  1614. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
  1615. hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U);
  1616. /* Process unlocked */
  1617. __HAL_UNLOCK(hdsi);
  1618. return HAL_OK;
  1619. }
  1620. /**
  1621. * @brief Custom lane pins configuration
  1622. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1623. * the configuration information for the DSI.
  1624. * @param CustomLane: Function to be applyed on selected lane.
  1625. * This parameter can be any value of @ref DSI_CustomLane
  1626. * @param Lane: select between clock or data lane 0 or data lane 1.
  1627. * This parameter can be any value of @ref DSI_Lane_Select
  1628. * @param State: ENABLE or DISABLE
  1629. * @retval HAL status
  1630. */
  1631. HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
  1632. {
  1633. /* Process locked */
  1634. __HAL_LOCK(hdsi);
  1635. /* Check function parameters */
  1636. assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
  1637. assert_param(IS_DSI_LANE(Lane));
  1638. assert_param(IS_FUNCTIONAL_STATE(State));
  1639. switch(CustomLane)
  1640. {
  1641. case DSI_SWAP_LANE_PINS:
  1642. if(Lane == DSI_CLK_LANE)
  1643. {
  1644. /* Swap pins on clock lane */
  1645. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
  1646. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);
  1647. }
  1648. else if(Lane == DSI_DATA_LANE0)
  1649. {
  1650. /* Swap pins on data lane 0 */
  1651. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
  1652. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);
  1653. }
  1654. else if(Lane == DSI_DATA_LANE1)
  1655. {
  1656. /* Swap pins on data lane 1 */
  1657. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
  1658. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
  1659. }
  1660. else
  1661. {
  1662. /* Process unlocked */
  1663. __HAL_UNLOCK(hdsi);
  1664. return HAL_ERROR;
  1665. }
  1666. break;
  1667. case DSI_INVERT_HS_SIGNAL:
  1668. if(Lane == DSI_CLK_LANE)
  1669. {
  1670. /* Invert HS signal on clock lane */
  1671. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
  1672. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);
  1673. }
  1674. else if(Lane == DSI_DATA_LANE0)
  1675. {
  1676. /* Invert HS signal on data lane 0 */
  1677. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
  1678. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);
  1679. }
  1680. else if(Lane == DSI_DATA_LANE1)
  1681. {
  1682. /* Invert HS signal on data lane 1 */
  1683. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
  1684. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);
  1685. }
  1686. else
  1687. {
  1688. /* Process unlocked */
  1689. __HAL_UNLOCK(hdsi);
  1690. return HAL_ERROR;
  1691. }
  1692. break;
  1693. default:
  1694. break;
  1695. }
  1696. /* Process unlocked */
  1697. __HAL_UNLOCK(hdsi);
  1698. return HAL_OK;
  1699. }
  1700. /**
  1701. * @brief Set custom timing for the PHY
  1702. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1703. * the configuration information for the DSI.
  1704. * @param Timing: PHY timing to be adjusted.
  1705. * This parameter can be any value of @ref DSI_PHY_Timing
  1706. * @param State: ENABLE or DISABLE
  1707. * @param Value: Custom value of the timing
  1708. * @retval HAL status
  1709. */
  1710. HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
  1711. {
  1712. /* Process locked */
  1713. __HAL_LOCK(hdsi);
  1714. /* Check function parameters */
  1715. assert_param(IS_DSI_PHY_TIMING(Timing));
  1716. assert_param(IS_FUNCTIONAL_STATE(State));
  1717. switch(Timing)
  1718. {
  1719. case DSI_TCLK_POST:
  1720. /* Enable/Disable custom timing setting */
  1721. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
  1722. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);
  1723. if(State != DISABLE)
  1724. {
  1725. /* Set custom value */
  1726. hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
  1727. hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;
  1728. }
  1729. break;
  1730. case DSI_TLPX_CLK:
  1731. /* Enable/Disable custom timing setting */
  1732. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
  1733. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);
  1734. if(State != DISABLE)
  1735. {
  1736. /* Set custom value */
  1737. hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
  1738. hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;
  1739. }
  1740. break;
  1741. case DSI_THS_EXIT:
  1742. /* Enable/Disable custom timing setting */
  1743. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
  1744. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);
  1745. if(State != DISABLE)
  1746. {
  1747. /* Set custom value */
  1748. hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
  1749. hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;
  1750. }
  1751. break;
  1752. case DSI_TLPX_DATA:
  1753. /* Enable/Disable custom timing setting */
  1754. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
  1755. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);
  1756. if(State != DISABLE)
  1757. {
  1758. /* Set custom value */
  1759. hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
  1760. hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;
  1761. }
  1762. break;
  1763. case DSI_THS_ZERO:
  1764. /* Enable/Disable custom timing setting */
  1765. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
  1766. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);
  1767. if(State != DISABLE)
  1768. {
  1769. /* Set custom value */
  1770. hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
  1771. hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;
  1772. }
  1773. break;
  1774. case DSI_THS_TRAIL:
  1775. /* Enable/Disable custom timing setting */
  1776. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
  1777. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);
  1778. if(State != DISABLE)
  1779. {
  1780. /* Set custom value */
  1781. hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
  1782. hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;
  1783. }
  1784. break;
  1785. case DSI_THS_PREPARE:
  1786. /* Enable/Disable custom timing setting */
  1787. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
  1788. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);
  1789. if(State != DISABLE)
  1790. {
  1791. /* Set custom value */
  1792. hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
  1793. hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;
  1794. }
  1795. break;
  1796. case DSI_TCLK_ZERO:
  1797. /* Enable/Disable custom timing setting */
  1798. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
  1799. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);
  1800. if(State != DISABLE)
  1801. {
  1802. /* Set custom value */
  1803. hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
  1804. hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;
  1805. }
  1806. break;
  1807. case DSI_TCLK_PREPARE:
  1808. /* Enable/Disable custom timing setting */
  1809. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
  1810. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);
  1811. if(State != DISABLE)
  1812. {
  1813. /* Set custom value */
  1814. hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
  1815. hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;
  1816. }
  1817. break;
  1818. default:
  1819. break;
  1820. }
  1821. /* Process unlocked */
  1822. __HAL_UNLOCK(hdsi);
  1823. return HAL_OK;
  1824. }
  1825. /**
  1826. * @brief Force the Clock/Data Lane in TX Stop Mode
  1827. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1828. * the configuration information for the DSI.
  1829. * @param Lane: select between clock or data lanes.
  1830. * This parameter can be any value of @ref DSI_Lane_Group
  1831. * @param State: ENABLE or DISABLE
  1832. * @retval HAL status
  1833. */
  1834. HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
  1835. {
  1836. /* Process locked */
  1837. __HAL_LOCK(hdsi);
  1838. /* Check function parameters */
  1839. assert_param(IS_DSI_LANE_GROUP(Lane));
  1840. assert_param(IS_FUNCTIONAL_STATE(State));
  1841. if(Lane == DSI_CLOCK_LANE)
  1842. {
  1843. /* Force/Unforce the Clock Lane in TX Stop Mode */
  1844. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
  1845. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);
  1846. }
  1847. else if(Lane == DSI_DATA_LANES)
  1848. {
  1849. /* Force/Unforce the Data Lanes in TX Stop Mode */
  1850. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
  1851. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);
  1852. }
  1853. else
  1854. {
  1855. /* Process unlocked */
  1856. __HAL_UNLOCK(hdsi);
  1857. return HAL_ERROR;
  1858. }
  1859. /* Process unlocked */
  1860. __HAL_UNLOCK(hdsi);
  1861. return HAL_OK;
  1862. }
  1863. /**
  1864. * @brief Force LP Receiver in Low-Power Mode
  1865. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1866. * the configuration information for the DSI.
  1867. * @param State: ENABLE or DISABLE
  1868. * @retval HAL status
  1869. */
  1870. HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
  1871. {
  1872. /* Process locked */
  1873. __HAL_LOCK(hdsi);
  1874. /* Check function parameters */
  1875. assert_param(IS_FUNCTIONAL_STATE(State));
  1876. /* Force/Unforce LP Receiver in Low-Power Mode */
  1877. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
  1878. hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U);
  1879. /* Process unlocked */
  1880. __HAL_UNLOCK(hdsi);
  1881. return HAL_OK;
  1882. }
  1883. /**
  1884. * @brief Force Data Lanes in RX Mode after a BTA
  1885. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1886. * the configuration information for the DSI.
  1887. * @param State: ENABLE or DISABLE
  1888. * @retval HAL status
  1889. */
  1890. HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
  1891. {
  1892. /* Process locked */
  1893. __HAL_LOCK(hdsi);
  1894. /* Check function parameters */
  1895. assert_param(IS_FUNCTIONAL_STATE(State));
  1896. /* Force Data Lanes in RX Mode */
  1897. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
  1898. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U);
  1899. /* Process unlocked */
  1900. __HAL_UNLOCK(hdsi);
  1901. return HAL_OK;
  1902. }
  1903. /**
  1904. * @brief Enable a pull-down on the lanes to prevent from floating states when unused
  1905. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1906. * the configuration information for the DSI.
  1907. * @param State: ENABLE or DISABLE
  1908. * @retval HAL status
  1909. */
  1910. HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
  1911. {
  1912. /* Process locked */
  1913. __HAL_LOCK(hdsi);
  1914. /* Check function parameters */
  1915. assert_param(IS_FUNCTIONAL_STATE(State));
  1916. /* Enable/Disable pull-down on lanes */
  1917. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
  1918. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U);
  1919. /* Process unlocked */
  1920. __HAL_UNLOCK(hdsi);
  1921. return HAL_OK;
  1922. }
  1923. /**
  1924. * @brief Switch off the contention detection on data lanes
  1925. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1926. * the configuration information for the DSI.
  1927. * @param State: ENABLE or DISABLE
  1928. * @retval HAL status
  1929. */
  1930. HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
  1931. {
  1932. /* Process locked */
  1933. __HAL_LOCK(hdsi);
  1934. /* Check function parameters */
  1935. assert_param(IS_FUNCTIONAL_STATE(State));
  1936. /* Contention Detection on Data Lanes OFF */
  1937. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
  1938. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U);
  1939. /* Process unlocked */
  1940. __HAL_UNLOCK(hdsi);
  1941. return HAL_OK;
  1942. }
  1943. /**
  1944. * @}
  1945. */
  1946. /** @defgroup DSI_Group4 Peripheral State and Errors functions
  1947. * @brief Peripheral State and Errors functions
  1948. *
  1949. @verbatim
  1950. ===============================================================================
  1951. ##### Peripheral State and Errors functions #####
  1952. ===============================================================================
  1953. [..]
  1954. This subsection provides functions allowing to
  1955. (+) Check the DSI state.
  1956. (+) Get error code.
  1957. @endverbatim
  1958. * @{
  1959. */
  1960. /**
  1961. * @brief Return the DSI state
  1962. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1963. * the configuration information for the DSI.
  1964. * @retval HAL state
  1965. */
  1966. HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
  1967. {
  1968. return hdsi->State;
  1969. }
  1970. /**
  1971. * @brief Return the DSI error code
  1972. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1973. * the configuration information for the DSI.
  1974. * @retval DSI Error Code
  1975. */
  1976. uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
  1977. {
  1978. /* Get the error code */
  1979. return hdsi->ErrorCode;
  1980. }
  1981. /**
  1982. * @}
  1983. */
  1984. /**
  1985. * @}
  1986. */
  1987. /**
  1988. * @}
  1989. */
  1990. #endif /* DSI */
  1991. #endif /* HAL_DSI_MODULE_ENABLED */
  1992. /**
  1993. * @}
  1994. */
  1995. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/