i2c_api.c 34 KB

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  1. /* mbed Microcontroller Library
  2. *******************************************************************************
  3. * Copyright (c) 2015, STMicroelectronics
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice,
  10. * this list of conditions and the following disclaimer.
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  15. * may be used to endorse or promote products derived from this software
  16. * without specific prior written permission.
  17. *
  18. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  19. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  21. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  22. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  24. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  25. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28. *******************************************************************************
  29. */
  30. #include "mbed_assert.h"
  31. #include "i2c_api.h"
  32. #include "platform/mbed_wait_api.h"
  33. #if DEVICE_I2C
  34. #include "cmsis.h"
  35. #include "pinmap.h"
  36. #include "PeripheralPins.h"
  37. #include "i2c_device.h" // family specific defines
  38. #ifndef DEBUG_STDIO
  39. # define DEBUG_STDIO 0
  40. #endif
  41. #if DEBUG_STDIO
  42. # include <stdio.h>
  43. # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
  44. #else
  45. # define DEBUG_PRINTF(...) {}
  46. #endif
  47. #if DEVICE_I2C_ASYNCH
  48. #define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c))
  49. #else
  50. #define I2C_S(obj) (struct i2c_s *) (obj)
  51. #endif
  52. /* Family specific description for I2C */
  53. #define I2C_NUM (5)
  54. static I2C_HandleTypeDef *i2c_handles[I2C_NUM];
  55. /* Timeout values are based on core clock and I2C clock.
  56. The BYTE_TIMEOUT is computed as twice the number of cycles it would
  57. take to send 10 bits over I2C. Most Flags should take less than that.
  58. This is for immediate FLAG or ACK check.
  59. */
  60. #define BYTE_TIMEOUT ((SystemCoreClock / obj_s->hz) * 2 * 10)
  61. /* Timeout values based on I2C clock.
  62. The BYTE_TIMEOUT_US is computed as 3x the time in us it would
  63. take to send 10 bits over I2C. Most Flags should take less than that.
  64. This is for complete transfers check.
  65. */
  66. #define BYTE_TIMEOUT_US ((SystemCoreClock / obj_s->hz) * 3 * 10)
  67. /* Timeout values for flags and events waiting loops. These timeouts are
  68. not based on accurate values, they just guarantee that the application will
  69. not remain stuck if the I2C communication is corrupted.
  70. */
  71. #define FLAG_TIMEOUT ((int)0x1000)
  72. /* GENERIC INIT and HELPERS FUNCTIONS */
  73. #if defined(I2C1_BASE)
  74. static void i2c1_irq(void)
  75. {
  76. I2C_HandleTypeDef *handle = i2c_handles[0];
  77. HAL_I2C_EV_IRQHandler(handle);
  78. HAL_I2C_ER_IRQHandler(handle);
  79. }
  80. #endif
  81. #if defined(I2C2_BASE)
  82. static void i2c2_irq(void)
  83. {
  84. I2C_HandleTypeDef *handle = i2c_handles[1];
  85. HAL_I2C_EV_IRQHandler(handle);
  86. HAL_I2C_ER_IRQHandler(handle);
  87. }
  88. #endif
  89. #if defined(I2C3_BASE)
  90. static void i2c3_irq(void)
  91. {
  92. I2C_HandleTypeDef *handle = i2c_handles[2];
  93. HAL_I2C_EV_IRQHandler(handle);
  94. HAL_I2C_ER_IRQHandler(handle);
  95. }
  96. #endif
  97. #if defined(I2C4_BASE)
  98. static void i2c4_irq(void)
  99. {
  100. I2C_HandleTypeDef *handle = i2c_handles[3];
  101. HAL_I2C_EV_IRQHandler(handle);
  102. HAL_I2C_ER_IRQHandler(handle);
  103. }
  104. #endif
  105. #if defined(FMPI2C1_BASE)
  106. static void i2c5_irq(void)
  107. {
  108. I2C_HandleTypeDef *handle = i2c_handles[4];
  109. HAL_I2C_EV_IRQHandler(handle);
  110. HAL_I2C_ER_IRQHandler(handle);
  111. }
  112. #endif
  113. void i2c_ev_err_enable(i2c_t *obj, uint32_t handler)
  114. {
  115. struct i2c_s *obj_s = I2C_S(obj);
  116. IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
  117. IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
  118. /* default prio in master case is set to 2 */
  119. uint32_t prio = 2;
  120. /* Set up ITs using IRQ and handler tables */
  121. NVIC_SetVector(irq_event_n, handler);
  122. NVIC_SetVector(irq_error_n, handler);
  123. #if DEVICE_I2CSLAVE
  124. /* Set higher priority to slave device than master.
  125. * In case a device makes use of both master and slave, the
  126. * slave needs higher responsiveness.
  127. */
  128. if (obj_s->slave) {
  129. prio = 1;
  130. }
  131. #endif
  132. NVIC_SetPriority(irq_event_n, prio);
  133. NVIC_SetPriority(irq_error_n, prio);
  134. NVIC_EnableIRQ(irq_event_n);
  135. NVIC_EnableIRQ(irq_error_n);
  136. }
  137. void i2c_ev_err_disable(i2c_t *obj)
  138. {
  139. struct i2c_s *obj_s = I2C_S(obj);
  140. IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
  141. IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
  142. HAL_NVIC_DisableIRQ(irq_event_n);
  143. HAL_NVIC_DisableIRQ(irq_error_n);
  144. }
  145. uint32_t i2c_get_irq_handler(i2c_t *obj)
  146. {
  147. struct i2c_s *obj_s = I2C_S(obj);
  148. I2C_HandleTypeDef *handle = &(obj_s->handle);
  149. uint32_t handler = 0;
  150. switch (obj_s->index) {
  151. #if defined(I2C1_BASE)
  152. case 0:
  153. handler = (uint32_t)&i2c1_irq;
  154. break;
  155. #endif
  156. #if defined(I2C2_BASE)
  157. case 1:
  158. handler = (uint32_t)&i2c2_irq;
  159. break;
  160. #endif
  161. #if defined(I2C3_BASE)
  162. case 2:
  163. handler = (uint32_t)&i2c3_irq;
  164. break;
  165. #endif
  166. #if defined(I2C4_BASE)
  167. case 3:
  168. handler = (uint32_t)&i2c4_irq;
  169. break;
  170. #endif
  171. #if defined(FMPI2C1_BASE)
  172. case 4:
  173. handler = (uint32_t)&i2c5_irq;
  174. break;
  175. #endif
  176. }
  177. i2c_handles[obj_s->index] = handle;
  178. return handler;
  179. }
  180. void i2c_hw_reset(i2c_t *obj)
  181. {
  182. int timeout;
  183. struct i2c_s *obj_s = I2C_S(obj);
  184. I2C_HandleTypeDef *handle = &(obj_s->handle);
  185. handle->Instance = (I2C_TypeDef *)(obj_s->i2c);
  186. // wait before reset
  187. timeout = BYTE_TIMEOUT;
  188. while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
  189. #if defined I2C1_BASE
  190. if (obj_s->i2c == I2C_1) {
  191. __HAL_RCC_I2C1_FORCE_RESET();
  192. __HAL_RCC_I2C1_RELEASE_RESET();
  193. }
  194. #endif
  195. #if defined I2C2_BASE
  196. if (obj_s->i2c == I2C_2) {
  197. __HAL_RCC_I2C2_FORCE_RESET();
  198. __HAL_RCC_I2C2_RELEASE_RESET();
  199. }
  200. #endif
  201. #if defined I2C3_BASE
  202. if (obj_s->i2c == I2C_3) {
  203. __HAL_RCC_I2C3_FORCE_RESET();
  204. __HAL_RCC_I2C3_RELEASE_RESET();
  205. }
  206. #endif
  207. #if defined I2C4_BASE
  208. if (obj_s->i2c == I2C_4) {
  209. __HAL_RCC_I2C4_FORCE_RESET();
  210. __HAL_RCC_I2C4_RELEASE_RESET();
  211. }
  212. #endif
  213. #if defined FMPI2C1_BASE
  214. if (obj_s->i2c == FMPI2C_1) {
  215. __HAL_RCC_FMPI2C1_FORCE_RESET();
  216. __HAL_RCC_FMPI2C1_RELEASE_RESET();
  217. }
  218. #endif
  219. }
  220. void i2c_sw_reset(i2c_t *obj)
  221. {
  222. struct i2c_s *obj_s = I2C_S(obj);
  223. I2C_HandleTypeDef *handle = &(obj_s->handle);
  224. /* SW reset procedure:
  225. * PE must be kept low during at least 3 APB clock cycles
  226. * in order to perform the software reset.
  227. * This is ensured by writing the following software sequence:
  228. * - Write PE=0
  229. * - Check PE=0
  230. * - Write PE=1.
  231. */
  232. handle->Instance->CR1 &= ~I2C_CR1_PE;
  233. while (handle->Instance->CR1 & I2C_CR1_PE);
  234. handle->Instance->CR1 |= I2C_CR1_PE;
  235. }
  236. void i2c_init(i2c_t *obj, PinName sda, PinName scl)
  237. {
  238. struct i2c_s *obj_s = I2C_S(obj);
  239. // Determine the I2C to use
  240. I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
  241. I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
  242. obj_s->sda = sda;
  243. obj_s->scl = scl;
  244. obj_s->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
  245. MBED_ASSERT(obj_s->i2c != (I2CName)NC);
  246. #if defined I2C1_BASE
  247. // Enable I2C1 clock and pinout if not done
  248. if (obj_s->i2c == I2C_1) {
  249. obj_s->index = 0;
  250. __HAL_RCC_I2C1_CLK_ENABLE();
  251. // Configure I2C pins
  252. obj_s->event_i2cIRQ = I2C1_EV_IRQn;
  253. obj_s->error_i2cIRQ = I2C1_ER_IRQn;
  254. }
  255. #endif
  256. #if defined I2C2_BASE
  257. // Enable I2C2 clock and pinout if not done
  258. if (obj_s->i2c == I2C_2) {
  259. obj_s->index = 1;
  260. __HAL_RCC_I2C2_CLK_ENABLE();
  261. obj_s->event_i2cIRQ = I2C2_EV_IRQn;
  262. obj_s->error_i2cIRQ = I2C2_ER_IRQn;
  263. }
  264. #endif
  265. #if defined I2C3_BASE
  266. // Enable I2C3 clock and pinout if not done
  267. if (obj_s->i2c == I2C_3) {
  268. obj_s->index = 2;
  269. __HAL_RCC_I2C3_CLK_ENABLE();
  270. obj_s->event_i2cIRQ = I2C3_EV_IRQn;
  271. obj_s->error_i2cIRQ = I2C3_ER_IRQn;
  272. }
  273. #endif
  274. #if defined I2C4_BASE
  275. // Enable I2C3 clock and pinout if not done
  276. if (obj_s->i2c == I2C_4) {
  277. obj_s->index = 3;
  278. __HAL_RCC_I2C4_CLK_ENABLE();
  279. obj_s->event_i2cIRQ = I2C4_EV_IRQn;
  280. obj_s->error_i2cIRQ = I2C4_ER_IRQn;
  281. }
  282. #endif
  283. #if defined FMPI2C1_BASE
  284. // Enable I2C3 clock and pinout if not done
  285. if (obj_s->i2c == FMPI2C_1) {
  286. obj_s->index = 4;
  287. __HAL_RCC_FMPI2C1_CLK_ENABLE();
  288. obj_s->event_i2cIRQ = FMPI2C1_EV_IRQn;
  289. obj_s->error_i2cIRQ = FMPI2C1_ER_IRQn;
  290. }
  291. #endif
  292. // Configure I2C pins
  293. pinmap_pinout(sda, PinMap_I2C_SDA);
  294. pinmap_pinout(scl, PinMap_I2C_SCL);
  295. pin_mode(sda, OpenDrainNoPull);
  296. pin_mode(scl, OpenDrainNoPull);
  297. // I2C configuration
  298. // Default hz value used for timeout computation
  299. if (!obj_s->hz) {
  300. obj_s->hz = 100000; // 100 kHz per default
  301. }
  302. // Reset to clear pending flags if any
  303. i2c_hw_reset(obj);
  304. i2c_frequency(obj, obj_s->hz);
  305. #if DEVICE_I2CSLAVE
  306. // I2C master by default
  307. obj_s->slave = 0;
  308. obj_s->pending_slave_tx_master_rx = 0;
  309. obj_s->pending_slave_rx_maxter_tx = 0;
  310. #endif
  311. // I2C Xfer operation init
  312. obj_s->event = 0;
  313. obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
  314. #ifdef I2C_IP_VERSION_V2
  315. obj_s->pending_start = 0;
  316. #endif
  317. }
  318. void i2c_frequency(i2c_t *obj, int hz)
  319. {
  320. int timeout;
  321. struct i2c_s *obj_s = I2C_S(obj);
  322. I2C_HandleTypeDef *handle = &(obj_s->handle);
  323. // wait before init
  324. timeout = BYTE_TIMEOUT;
  325. while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
  326. #ifdef I2C_IP_VERSION_V1
  327. handle->Init.ClockSpeed = hz;
  328. handle->Init.DutyCycle = I2C_DUTYCYCLE_2;
  329. #endif
  330. #ifdef I2C_IP_VERSION_V2
  331. /* Only predefined timing for below frequencies are supported */
  332. MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
  333. handle->Init.Timing = get_i2c_timing(hz);
  334. // Enable the Fast Mode Plus capability
  335. if (hz == 1000000) {
  336. #if defined(I2C1_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C1)
  337. if (obj_s->i2c == I2C_1) {
  338. HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C1);
  339. }
  340. #endif
  341. #if defined(I2C2_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C2)
  342. if (obj_s->i2c == I2C_2) {
  343. HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C2);
  344. }
  345. #endif
  346. #if defined(I2C3_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C3)
  347. if (obj_s->i2c == I2C_3) {
  348. HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C3);
  349. }
  350. #endif
  351. #if defined(I2C4_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C4)
  352. if (obj_s->i2c == I2C_4) {
  353. HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C4);
  354. }
  355. #endif
  356. }
  357. #endif //I2C_IP_VERSION_V2
  358. /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
  359. #if defined(I2C1_BASE) && defined (__HAL_RCC_I2C1_CONFIG)
  360. if (obj_s->i2c == I2C_1) {
  361. __HAL_RCC_I2C1_CONFIG(I2CAPI_I2C1_CLKSRC);
  362. }
  363. #endif
  364. #if defined(I2C2_BASE) && defined(__HAL_RCC_I2C2_CONFIG)
  365. if (obj_s->i2c == I2C_2) {
  366. __HAL_RCC_I2C2_CONFIG(I2CAPI_I2C2_CLKSRC);
  367. }
  368. #endif
  369. #if defined(I2C3_BASE) && defined(__HAL_RCC_I2C3_CONFIG)
  370. if (obj_s->i2c == I2C_3) {
  371. __HAL_RCC_I2C3_CONFIG(I2CAPI_I2C3_CLKSRC);
  372. }
  373. #endif
  374. #if defined(I2C4_BASE) && defined(__HAL_RCC_I2C4_CONFIG)
  375. if (obj_s->i2c == I2C_4) {
  376. __HAL_RCC_I2C4_CONFIG(I2CAPI_I2C4_CLKSRC);
  377. }
  378. #endif
  379. #ifdef I2C_ANALOGFILTER_ENABLE
  380. /* Enable the Analog I2C Filter */
  381. HAL_I2CEx_ConfigAnalogFilter(handle, I2C_ANALOGFILTER_ENABLE);
  382. #endif
  383. // I2C configuration
  384. handle->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
  385. handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
  386. handle->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
  387. handle->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
  388. handle->Init.OwnAddress1 = 0;
  389. handle->Init.OwnAddress2 = 0;
  390. HAL_I2C_Init(handle);
  391. /* store frequency for timeout computation */
  392. obj_s->hz = hz;
  393. }
  394. i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c)
  395. {
  396. /* Aim of the function is to get i2c_s pointer using hi2c pointer */
  397. /* Highly inspired from magical linux kernel's "container_of" */
  398. /* (which was not directly used since not compatible with IAR toolchain) */
  399. struct i2c_s *obj_s;
  400. i2c_t *obj;
  401. obj_s = (struct i2c_s *)((char *)hi2c - offsetof(struct i2c_s, handle));
  402. obj = (i2c_t *)((char *)obj_s - offsetof(i2c_t, i2c));
  403. return (obj);
  404. }
  405. void i2c_reset(i2c_t *obj)
  406. {
  407. struct i2c_s *obj_s = I2C_S(obj);
  408. /* As recommended in i2c_api.h, mainly send stop */
  409. i2c_stop(obj);
  410. /* then re-init */
  411. i2c_init(obj, obj_s->sda, obj_s->scl);
  412. }
  413. /*
  414. * UNITARY APIS.
  415. * For very basic operations, direct registers access is needed
  416. * There are 2 different IPs version that need to be supported
  417. */
  418. #ifdef I2C_IP_VERSION_V1
  419. int i2c_start(i2c_t *obj)
  420. {
  421. int timeout;
  422. struct i2c_s *obj_s = I2C_S(obj);
  423. I2C_HandleTypeDef *handle = &(obj_s->handle);
  424. // Clear Acknowledge failure flag
  425. __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_AF);
  426. // Wait the STOP condition has been previously correctly sent
  427. // This timeout can be avoid in some specific cases by simply clearing the STOP bit
  428. timeout = FLAG_TIMEOUT;
  429. while ((handle->Instance->CR1 & I2C_CR1_STOP) == I2C_CR1_STOP) {
  430. if ((timeout--) == 0) {
  431. return 1;
  432. }
  433. }
  434. // Generate the START condition
  435. handle->Instance->CR1 |= I2C_CR1_START;
  436. // Wait the START condition has been correctly sent
  437. timeout = FLAG_TIMEOUT;
  438. while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_SB) == RESET) {
  439. if ((timeout--) == 0) {
  440. return 1;
  441. }
  442. }
  443. return 0;
  444. }
  445. int i2c_stop(i2c_t *obj)
  446. {
  447. struct i2c_s *obj_s = I2C_S(obj);
  448. I2C_TypeDef *i2c = (I2C_TypeDef *)obj_s->i2c;
  449. // Generate the STOP condition
  450. i2c->CR1 |= I2C_CR1_STOP;
  451. /* In case of mixed usage of the APIs (unitary + SYNC)
  452. * re-init HAL state
  453. */
  454. if (obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME) {
  455. i2c_init(obj, obj_s->sda, obj_s->scl);
  456. }
  457. return 0;
  458. }
  459. int i2c_byte_read(i2c_t *obj, int last)
  460. {
  461. int timeout;
  462. struct i2c_s *obj_s = I2C_S(obj);
  463. I2C_HandleTypeDef *handle = &(obj_s->handle);
  464. if (last) {
  465. // Don't acknowledge the last byte
  466. handle->Instance->CR1 &= ~I2C_CR1_ACK;
  467. } else {
  468. // Acknowledge the byte
  469. handle->Instance->CR1 |= I2C_CR1_ACK;
  470. }
  471. // Wait until the byte is received
  472. timeout = FLAG_TIMEOUT;
  473. while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE) == RESET) {
  474. if ((timeout--) == 0) {
  475. return -1;
  476. }
  477. }
  478. return (int)handle->Instance->DR;
  479. }
  480. int i2c_byte_write(i2c_t *obj, int data)
  481. {
  482. int timeout;
  483. struct i2c_s *obj_s = I2C_S(obj);
  484. I2C_HandleTypeDef *handle = &(obj_s->handle);
  485. handle->Instance->DR = (uint8_t)data;
  486. // Wait until the byte (might be the address) is transmitted
  487. timeout = FLAG_TIMEOUT;
  488. while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE) == RESET) &&
  489. (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BTF) == RESET) &&
  490. (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) == RESET)) {
  491. if ((timeout--) == 0) {
  492. return 2;
  493. }
  494. }
  495. if (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) != RESET) {
  496. __HAL_I2C_CLEAR_ADDRFLAG(handle);
  497. }
  498. return 1;
  499. }
  500. #endif //I2C_IP_VERSION_V1
  501. #ifdef I2C_IP_VERSION_V2
  502. int i2c_start(i2c_t *obj)
  503. {
  504. struct i2c_s *obj_s = I2C_S(obj);
  505. /* This I2C IP doesn't */
  506. obj_s->pending_start = 1;
  507. return 0;
  508. }
  509. int i2c_stop(i2c_t *obj)
  510. {
  511. struct i2c_s *obj_s = I2C_S(obj);
  512. I2C_HandleTypeDef *handle = &(obj_s->handle);
  513. int timeout = FLAG_TIMEOUT;
  514. #if DEVICE_I2CSLAVE
  515. if (obj_s->slave) {
  516. /* re-init slave when stop is requested */
  517. i2c_init(obj, obj_s->sda, obj_s->scl);
  518. return 0;
  519. }
  520. #endif
  521. // Disable reload mode
  522. handle->Instance->CR2 &= (uint32_t)~I2C_CR2_RELOAD;
  523. // Generate the STOP condition
  524. handle->Instance->CR2 |= I2C_CR2_STOP;
  525. timeout = FLAG_TIMEOUT;
  526. while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_STOPF)) {
  527. if ((timeout--) == 0) {
  528. return I2C_ERROR_BUS_BUSY;
  529. }
  530. }
  531. /* Clear STOP Flag */
  532. __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_STOPF);
  533. /* Erase slave address, this wiil be used as a marker
  534. * to know when we need to prepare next start */
  535. handle->Instance->CR2 &= ~I2C_CR2_SADD;
  536. /*
  537. * V2 IP is meant for automatic STOP, not user STOP
  538. * SW reset the IP state machine before next transaction
  539. */
  540. i2c_sw_reset(obj);
  541. /* In case of mixed usage of the APIs (unitary + SYNC)
  542. * re-init HAL state */
  543. if (obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME) {
  544. i2c_init(obj, obj_s->sda, obj_s->scl);
  545. }
  546. return 0;
  547. }
  548. int i2c_byte_read(i2c_t *obj, int last)
  549. {
  550. struct i2c_s *obj_s = I2C_S(obj);
  551. I2C_HandleTypeDef *handle = &(obj_s->handle);
  552. int timeout = FLAG_TIMEOUT;
  553. uint32_t tmpreg = handle->Instance->CR2;
  554. char data;
  555. #if DEVICE_I2CSLAVE
  556. if (obj_s->slave) {
  557. return i2c_slave_read(obj, &data, 1);
  558. }
  559. #endif
  560. /* Then send data when there's room in the TX fifo */
  561. if ((tmpreg & I2C_CR2_RELOAD) != 0) {
  562. while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
  563. if ((timeout--) == 0) {
  564. DEBUG_PRINTF("timeout in byte_read\r\n");
  565. return -1;
  566. }
  567. }
  568. }
  569. /* Enable reload mode as we don't know how many bytes will be sent */
  570. /* and set transfer size to 1 */
  571. tmpreg |= I2C_CR2_RELOAD | (I2C_CR2_NBYTES & (1 << 16));
  572. /* Set the prepared configuration */
  573. handle->Instance->CR2 = tmpreg;
  574. timeout = FLAG_TIMEOUT;
  575. while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE)) {
  576. if ((timeout--) == 0) {
  577. return -1;
  578. }
  579. }
  580. /* Then Get Byte */
  581. data = handle->Instance->RXDR;
  582. if (last) {
  583. /* Disable Address Acknowledge */
  584. handle->Instance->CR2 |= I2C_CR2_NACK;
  585. }
  586. return data;
  587. }
  588. int i2c_byte_write(i2c_t *obj, int data)
  589. {
  590. struct i2c_s *obj_s = I2C_S(obj);
  591. I2C_HandleTypeDef *handle = &(obj_s->handle);
  592. int timeout = FLAG_TIMEOUT;
  593. uint32_t tmpreg = handle->Instance->CR2;
  594. #if DEVICE_I2CSLAVE
  595. if (obj_s->slave) {
  596. return i2c_slave_write(obj, (char *) &data, 1);
  597. }
  598. #endif
  599. if (obj_s->pending_start) {
  600. obj_s->pending_start = 0;
  601. //* First byte after the start is the address */
  602. tmpreg |= (uint32_t)((uint32_t)data & I2C_CR2_SADD);
  603. if (data & 0x01) {
  604. tmpreg |= I2C_CR2_START | I2C_CR2_RD_WRN;
  605. } else {
  606. tmpreg |= I2C_CR2_START;
  607. tmpreg &= ~I2C_CR2_RD_WRN;
  608. }
  609. /* Disable reload first to use it later */
  610. tmpreg &= ~I2C_CR2_RELOAD;
  611. /* Disable Autoend */
  612. tmpreg &= ~I2C_CR2_AUTOEND;
  613. /* Do not set any transfer size for now */
  614. tmpreg |= (I2C_CR2_NBYTES & (1 << 16));
  615. /* Set the prepared configuration */
  616. handle->Instance->CR2 = tmpreg;
  617. } else {
  618. /* Set the prepared configuration */
  619. tmpreg = handle->Instance->CR2;
  620. /* Then send data when there's room in the TX fifo */
  621. if ((tmpreg & I2C_CR2_RELOAD) != 0) {
  622. while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
  623. if ((timeout--) == 0) {
  624. DEBUG_PRINTF("timeout in byte_write\r\n");
  625. return 2;
  626. }
  627. }
  628. }
  629. /* Enable reload mode as we don't know how many bytes will eb sent */
  630. tmpreg |= I2C_CR2_RELOAD;
  631. /* Set transfer size to 1 */
  632. tmpreg |= (I2C_CR2_NBYTES & (1 << 16));
  633. /* Set the prepared configuration */
  634. handle->Instance->CR2 = tmpreg;
  635. /* Prepare next write */
  636. timeout = FLAG_TIMEOUT;
  637. while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE)) {
  638. if ((timeout--) == 0) {
  639. return 2;
  640. }
  641. }
  642. /* Write byte */
  643. handle->Instance->TXDR = data;
  644. }
  645. return 1;
  646. }
  647. #endif //I2C_IP_VERSION_V2
  648. /*
  649. * SYNC APIS
  650. */
  651. int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
  652. {
  653. struct i2c_s *obj_s = I2C_S(obj);
  654. I2C_HandleTypeDef *handle = &(obj_s->handle);
  655. int count = I2C_ERROR_BUS_BUSY, ret = 0;
  656. uint32_t timeout = 0;
  657. // Trick to remove compiler warning "left and right operands are identical" in some cases
  658. uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
  659. uint32_t op2 = I2C_LAST_FRAME;
  660. if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
  661. if (stop) {
  662. obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
  663. } else {
  664. obj_s->XferOperation = I2C_FIRST_FRAME;
  665. }
  666. } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
  667. (obj_s->XferOperation == I2C_NEXT_FRAME)) {
  668. if (stop) {
  669. obj_s->XferOperation = I2C_LAST_FRAME;
  670. } else {
  671. obj_s->XferOperation = I2C_NEXT_FRAME;
  672. }
  673. }
  674. obj_s->event = 0;
  675. /* Activate default IRQ handlers for sync mode
  676. * which would be overwritten in async mode
  677. */
  678. i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
  679. ret = HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
  680. if (ret == HAL_OK) {
  681. timeout = BYTE_TIMEOUT_US * (length + 1);
  682. /* transfer started : wait completion or timeout */
  683. while (!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
  684. wait_us(1);
  685. }
  686. i2c_ev_err_disable(obj);
  687. if ((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
  688. DEBUG_PRINTF(" TIMEOUT or error in i2c_read\r\n");
  689. /* re-init IP to try and get back in a working state */
  690. i2c_init(obj, obj_s->sda, obj_s->scl);
  691. } else {
  692. count = length;
  693. }
  694. } else {
  695. DEBUG_PRINTF("ERROR in i2c_read:%d\r\n", ret);
  696. }
  697. return count;
  698. }
  699. int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
  700. {
  701. struct i2c_s *obj_s = I2C_S(obj);
  702. I2C_HandleTypeDef *handle = &(obj_s->handle);
  703. int count = I2C_ERROR_BUS_BUSY, ret = 0;
  704. uint32_t timeout = 0;
  705. // Trick to remove compiler warning "left and right operands are identical" in some cases
  706. uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
  707. uint32_t op2 = I2C_LAST_FRAME;
  708. if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
  709. if (stop) {
  710. obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
  711. } else {
  712. obj_s->XferOperation = I2C_FIRST_FRAME;
  713. }
  714. } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
  715. (obj_s->XferOperation == I2C_NEXT_FRAME)) {
  716. if (stop) {
  717. obj_s->XferOperation = I2C_LAST_FRAME;
  718. } else {
  719. obj_s->XferOperation = I2C_NEXT_FRAME;
  720. }
  721. }
  722. obj_s->event = 0;
  723. i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
  724. ret = HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
  725. if (ret == HAL_OK) {
  726. timeout = BYTE_TIMEOUT_US * (length + 1);
  727. /* transfer started : wait completion or timeout */
  728. while (!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
  729. wait_us(1);
  730. }
  731. i2c_ev_err_disable(obj);
  732. if ((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
  733. DEBUG_PRINTF(" TIMEOUT or error in i2c_write\r\n");
  734. /* re-init IP to try and get back in a working state */
  735. i2c_init(obj, obj_s->sda, obj_s->scl);
  736. } else {
  737. count = length;
  738. }
  739. } else {
  740. DEBUG_PRINTF("ERROR in i2c_read\r\n");
  741. }
  742. return count;
  743. }
  744. void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
  745. {
  746. /* Get object ptr based on handler ptr */
  747. i2c_t *obj = get_i2c_obj(hi2c);
  748. struct i2c_s *obj_s = I2C_S(obj);
  749. #if DEVICE_I2C_ASYNCH
  750. /* Handle potential Tx/Rx use case */
  751. if ((obj->tx_buff.length) && (obj->rx_buff.length)) {
  752. if (obj_s->stop) {
  753. obj_s->XferOperation = I2C_LAST_FRAME;
  754. } else {
  755. obj_s->XferOperation = I2C_NEXT_FRAME;
  756. }
  757. HAL_I2C_Master_Sequential_Receive_IT(hi2c, obj_s->address, (uint8_t *)obj->rx_buff.buffer, obj->rx_buff.length, obj_s->XferOperation);
  758. } else
  759. #endif
  760. {
  761. /* Set event flag */
  762. obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
  763. }
  764. }
  765. void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
  766. {
  767. /* Get object ptr based on handler ptr */
  768. i2c_t *obj = get_i2c_obj(hi2c);
  769. struct i2c_s *obj_s = I2C_S(obj);
  770. /* Set event flag */
  771. obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
  772. }
  773. void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
  774. {
  775. /* Get object ptr based on handler ptr */
  776. i2c_t *obj = get_i2c_obj(hi2c);
  777. struct i2c_s *obj_s = I2C_S(obj);
  778. #if DEVICE_I2CSLAVE
  779. I2C_HandleTypeDef *handle = &(obj_s->handle);
  780. uint32_t address = 0;
  781. /* Store address to handle it after reset */
  782. if (obj_s->slave) {
  783. address = handle->Init.OwnAddress1;
  784. }
  785. #endif
  786. DEBUG_PRINTF("HAL_I2C_ErrorCallback:%d, index=%d\r\n", (int) hi2c->ErrorCode, obj_s->index);
  787. /* re-init IP to try and get back in a working state */
  788. i2c_init(obj, obj_s->sda, obj_s->scl);
  789. #if DEVICE_I2CSLAVE
  790. /* restore slave address */
  791. if (address != 0) {
  792. obj_s->slave = 1;
  793. i2c_slave_address(obj, 0, address, 0);
  794. }
  795. #endif
  796. /* Keep Set event flag */
  797. obj_s->event = I2C_EVENT_ERROR;
  798. }
  799. #if DEVICE_I2CSLAVE
  800. /* SLAVE API FUNCTIONS */
  801. void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
  802. {
  803. struct i2c_s *obj_s = I2C_S(obj);
  804. I2C_HandleTypeDef *handle = &(obj_s->handle);
  805. // I2C configuration
  806. handle->Init.OwnAddress1 = address;
  807. HAL_I2C_Init(handle);
  808. i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
  809. HAL_I2C_EnableListen_IT(handle);
  810. }
  811. void i2c_slave_mode(i2c_t *obj, int enable_slave)
  812. {
  813. struct i2c_s *obj_s = I2C_S(obj);
  814. I2C_HandleTypeDef *handle = &(obj_s->handle);
  815. if (enable_slave) {
  816. obj_s->slave = 1;
  817. HAL_I2C_EnableListen_IT(handle);
  818. } else {
  819. obj_s->slave = 0;
  820. HAL_I2C_DisableListen_IT(handle);
  821. }
  822. }
  823. // See I2CSlave.h
  824. #define NoData 0 // the slave has not been addressed
  825. #define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
  826. #define WriteGeneral 2 // the master is writing to all slave
  827. #define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
  828. void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
  829. {
  830. /* Get object ptr based on handler ptr */
  831. i2c_t *obj = get_i2c_obj(hi2c);
  832. struct i2c_s *obj_s = I2C_S(obj);
  833. /* Transfer direction in HAL is from Master point of view */
  834. if (TransferDirection == I2C_DIRECTION_RECEIVE) {
  835. obj_s->pending_slave_tx_master_rx = 1;
  836. }
  837. if (TransferDirection == I2C_DIRECTION_TRANSMIT) {
  838. obj_s->pending_slave_rx_maxter_tx = 1;
  839. }
  840. }
  841. void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle)
  842. {
  843. /* Get object ptr based on handler ptr */
  844. i2c_t *obj = get_i2c_obj(I2cHandle);
  845. struct i2c_s *obj_s = I2C_S(obj);
  846. obj_s->pending_slave_tx_master_rx = 0;
  847. }
  848. void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle)
  849. {
  850. /* Get object ptr based on handler ptr */
  851. i2c_t *obj = get_i2c_obj(I2cHandle);
  852. struct i2c_s *obj_s = I2C_S(obj);
  853. obj_s->pending_slave_rx_maxter_tx = 0;
  854. }
  855. void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
  856. {
  857. /* restart listening for master requests */
  858. HAL_I2C_EnableListen_IT(hi2c);
  859. }
  860. int i2c_slave_receive(i2c_t *obj)
  861. {
  862. struct i2c_s *obj_s = I2C_S(obj);
  863. int retValue = NoData;
  864. if (obj_s->pending_slave_rx_maxter_tx) {
  865. retValue = WriteAddressed;
  866. }
  867. if (obj_s->pending_slave_tx_master_rx) {
  868. retValue = ReadAddressed;
  869. }
  870. return (retValue);
  871. }
  872. int i2c_slave_read(i2c_t *obj, char *data, int length)
  873. {
  874. struct i2c_s *obj_s = I2C_S(obj);
  875. I2C_HandleTypeDef *handle = &(obj_s->handle);
  876. int count = 0;
  877. int ret = 0;
  878. uint32_t timeout = 0;
  879. /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
  880. ret = HAL_I2C_Slave_Sequential_Receive_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
  881. if (ret == HAL_OK) {
  882. timeout = BYTE_TIMEOUT_US * (length + 1);
  883. while (obj_s->pending_slave_rx_maxter_tx && (--timeout != 0)) {
  884. wait_us(1);
  885. }
  886. if (timeout != 0) {
  887. count = length;
  888. } else {
  889. DEBUG_PRINTF("TIMEOUT or error in i2c_slave_read\r\n");
  890. }
  891. }
  892. return count;
  893. }
  894. int i2c_slave_write(i2c_t *obj, const char *data, int length)
  895. {
  896. struct i2c_s *obj_s = I2C_S(obj);
  897. I2C_HandleTypeDef *handle = &(obj_s->handle);
  898. int count = 0;
  899. int ret = 0;
  900. uint32_t timeout = 0;
  901. /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
  902. ret = HAL_I2C_Slave_Sequential_Transmit_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
  903. if (ret == HAL_OK) {
  904. timeout = BYTE_TIMEOUT_US * (length + 1);
  905. while (obj_s->pending_slave_tx_master_rx && (--timeout != 0)) {
  906. wait_us(1);
  907. }
  908. if (timeout != 0) {
  909. count = length;
  910. } else {
  911. DEBUG_PRINTF("TIMEOUT or error in i2c_slave_write\r\n");
  912. }
  913. }
  914. return count;
  915. }
  916. #endif // DEVICE_I2CSLAVE
  917. #if DEVICE_I2C_ASYNCH
  918. /* ASYNCH MASTER API FUNCTIONS */
  919. void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
  920. {
  921. /* Get object ptr based on handler ptr */
  922. i2c_t *obj = get_i2c_obj(hi2c);
  923. struct i2c_s *obj_s = I2C_S(obj);
  924. I2C_HandleTypeDef *handle = &(obj_s->handle);
  925. /* Disable IT. Not always done before calling macro */
  926. __HAL_I2C_DISABLE_IT(handle, I2C_IT_ALL);
  927. i2c_ev_err_disable(obj);
  928. /* Set event flag */
  929. obj_s->event = I2C_EVENT_ERROR;
  930. }
  931. void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
  932. {
  933. // TODO: DMA usage is currently ignored by this way
  934. (void) hint;
  935. struct i2c_s *obj_s = I2C_S(obj);
  936. I2C_HandleTypeDef *handle = &(obj_s->handle);
  937. /* Update object */
  938. obj->tx_buff.buffer = (void *)tx;
  939. obj->tx_buff.length = tx_length;
  940. obj->tx_buff.pos = 0;
  941. obj->tx_buff.width = 8;
  942. obj->rx_buff.buffer = (void *)rx;
  943. obj->rx_buff.length = rx_length;
  944. obj->rx_buff.pos = SIZE_MAX;
  945. obj->rx_buff.width = 8;
  946. obj_s->available_events = event;
  947. obj_s->event = 0;
  948. obj_s->address = address;
  949. obj_s->stop = stop;
  950. i2c_ev_err_enable(obj, handler);
  951. /* Set operation step depending if stop sending required or not */
  952. if ((tx_length && !rx_length) || (!tx_length && rx_length)) {
  953. // Trick to remove compiler warning "left and right operands are identical" in some cases
  954. uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
  955. uint32_t op2 = I2C_LAST_FRAME;
  956. if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
  957. if (stop) {
  958. obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
  959. } else {
  960. obj_s->XferOperation = I2C_FIRST_FRAME;
  961. }
  962. } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
  963. (obj_s->XferOperation == I2C_NEXT_FRAME)) {
  964. if (stop) {
  965. obj_s->XferOperation = I2C_LAST_FRAME;
  966. } else {
  967. obj_s->XferOperation = I2C_NEXT_FRAME;
  968. }
  969. }
  970. if (tx_length > 0) {
  971. HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *)tx, tx_length, obj_s->XferOperation);
  972. }
  973. if (rx_length > 0) {
  974. HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t *)rx, rx_length, obj_s->XferOperation);
  975. }
  976. } else if (tx_length && rx_length) {
  977. /* Two steps operation, don't modify XferOperation, keep it for next step */
  978. // Trick to remove compiler warning "left and right operands are identical" in some cases
  979. uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
  980. uint32_t op2 = I2C_LAST_FRAME;
  981. if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
  982. HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *)tx, tx_length, I2C_FIRST_FRAME);
  983. } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
  984. (obj_s->XferOperation == I2C_NEXT_FRAME)) {
  985. HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *)tx, tx_length, I2C_NEXT_FRAME);
  986. }
  987. }
  988. }
  989. uint32_t i2c_irq_handler_asynch(i2c_t *obj)
  990. {
  991. struct i2c_s *obj_s = I2C_S(obj);
  992. I2C_HandleTypeDef *handle = &(obj_s->handle);
  993. HAL_I2C_EV_IRQHandler(handle);
  994. HAL_I2C_ER_IRQHandler(handle);
  995. /* Return I2C event status */
  996. return (obj_s->event & obj_s->available_events);
  997. }
  998. uint8_t i2c_active(i2c_t *obj)
  999. {
  1000. struct i2c_s *obj_s = I2C_S(obj);
  1001. I2C_HandleTypeDef *handle = &(obj_s->handle);
  1002. if (handle->State == HAL_I2C_STATE_READY) {
  1003. return 0;
  1004. } else {
  1005. return 1;
  1006. }
  1007. }
  1008. void i2c_abort_asynch(i2c_t *obj)
  1009. {
  1010. struct i2c_s *obj_s = I2C_S(obj);
  1011. I2C_HandleTypeDef *handle = &(obj_s->handle);
  1012. /* Abort HAL requires DevAddress, but is not used. Use Dummy */
  1013. uint16_t Dummy_DevAddress = 0x00;
  1014. HAL_I2C_Master_Abort_IT(handle, Dummy_DevAddress);
  1015. }
  1016. #endif // DEVICE_I2C_ASYNCH
  1017. #endif // DEVICE_I2C