stm32l432xx.h 1.1 MB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32l432xx.h
  4. * @author MCD Application Team
  5. * @brief CMSIS STM32L432xx Device Peripheral Access Layer Header File.
  6. *
  7. * This file contains:
  8. * - Data structures and the address mapping for all peripherals
  9. * - Peripheral's registers declarations and bits definition
  10. * - Macros to access peripheral’s registers hardware
  11. *
  12. ******************************************************************************
  13. * @attention
  14. *
  15. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  16. *
  17. * Redistribution and use in source and binary forms, with or without modification,
  18. * are permitted provided that the following conditions are met:
  19. * 1. Redistributions of source code must retain the above copyright notice,
  20. * this list of conditions and the following disclaimer.
  21. * 2. Redistributions in binary form must reproduce the above copyright notice,
  22. * this list of conditions and the following disclaimer in the documentation
  23. * and/or other materials provided with the distribution.
  24. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  25. * may be used to endorse or promote products derived from this software
  26. * without specific prior written permission.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  29. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  32. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  34. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. *
  39. ******************************************************************************
  40. */
  41. /** @addtogroup CMSIS_Device
  42. * @{
  43. */
  44. /** @addtogroup stm32l432xx
  45. * @{
  46. */
  47. #ifndef __STM32L432xx_H
  48. #define __STM32L432xx_H
  49. #ifdef __cplusplus
  50. extern "C" {
  51. #endif /* __cplusplus */
  52. /** @addtogroup Configuration_section_for_CMSIS
  53. * @{
  54. */
  55. /**
  56. * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
  57. */
  58. #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
  59. #define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
  60. #define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
  61. #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
  62. #define __FPU_PRESENT 0 /*!< FPU present */
  63. /**
  64. * @}
  65. */
  66. /** @addtogroup Peripheral_interrupt_number_definition
  67. * @{
  68. */
  69. /**
  70. * @brief STM32L4XX Interrupt Number Definition, according to the selected device
  71. * in @ref Library_configuration_section
  72. */
  73. typedef enum
  74. {
  75. /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
  76. NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
  77. HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
  78. MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
  79. BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
  80. UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
  81. SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
  82. DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
  83. PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
  84. SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
  85. /****** STM32 specific Interrupt Numbers **********************************************************************/
  86. WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
  87. PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
  88. TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
  89. RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
  90. FLASH_IRQn = 4, /*!< FLASH global Interrupt */
  91. RCC_IRQn = 5, /*!< RCC global Interrupt */
  92. EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
  93. EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
  94. EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
  95. EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
  96. EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
  97. DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
  98. DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
  99. DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
  100. DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
  101. DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
  102. DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
  103. DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
  104. ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
  105. CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
  106. CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
  107. CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
  108. CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
  109. EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
  110. TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
  111. TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
  112. TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
  113. TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
  114. TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
  115. I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
  116. I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
  117. SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
  118. USART1_IRQn = 37, /*!< USART1 global Interrupt */
  119. USART2_IRQn = 38, /*!< USART2 global Interrupt */
  120. EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
  121. RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
  122. SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
  123. TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
  124. TIM7_IRQn = 55, /*!< TIM7 global interrupt */
  125. DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
  126. DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
  127. DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
  128. DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
  129. DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
  130. COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
  131. LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
  132. LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
  133. USB_IRQn = 67, /*!< USB event Interrupt */
  134. DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
  135. DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
  136. LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
  137. QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
  138. I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
  139. I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
  140. SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
  141. SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */
  142. TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
  143. RNG_IRQn = 80, /*!< RNG global interrupt */
  144. FPU_IRQn = 81, /*!< FPU global interrupt */
  145. CRS_IRQn = 82 /*!< CRS global interrupt */
  146. } IRQn_Type;
  147. /**
  148. * @}
  149. */
  150. #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
  151. #include "system_stm32l4xx.h"
  152. #include <stdint.h>
  153. /** @addtogroup Peripheral_registers_structures
  154. * @{
  155. */
  156. /**
  157. * @brief Analog to Digital Converter
  158. */
  159. typedef struct
  160. {
  161. __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
  162. __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
  163. __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
  164. __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
  165. __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
  166. __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
  167. __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
  168. uint32_t RESERVED1; /*!< Reserved, 0x1C */
  169. __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
  170. __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
  171. __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
  172. uint32_t RESERVED2; /*!< Reserved, 0x2C */
  173. __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
  174. __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
  175. __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
  176. __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
  177. __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
  178. uint32_t RESERVED3; /*!< Reserved, 0x44 */
  179. uint32_t RESERVED4; /*!< Reserved, 0x48 */
  180. __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
  181. uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
  182. __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
  183. __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
  184. __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
  185. __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
  186. uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
  187. __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
  188. __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
  189. __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
  190. __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
  191. uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
  192. __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
  193. __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
  194. uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
  195. uint32_t RESERVED9; /*!< Reserved, 0x0AC */
  196. __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
  197. __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
  198. } ADC_TypeDef;
  199. typedef struct
  200. {
  201. uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */
  202. uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
  203. __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
  204. uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */
  205. } ADC_Common_TypeDef;
  206. /**
  207. * @brief Controller Area Network TxMailBox
  208. */
  209. typedef struct
  210. {
  211. __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
  212. __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
  213. __IO uint32_t TDLR; /*!< CAN mailbox data low register */
  214. __IO uint32_t TDHR; /*!< CAN mailbox data high register */
  215. } CAN_TxMailBox_TypeDef;
  216. /**
  217. * @brief Controller Area Network FIFOMailBox
  218. */
  219. typedef struct
  220. {
  221. __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
  222. __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
  223. __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
  224. __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
  225. } CAN_FIFOMailBox_TypeDef;
  226. /**
  227. * @brief Controller Area Network FilterRegister
  228. */
  229. typedef struct
  230. {
  231. __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
  232. __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
  233. } CAN_FilterRegister_TypeDef;
  234. /**
  235. * @brief Controller Area Network
  236. */
  237. typedef struct
  238. {
  239. __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
  240. __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
  241. __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
  242. __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
  243. __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
  244. __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
  245. __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
  246. __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
  247. uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
  248. CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
  249. CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
  250. uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
  251. __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
  252. __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
  253. uint32_t RESERVED2; /*!< Reserved, 0x208 */
  254. __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
  255. uint32_t RESERVED3; /*!< Reserved, 0x210 */
  256. __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
  257. uint32_t RESERVED4; /*!< Reserved, 0x218 */
  258. __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
  259. uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
  260. CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
  261. } CAN_TypeDef;
  262. /**
  263. * @brief Comparator
  264. */
  265. typedef struct
  266. {
  267. __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
  268. } COMP_TypeDef;
  269. typedef struct
  270. {
  271. __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
  272. } COMP_Common_TypeDef;
  273. /**
  274. * @brief CRC calculation unit
  275. */
  276. typedef struct
  277. {
  278. __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
  279. __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
  280. uint8_t RESERVED0; /*!< Reserved, 0x05 */
  281. uint16_t RESERVED1; /*!< Reserved, 0x06 */
  282. __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
  283. uint32_t RESERVED2; /*!< Reserved, 0x0C */
  284. __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
  285. __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
  286. } CRC_TypeDef;
  287. /**
  288. * @brief Clock Recovery System
  289. */
  290. typedef struct
  291. {
  292. __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
  293. __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
  294. __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
  295. __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
  296. } CRS_TypeDef;
  297. /**
  298. * @brief Digital to Analog Converter
  299. */
  300. typedef struct
  301. {
  302. __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
  303. __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
  304. __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
  305. __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
  306. __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
  307. __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
  308. __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
  309. __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
  310. __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
  311. __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
  312. __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
  313. __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
  314. __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
  315. __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
  316. __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
  317. __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
  318. __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
  319. __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
  320. __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
  321. __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
  322. } DAC_TypeDef;
  323. /**
  324. * @brief Debug MCU
  325. */
  326. typedef struct
  327. {
  328. __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
  329. __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
  330. __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
  331. __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
  332. __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
  333. } DBGMCU_TypeDef;
  334. /**
  335. * @brief DMA Controller
  336. */
  337. typedef struct
  338. {
  339. __IO uint32_t CCR; /*!< DMA channel x configuration register */
  340. __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
  341. __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
  342. __IO uint32_t CMAR; /*!< DMA channel x memory address register */
  343. } DMA_Channel_TypeDef;
  344. typedef struct
  345. {
  346. __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
  347. __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
  348. } DMA_TypeDef;
  349. typedef struct
  350. {
  351. __IO uint32_t CSELR; /*!< DMA channel selection register */
  352. } DMA_Request_TypeDef;
  353. /* Legacy define */
  354. #define DMA_request_TypeDef DMA_Request_TypeDef
  355. /**
  356. * @brief External Interrupt/Event Controller
  357. */
  358. typedef struct
  359. {
  360. __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
  361. __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
  362. __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
  363. __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
  364. __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
  365. __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
  366. uint32_t RESERVED1; /*!< Reserved, 0x18 */
  367. uint32_t RESERVED2; /*!< Reserved, 0x1C */
  368. __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
  369. __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
  370. __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
  371. __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
  372. __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
  373. __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
  374. } EXTI_TypeDef;
  375. /**
  376. * @brief Firewall
  377. */
  378. typedef struct
  379. {
  380. __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
  381. __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
  382. __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
  383. __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
  384. __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
  385. __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
  386. uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
  387. uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
  388. __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
  389. } FIREWALL_TypeDef;
  390. /**
  391. * @brief FLASH Registers
  392. */
  393. typedef struct
  394. {
  395. __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
  396. __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
  397. __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
  398. __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
  399. __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
  400. __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
  401. __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
  402. __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
  403. __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
  404. __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
  405. __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
  406. __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
  407. __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
  408. } FLASH_TypeDef;
  409. /**
  410. * @brief General Purpose I/O
  411. */
  412. typedef struct
  413. {
  414. __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
  415. __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
  416. __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
  417. __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
  418. __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
  419. __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
  420. __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
  421. __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
  422. __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
  423. __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
  424. } GPIO_TypeDef;
  425. /**
  426. * @brief Inter-integrated Circuit Interface
  427. */
  428. typedef struct
  429. {
  430. __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
  431. __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
  432. __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
  433. __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
  434. __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
  435. __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
  436. __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
  437. __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
  438. __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
  439. __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
  440. __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
  441. } I2C_TypeDef;
  442. /**
  443. * @brief Independent WATCHDOG
  444. */
  445. typedef struct
  446. {
  447. __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
  448. __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
  449. __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
  450. __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
  451. __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
  452. } IWDG_TypeDef;
  453. /**
  454. * @brief LPTIMER
  455. */
  456. typedef struct
  457. {
  458. __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
  459. __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
  460. __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
  461. __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
  462. __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
  463. __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
  464. __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
  465. __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
  466. __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
  467. } LPTIM_TypeDef;
  468. /**
  469. * @brief Operational Amplifier (OPAMP)
  470. */
  471. typedef struct
  472. {
  473. __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
  474. __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
  475. __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
  476. } OPAMP_TypeDef;
  477. typedef struct
  478. {
  479. __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
  480. } OPAMP_Common_TypeDef;
  481. /**
  482. * @brief Power Control
  483. */
  484. typedef struct
  485. {
  486. __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
  487. __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
  488. __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
  489. __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
  490. __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
  491. __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
  492. __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
  493. uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
  494. __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
  495. __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
  496. __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
  497. __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
  498. __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
  499. __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
  500. __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
  501. __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
  502. __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
  503. __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
  504. uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */
  505. uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */
  506. uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */
  507. uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */
  508. __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
  509. __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
  510. } PWR_TypeDef;
  511. /**
  512. * @brief QUAD Serial Peripheral Interface
  513. */
  514. typedef struct
  515. {
  516. __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
  517. __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
  518. __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
  519. __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
  520. __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
  521. __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
  522. __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
  523. __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
  524. __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
  525. __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
  526. __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
  527. __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
  528. __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
  529. } QUADSPI_TypeDef;
  530. /**
  531. * @brief Reset and Clock Control
  532. */
  533. typedef struct
  534. {
  535. __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
  536. __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
  537. __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
  538. __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
  539. __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
  540. uint32_t RESERVED; /*!< Reserved, Address offset: 0x14 */
  541. __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
  542. __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
  543. __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
  544. uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
  545. __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
  546. __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
  547. __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
  548. uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
  549. __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
  550. __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
  551. __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
  552. uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
  553. __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
  554. __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
  555. __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
  556. uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
  557. __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
  558. __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
  559. __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
  560. uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
  561. __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
  562. __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
  563. __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
  564. uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
  565. __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
  566. __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
  567. __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
  568. uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
  569. __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
  570. uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
  571. __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
  572. __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
  573. __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
  574. } RCC_TypeDef;
  575. /**
  576. * @brief Real-Time Clock
  577. */
  578. typedef struct
  579. {
  580. __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
  581. __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
  582. __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
  583. __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
  584. __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
  585. __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
  586. uint32_t reserved; /*!< Reserved */
  587. __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
  588. __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
  589. __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
  590. __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
  591. __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
  592. __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
  593. __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
  594. __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
  595. __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
  596. __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
  597. __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
  598. __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
  599. __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
  600. __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
  601. __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
  602. __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
  603. __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
  604. __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
  605. __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
  606. __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
  607. __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
  608. __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
  609. __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
  610. __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
  611. __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
  612. __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
  613. __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
  614. __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
  615. __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
  616. __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
  617. __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
  618. __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
  619. __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
  620. __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
  621. __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
  622. __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
  623. __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
  624. __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
  625. __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
  626. __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
  627. __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
  628. __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
  629. __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
  630. __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
  631. __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
  632. } RTC_TypeDef;
  633. /**
  634. * @brief Serial Audio Interface
  635. */
  636. typedef struct
  637. {
  638. __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
  639. } SAI_TypeDef;
  640. typedef struct
  641. {
  642. __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
  643. __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
  644. __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
  645. __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
  646. __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
  647. __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
  648. __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
  649. __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
  650. } SAI_Block_TypeDef;
  651. /**
  652. * @brief Serial Peripheral Interface
  653. */
  654. typedef struct
  655. {
  656. __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
  657. __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
  658. __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
  659. __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
  660. __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
  661. __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
  662. __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
  663. } SPI_TypeDef;
  664. /**
  665. * @brief Single Wire Protocol Master Interface SPWMI
  666. */
  667. typedef struct
  668. {
  669. __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
  670. __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
  671. uint32_t RESERVED1; /*!< Reserved, 0x08 */
  672. __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
  673. __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
  674. __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
  675. __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
  676. __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
  677. __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
  678. __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
  679. } SWPMI_TypeDef;
  680. /**
  681. * @brief System configuration controller
  682. */
  683. typedef struct
  684. {
  685. __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
  686. __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
  687. __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
  688. __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
  689. __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
  690. __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
  691. __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
  692. } SYSCFG_TypeDef;
  693. /**
  694. * @brief TIM
  695. */
  696. typedef struct
  697. {
  698. __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
  699. __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
  700. __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
  701. __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
  702. __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
  703. __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
  704. __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
  705. __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
  706. __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
  707. __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
  708. __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
  709. __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
  710. __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
  711. __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
  712. __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
  713. __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
  714. __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
  715. __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
  716. __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
  717. __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
  718. __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
  719. __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
  720. __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
  721. __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
  722. __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
  723. __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
  724. } TIM_TypeDef;
  725. /**
  726. * @brief Touch Sensing Controller (TSC)
  727. */
  728. typedef struct
  729. {
  730. __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
  731. __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
  732. __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
  733. __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
  734. __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
  735. uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
  736. __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
  737. uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
  738. __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
  739. uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
  740. __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
  741. uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
  742. __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
  743. __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */
  744. } TSC_TypeDef;
  745. /**
  746. * @brief Universal Synchronous Asynchronous Receiver Transmitter
  747. */
  748. typedef struct
  749. {
  750. __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
  751. __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
  752. __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
  753. __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
  754. __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
  755. uint16_t RESERVED2; /*!< Reserved, 0x12 */
  756. __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
  757. __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
  758. uint16_t RESERVED3; /*!< Reserved, 0x1A */
  759. __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
  760. __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
  761. __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
  762. uint16_t RESERVED4; /*!< Reserved, 0x26 */
  763. __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
  764. uint16_t RESERVED5; /*!< Reserved, 0x2A */
  765. } USART_TypeDef;
  766. /**
  767. * @brief Universal Serial Bus Full Speed Device
  768. */
  769. typedef struct
  770. {
  771. __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
  772. __IO uint16_t RESERVED0; /*!< Reserved */
  773. __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
  774. __IO uint16_t RESERVED1; /*!< Reserved */
  775. __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
  776. __IO uint16_t RESERVED2; /*!< Reserved */
  777. __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
  778. __IO uint16_t RESERVED3; /*!< Reserved */
  779. __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
  780. __IO uint16_t RESERVED4; /*!< Reserved */
  781. __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
  782. __IO uint16_t RESERVED5; /*!< Reserved */
  783. __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
  784. __IO uint16_t RESERVED6; /*!< Reserved */
  785. __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
  786. __IO uint16_t RESERVED7[17]; /*!< Reserved */
  787. __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
  788. __IO uint16_t RESERVED8; /*!< Reserved */
  789. __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
  790. __IO uint16_t RESERVED9; /*!< Reserved */
  791. __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
  792. __IO uint16_t RESERVEDA; /*!< Reserved */
  793. __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
  794. __IO uint16_t RESERVEDB; /*!< Reserved */
  795. __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
  796. __IO uint16_t RESERVEDC; /*!< Reserved */
  797. __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
  798. __IO uint16_t RESERVEDD; /*!< Reserved */
  799. __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
  800. __IO uint16_t RESERVEDE; /*!< Reserved */
  801. } USB_TypeDef;
  802. /**
  803. * @brief Window WATCHDOG
  804. */
  805. typedef struct
  806. {
  807. __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
  808. __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
  809. __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
  810. } WWDG_TypeDef;
  811. /**
  812. * @brief RNG
  813. */
  814. typedef struct
  815. {
  816. __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
  817. __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
  818. __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
  819. } RNG_TypeDef;
  820. /**
  821. * @}
  822. */
  823. /** @addtogroup Peripheral_memory_map
  824. * @{
  825. */
  826. #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */
  827. #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */
  828. #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */
  829. #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
  830. #define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */
  831. #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
  832. #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
  833. #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
  834. /* Legacy defines */
  835. #define SRAM_BASE SRAM1_BASE
  836. #define SRAM_BB_BASE SRAM1_BB_BASE
  837. #define SRAM1_SIZE_MAX ((uint32_t)0x0000C000U) /*!< maximum SRAM1 size (up to 48 KBytes) */
  838. #define SRAM2_SIZE ((uint32_t)0x00004000U) /*!< SRAM2 size (16 KBytes) */
  839. /*!< Peripheral memory map */
  840. #define APB1PERIPH_BASE PERIPH_BASE
  841. #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
  842. #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
  843. #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
  844. /*!< APB1 peripherals */
  845. #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
  846. #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
  847. #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
  848. #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
  849. #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
  850. #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
  851. #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
  852. #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
  853. #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
  854. #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
  855. #define CRS_BASE (APB1PERIPH_BASE + 0x6000U)
  856. #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
  857. #define USB_BASE (APB1PERIPH_BASE + 0x6800U) /*!< USB_IP Peripheral Registers base address */
  858. #define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00U) /*!< USB_IP Packet Memory Area base address */
  859. #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
  860. #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
  861. #define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
  862. #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
  863. #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
  864. #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
  865. #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
  866. #define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U)
  867. #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
  868. /*!< APB2 peripherals */
  869. #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
  870. #define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
  871. #define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
  872. #define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
  873. #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
  874. #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
  875. #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
  876. #define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
  877. #define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
  878. #define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
  879. #define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
  880. #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
  881. #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
  882. /*!< AHB1 peripherals */
  883. #define DMA1_BASE (AHB1PERIPH_BASE)
  884. #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
  885. #define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
  886. #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
  887. #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
  888. #define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
  889. #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
  890. #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
  891. #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
  892. #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
  893. #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
  894. #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
  895. #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
  896. #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U)
  897. #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
  898. #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
  899. #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
  900. #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
  901. #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
  902. #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
  903. #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
  904. #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U)
  905. /*!< AHB2 peripherals */
  906. #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
  907. #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
  908. #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
  909. #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
  910. #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
  911. #define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
  912. #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
  913. /* Debug MCU registers base address */
  914. #define DBGMCU_BASE ((uint32_t)0xE0042000U)
  915. #define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
  916. #define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
  917. #define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
  918. /**
  919. * @}
  920. */
  921. /** @addtogroup Peripheral_declaration
  922. * @{
  923. */
  924. #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
  925. #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
  926. #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
  927. #define RTC ((RTC_TypeDef *) RTC_BASE)
  928. #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
  929. #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
  930. #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
  931. #define USART2 ((USART_TypeDef *) USART2_BASE)
  932. #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
  933. #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
  934. #define CRS ((CRS_TypeDef *) CRS_BASE)
  935. #define CAN ((CAN_TypeDef *) CAN1_BASE)
  936. #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
  937. #define USB ((USB_TypeDef *) USB_BASE)
  938. #define PWR ((PWR_TypeDef *) PWR_BASE)
  939. #define DAC ((DAC_TypeDef *) DAC1_BASE)
  940. #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
  941. #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
  942. #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
  943. #define OPAMP1_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
  944. #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
  945. #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
  946. #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
  947. #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
  948. #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
  949. #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
  950. #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
  951. #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
  952. #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
  953. #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
  954. #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
  955. #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
  956. #define USART1 ((USART_TypeDef *) USART1_BASE)
  957. #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
  958. #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
  959. #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
  960. #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
  961. #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
  962. #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
  963. #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
  964. #define RCC ((RCC_TypeDef *) RCC_BASE)
  965. #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
  966. #define CRC ((CRC_TypeDef *) CRC_BASE)
  967. #define TSC ((TSC_TypeDef *) TSC_BASE)
  968. #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
  969. #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
  970. #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
  971. #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
  972. #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
  973. #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
  974. #define RNG ((RNG_TypeDef *) RNG_BASE)
  975. #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
  976. #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
  977. #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
  978. #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
  979. #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
  980. #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
  981. #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
  982. #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
  983. #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
  984. #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
  985. #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
  986. #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
  987. #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
  988. #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
  989. #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
  990. #define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
  991. #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
  992. #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
  993. /**
  994. * @}
  995. */
  996. /** @addtogroup Exported_constants
  997. * @{
  998. */
  999. /** @addtogroup Peripheral_Registers_Bits_Definition
  1000. * @{
  1001. */
  1002. /******************************************************************************/
  1003. /* Peripheral Registers_Bits_Definition */
  1004. /******************************************************************************/
  1005. /******************************************************************************/
  1006. /* */
  1007. /* Analog to Digital Converter */
  1008. /* */
  1009. /******************************************************************************/
  1010. /*
  1011. * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
  1012. */
  1013. /* Note: No specific macro feature on this device */
  1014. /******************** Bit definition for ADC_ISR register *******************/
  1015. #define ADC_ISR_ADRDY_Pos (0U)
  1016. #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
  1017. #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
  1018. #define ADC_ISR_EOSMP_Pos (1U)
  1019. #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
  1020. #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
  1021. #define ADC_ISR_EOC_Pos (2U)
  1022. #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
  1023. #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
  1024. #define ADC_ISR_EOS_Pos (3U)
  1025. #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
  1026. #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
  1027. #define ADC_ISR_OVR_Pos (4U)
  1028. #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
  1029. #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
  1030. #define ADC_ISR_JEOC_Pos (5U)
  1031. #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
  1032. #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
  1033. #define ADC_ISR_JEOS_Pos (6U)
  1034. #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
  1035. #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
  1036. #define ADC_ISR_AWD1_Pos (7U)
  1037. #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
  1038. #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
  1039. #define ADC_ISR_AWD2_Pos (8U)
  1040. #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
  1041. #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
  1042. #define ADC_ISR_AWD3_Pos (9U)
  1043. #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
  1044. #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
  1045. #define ADC_ISR_JQOVF_Pos (10U)
  1046. #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
  1047. #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
  1048. /******************** Bit definition for ADC_IER register *******************/
  1049. #define ADC_IER_ADRDYIE_Pos (0U)
  1050. #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
  1051. #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
  1052. #define ADC_IER_EOSMPIE_Pos (1U)
  1053. #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
  1054. #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
  1055. #define ADC_IER_EOCIE_Pos (2U)
  1056. #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
  1057. #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
  1058. #define ADC_IER_EOSIE_Pos (3U)
  1059. #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
  1060. #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
  1061. #define ADC_IER_OVRIE_Pos (4U)
  1062. #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
  1063. #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
  1064. #define ADC_IER_JEOCIE_Pos (5U)
  1065. #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
  1066. #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
  1067. #define ADC_IER_JEOSIE_Pos (6U)
  1068. #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
  1069. #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
  1070. #define ADC_IER_AWD1IE_Pos (7U)
  1071. #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
  1072. #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
  1073. #define ADC_IER_AWD2IE_Pos (8U)
  1074. #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
  1075. #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
  1076. #define ADC_IER_AWD3IE_Pos (9U)
  1077. #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
  1078. #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
  1079. #define ADC_IER_JQOVFIE_Pos (10U)
  1080. #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
  1081. #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
  1082. /* Legacy defines */
  1083. #define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
  1084. #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
  1085. #define ADC_IER_EOC (ADC_IER_EOCIE)
  1086. #define ADC_IER_EOS (ADC_IER_EOSIE)
  1087. #define ADC_IER_OVR (ADC_IER_OVRIE)
  1088. #define ADC_IER_JEOC (ADC_IER_JEOCIE)
  1089. #define ADC_IER_JEOS (ADC_IER_JEOSIE)
  1090. #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
  1091. #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
  1092. #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
  1093. #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
  1094. /******************** Bit definition for ADC_CR register ********************/
  1095. #define ADC_CR_ADEN_Pos (0U)
  1096. #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
  1097. #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
  1098. #define ADC_CR_ADDIS_Pos (1U)
  1099. #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
  1100. #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
  1101. #define ADC_CR_ADSTART_Pos (2U)
  1102. #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
  1103. #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
  1104. #define ADC_CR_JADSTART_Pos (3U)
  1105. #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
  1106. #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
  1107. #define ADC_CR_ADSTP_Pos (4U)
  1108. #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
  1109. #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
  1110. #define ADC_CR_JADSTP_Pos (5U)
  1111. #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
  1112. #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
  1113. #define ADC_CR_ADVREGEN_Pos (28U)
  1114. #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
  1115. #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
  1116. #define ADC_CR_DEEPPWD_Pos (29U)
  1117. #define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
  1118. #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
  1119. #define ADC_CR_ADCALDIF_Pos (30U)
  1120. #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
  1121. #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
  1122. #define ADC_CR_ADCAL_Pos (31U)
  1123. #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
  1124. #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
  1125. /******************** Bit definition for ADC_CFGR register ******************/
  1126. #define ADC_CFGR_DMAEN_Pos (0U)
  1127. #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
  1128. #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
  1129. #define ADC_CFGR_DMACFG_Pos (1U)
  1130. #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
  1131. #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
  1132. #define ADC_CFGR_RES_Pos (3U)
  1133. #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
  1134. #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
  1135. #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
  1136. #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
  1137. #define ADC_CFGR_ALIGN_Pos (5U)
  1138. #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
  1139. #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
  1140. #define ADC_CFGR_EXTSEL_Pos (6U)
  1141. #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
  1142. #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
  1143. #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
  1144. #define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
  1145. #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
  1146. #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
  1147. #define ADC_CFGR_EXTEN_Pos (10U)
  1148. #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
  1149. #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
  1150. #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
  1151. #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
  1152. #define ADC_CFGR_OVRMOD_Pos (12U)
  1153. #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
  1154. #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
  1155. #define ADC_CFGR_CONT_Pos (13U)
  1156. #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
  1157. #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
  1158. #define ADC_CFGR_AUTDLY_Pos (14U)
  1159. #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
  1160. #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
  1161. #define ADC_CFGR_DISCEN_Pos (16U)
  1162. #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
  1163. #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
  1164. #define ADC_CFGR_DISCNUM_Pos (17U)
  1165. #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
  1166. #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
  1167. #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
  1168. #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
  1169. #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
  1170. #define ADC_CFGR_JDISCEN_Pos (20U)
  1171. #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
  1172. #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
  1173. #define ADC_CFGR_JQM_Pos (21U)
  1174. #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
  1175. #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
  1176. #define ADC_CFGR_AWD1SGL_Pos (22U)
  1177. #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
  1178. #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
  1179. #define ADC_CFGR_AWD1EN_Pos (23U)
  1180. #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
  1181. #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
  1182. #define ADC_CFGR_JAWD1EN_Pos (24U)
  1183. #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
  1184. #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
  1185. #define ADC_CFGR_JAUTO_Pos (25U)
  1186. #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
  1187. #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
  1188. #define ADC_CFGR_AWD1CH_Pos (26U)
  1189. #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
  1190. #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
  1191. #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
  1192. #define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
  1193. #define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
  1194. #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
  1195. #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
  1196. #define ADC_CFGR_JQDIS_Pos (31U)
  1197. #define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
  1198. #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
  1199. /******************** Bit definition for ADC_CFGR2 register *****************/
  1200. #define ADC_CFGR2_ROVSE_Pos (0U)
  1201. #define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
  1202. #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
  1203. #define ADC_CFGR2_JOVSE_Pos (1U)
  1204. #define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
  1205. #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
  1206. #define ADC_CFGR2_OVSR_Pos (2U)
  1207. #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
  1208. #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
  1209. #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
  1210. #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
  1211. #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
  1212. #define ADC_CFGR2_OVSS_Pos (5U)
  1213. #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
  1214. #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
  1215. #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
  1216. #define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
  1217. #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
  1218. #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
  1219. #define ADC_CFGR2_TROVS_Pos (9U)
  1220. #define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
  1221. #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
  1222. #define ADC_CFGR2_ROVSM_Pos (10U)
  1223. #define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
  1224. #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
  1225. /******************** Bit definition for ADC_SMPR1 register *****************/
  1226. #define ADC_SMPR1_SMP0_Pos (0U)
  1227. #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
  1228. #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
  1229. #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
  1230. #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
  1231. #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
  1232. #define ADC_SMPR1_SMP1_Pos (3U)
  1233. #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
  1234. #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
  1235. #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
  1236. #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
  1237. #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
  1238. #define ADC_SMPR1_SMP2_Pos (6U)
  1239. #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
  1240. #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
  1241. #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
  1242. #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
  1243. #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
  1244. #define ADC_SMPR1_SMP3_Pos (9U)
  1245. #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
  1246. #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
  1247. #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
  1248. #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
  1249. #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
  1250. #define ADC_SMPR1_SMP4_Pos (12U)
  1251. #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
  1252. #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
  1253. #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
  1254. #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
  1255. #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
  1256. #define ADC_SMPR1_SMP5_Pos (15U)
  1257. #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
  1258. #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
  1259. #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
  1260. #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
  1261. #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
  1262. #define ADC_SMPR1_SMP6_Pos (18U)
  1263. #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
  1264. #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
  1265. #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
  1266. #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
  1267. #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
  1268. #define ADC_SMPR1_SMP7_Pos (21U)
  1269. #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
  1270. #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
  1271. #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
  1272. #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
  1273. #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
  1274. #define ADC_SMPR1_SMP8_Pos (24U)
  1275. #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
  1276. #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
  1277. #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
  1278. #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
  1279. #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
  1280. #define ADC_SMPR1_SMP9_Pos (27U)
  1281. #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
  1282. #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
  1283. #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
  1284. #define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
  1285. #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
  1286. /******************** Bit definition for ADC_SMPR2 register *****************/
  1287. #define ADC_SMPR2_SMP10_Pos (0U)
  1288. #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
  1289. #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
  1290. #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
  1291. #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
  1292. #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
  1293. #define ADC_SMPR2_SMP11_Pos (3U)
  1294. #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
  1295. #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
  1296. #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
  1297. #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
  1298. #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
  1299. #define ADC_SMPR2_SMP12_Pos (6U)
  1300. #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
  1301. #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
  1302. #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
  1303. #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
  1304. #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
  1305. #define ADC_SMPR2_SMP13_Pos (9U)
  1306. #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
  1307. #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
  1308. #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
  1309. #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
  1310. #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
  1311. #define ADC_SMPR2_SMP14_Pos (12U)
  1312. #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
  1313. #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
  1314. #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
  1315. #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
  1316. #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
  1317. #define ADC_SMPR2_SMP15_Pos (15U)
  1318. #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
  1319. #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
  1320. #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
  1321. #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
  1322. #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
  1323. #define ADC_SMPR2_SMP16_Pos (18U)
  1324. #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
  1325. #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
  1326. #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
  1327. #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
  1328. #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
  1329. #define ADC_SMPR2_SMP17_Pos (21U)
  1330. #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
  1331. #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
  1332. #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
  1333. #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
  1334. #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
  1335. #define ADC_SMPR2_SMP18_Pos (24U)
  1336. #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
  1337. #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
  1338. #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
  1339. #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
  1340. #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
  1341. /******************** Bit definition for ADC_TR1 register *******************/
  1342. #define ADC_TR1_LT1_Pos (0U)
  1343. #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
  1344. #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
  1345. #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
  1346. #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
  1347. #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
  1348. #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
  1349. #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
  1350. #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
  1351. #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
  1352. #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
  1353. #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
  1354. #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
  1355. #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
  1356. #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
  1357. #define ADC_TR1_HT1_Pos (16U)
  1358. #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
  1359. #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
  1360. #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
  1361. #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
  1362. #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
  1363. #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
  1364. #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
  1365. #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
  1366. #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
  1367. #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
  1368. #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
  1369. #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
  1370. #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
  1371. #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
  1372. /******************** Bit definition for ADC_TR2 register *******************/
  1373. #define ADC_TR2_LT2_Pos (0U)
  1374. #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
  1375. #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
  1376. #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
  1377. #define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
  1378. #define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
  1379. #define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
  1380. #define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
  1381. #define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
  1382. #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
  1383. #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
  1384. #define ADC_TR2_HT2_Pos (16U)
  1385. #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
  1386. #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
  1387. #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
  1388. #define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
  1389. #define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
  1390. #define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
  1391. #define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
  1392. #define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
  1393. #define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
  1394. #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
  1395. /******************** Bit definition for ADC_TR3 register *******************/
  1396. #define ADC_TR3_LT3_Pos (0U)
  1397. #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
  1398. #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
  1399. #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
  1400. #define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
  1401. #define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
  1402. #define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
  1403. #define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
  1404. #define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
  1405. #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
  1406. #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
  1407. #define ADC_TR3_HT3_Pos (16U)
  1408. #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
  1409. #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
  1410. #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
  1411. #define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
  1412. #define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
  1413. #define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
  1414. #define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
  1415. #define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
  1416. #define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
  1417. #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
  1418. /******************** Bit definition for ADC_SQR1 register ******************/
  1419. #define ADC_SQR1_L_Pos (0U)
  1420. #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
  1421. #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
  1422. #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
  1423. #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
  1424. #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
  1425. #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
  1426. #define ADC_SQR1_SQ1_Pos (6U)
  1427. #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
  1428. #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
  1429. #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
  1430. #define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
  1431. #define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
  1432. #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
  1433. #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
  1434. #define ADC_SQR1_SQ2_Pos (12U)
  1435. #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
  1436. #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
  1437. #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
  1438. #define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
  1439. #define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
  1440. #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
  1441. #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
  1442. #define ADC_SQR1_SQ3_Pos (18U)
  1443. #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
  1444. #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
  1445. #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
  1446. #define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
  1447. #define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
  1448. #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
  1449. #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
  1450. #define ADC_SQR1_SQ4_Pos (24U)
  1451. #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
  1452. #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
  1453. #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
  1454. #define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
  1455. #define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
  1456. #define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
  1457. #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
  1458. /******************** Bit definition for ADC_SQR2 register ******************/
  1459. #define ADC_SQR2_SQ5_Pos (0U)
  1460. #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
  1461. #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
  1462. #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
  1463. #define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
  1464. #define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
  1465. #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
  1466. #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
  1467. #define ADC_SQR2_SQ6_Pos (6U)
  1468. #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
  1469. #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
  1470. #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
  1471. #define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
  1472. #define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
  1473. #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
  1474. #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
  1475. #define ADC_SQR2_SQ7_Pos (12U)
  1476. #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
  1477. #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
  1478. #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
  1479. #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
  1480. #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
  1481. #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
  1482. #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
  1483. #define ADC_SQR2_SQ8_Pos (18U)
  1484. #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
  1485. #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
  1486. #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
  1487. #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
  1488. #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
  1489. #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
  1490. #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
  1491. #define ADC_SQR2_SQ9_Pos (24U)
  1492. #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
  1493. #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
  1494. #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
  1495. #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
  1496. #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
  1497. #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
  1498. #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
  1499. /******************** Bit definition for ADC_SQR3 register ******************/
  1500. #define ADC_SQR3_SQ10_Pos (0U)
  1501. #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
  1502. #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
  1503. #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
  1504. #define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
  1505. #define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
  1506. #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
  1507. #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
  1508. #define ADC_SQR3_SQ11_Pos (6U)
  1509. #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
  1510. #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
  1511. #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
  1512. #define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
  1513. #define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
  1514. #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
  1515. #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
  1516. #define ADC_SQR3_SQ12_Pos (12U)
  1517. #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
  1518. #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
  1519. #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
  1520. #define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
  1521. #define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
  1522. #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
  1523. #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
  1524. #define ADC_SQR3_SQ13_Pos (18U)
  1525. #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
  1526. #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
  1527. #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
  1528. #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
  1529. #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
  1530. #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
  1531. #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
  1532. #define ADC_SQR3_SQ14_Pos (24U)
  1533. #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
  1534. #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
  1535. #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
  1536. #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
  1537. #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
  1538. #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
  1539. #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
  1540. /******************** Bit definition for ADC_SQR4 register ******************/
  1541. #define ADC_SQR4_SQ15_Pos (0U)
  1542. #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
  1543. #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
  1544. #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
  1545. #define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
  1546. #define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
  1547. #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
  1548. #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
  1549. #define ADC_SQR4_SQ16_Pos (6U)
  1550. #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
  1551. #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
  1552. #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
  1553. #define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
  1554. #define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
  1555. #define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
  1556. #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
  1557. /******************** Bit definition for ADC_DR register ********************/
  1558. #define ADC_DR_RDATA_Pos (0U)
  1559. #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
  1560. #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
  1561. #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
  1562. #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
  1563. #define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
  1564. #define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
  1565. #define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
  1566. #define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
  1567. #define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
  1568. #define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
  1569. #define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
  1570. #define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
  1571. #define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
  1572. #define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
  1573. #define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
  1574. #define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
  1575. #define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
  1576. #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
  1577. /******************** Bit definition for ADC_JSQR register ******************/
  1578. #define ADC_JSQR_JL_Pos (0U)
  1579. #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
  1580. #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
  1581. #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
  1582. #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
  1583. #define ADC_JSQR_JEXTSEL_Pos (2U)
  1584. #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
  1585. #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
  1586. #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
  1587. #define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
  1588. #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
  1589. #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
  1590. #define ADC_JSQR_JEXTEN_Pos (6U)
  1591. #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
  1592. #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
  1593. #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
  1594. #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
  1595. #define ADC_JSQR_JSQ1_Pos (8U)
  1596. #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
  1597. #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
  1598. #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
  1599. #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
  1600. #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
  1601. #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
  1602. #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
  1603. #define ADC_JSQR_JSQ2_Pos (14U)
  1604. #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
  1605. #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
  1606. #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
  1607. #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
  1608. #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
  1609. #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
  1610. #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
  1611. #define ADC_JSQR_JSQ3_Pos (20U)
  1612. #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
  1613. #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
  1614. #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
  1615. #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
  1616. #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
  1617. #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
  1618. #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
  1619. #define ADC_JSQR_JSQ4_Pos (26U)
  1620. #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
  1621. #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
  1622. #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
  1623. #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
  1624. #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
  1625. #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
  1626. #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
  1627. /******************** Bit definition for ADC_OFR1 register ******************/
  1628. #define ADC_OFR1_OFFSET1_Pos (0U)
  1629. #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
  1630. #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
  1631. #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
  1632. #define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
  1633. #define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
  1634. #define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
  1635. #define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
  1636. #define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
  1637. #define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
  1638. #define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
  1639. #define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
  1640. #define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
  1641. #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
  1642. #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
  1643. #define ADC_OFR1_OFFSET1_CH_Pos (26U)
  1644. #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
  1645. #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
  1646. #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
  1647. #define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
  1648. #define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
  1649. #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
  1650. #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
  1651. #define ADC_OFR1_OFFSET1_EN_Pos (31U)
  1652. #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
  1653. #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
  1654. /******************** Bit definition for ADC_OFR2 register ******************/
  1655. #define ADC_OFR2_OFFSET2_Pos (0U)
  1656. #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
  1657. #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
  1658. #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
  1659. #define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
  1660. #define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
  1661. #define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
  1662. #define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
  1663. #define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
  1664. #define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
  1665. #define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
  1666. #define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
  1667. #define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
  1668. #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
  1669. #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
  1670. #define ADC_OFR2_OFFSET2_CH_Pos (26U)
  1671. #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
  1672. #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
  1673. #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
  1674. #define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
  1675. #define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
  1676. #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
  1677. #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
  1678. #define ADC_OFR2_OFFSET2_EN_Pos (31U)
  1679. #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
  1680. #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
  1681. /******************** Bit definition for ADC_OFR3 register ******************/
  1682. #define ADC_OFR3_OFFSET3_Pos (0U)
  1683. #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
  1684. #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
  1685. #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
  1686. #define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
  1687. #define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
  1688. #define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
  1689. #define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
  1690. #define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
  1691. #define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
  1692. #define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
  1693. #define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
  1694. #define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
  1695. #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
  1696. #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
  1697. #define ADC_OFR3_OFFSET3_CH_Pos (26U)
  1698. #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
  1699. #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
  1700. #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
  1701. #define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
  1702. #define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
  1703. #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
  1704. #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
  1705. #define ADC_OFR3_OFFSET3_EN_Pos (31U)
  1706. #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
  1707. #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
  1708. /******************** Bit definition for ADC_OFR4 register ******************/
  1709. #define ADC_OFR4_OFFSET4_Pos (0U)
  1710. #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
  1711. #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
  1712. #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
  1713. #define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
  1714. #define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
  1715. #define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
  1716. #define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
  1717. #define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
  1718. #define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
  1719. #define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
  1720. #define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
  1721. #define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
  1722. #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
  1723. #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
  1724. #define ADC_OFR4_OFFSET4_CH_Pos (26U)
  1725. #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
  1726. #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
  1727. #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
  1728. #define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
  1729. #define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
  1730. #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
  1731. #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
  1732. #define ADC_OFR4_OFFSET4_EN_Pos (31U)
  1733. #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
  1734. #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
  1735. /******************** Bit definition for ADC_JDR1 register ******************/
  1736. #define ADC_JDR1_JDATA_Pos (0U)
  1737. #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
  1738. #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
  1739. #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
  1740. #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
  1741. #define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
  1742. #define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
  1743. #define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
  1744. #define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
  1745. #define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
  1746. #define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
  1747. #define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
  1748. #define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
  1749. #define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
  1750. #define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
  1751. #define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
  1752. #define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
  1753. #define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
  1754. #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
  1755. /******************** Bit definition for ADC_JDR2 register ******************/
  1756. #define ADC_JDR2_JDATA_Pos (0U)
  1757. #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
  1758. #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
  1759. #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
  1760. #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
  1761. #define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
  1762. #define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
  1763. #define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
  1764. #define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
  1765. #define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
  1766. #define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
  1767. #define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
  1768. #define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
  1769. #define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
  1770. #define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
  1771. #define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
  1772. #define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
  1773. #define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
  1774. #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
  1775. /******************** Bit definition for ADC_JDR3 register ******************/
  1776. #define ADC_JDR3_JDATA_Pos (0U)
  1777. #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
  1778. #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
  1779. #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
  1780. #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
  1781. #define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
  1782. #define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
  1783. #define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
  1784. #define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
  1785. #define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
  1786. #define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
  1787. #define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
  1788. #define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
  1789. #define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
  1790. #define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
  1791. #define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
  1792. #define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
  1793. #define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
  1794. #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
  1795. /******************** Bit definition for ADC_JDR4 register ******************/
  1796. #define ADC_JDR4_JDATA_Pos (0U)
  1797. #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
  1798. #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
  1799. #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
  1800. #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
  1801. #define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
  1802. #define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
  1803. #define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
  1804. #define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
  1805. #define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
  1806. #define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
  1807. #define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
  1808. #define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
  1809. #define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
  1810. #define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
  1811. #define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
  1812. #define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
  1813. #define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
  1814. #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
  1815. /******************** Bit definition for ADC_AWD2CR register ****************/
  1816. #define ADC_AWD2CR_AWD2CH_Pos (0U)
  1817. #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
  1818. #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
  1819. #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
  1820. #define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
  1821. #define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
  1822. #define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
  1823. #define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
  1824. #define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
  1825. #define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
  1826. #define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
  1827. #define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
  1828. #define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
  1829. #define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
  1830. #define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
  1831. #define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
  1832. #define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
  1833. #define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
  1834. #define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
  1835. #define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
  1836. #define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
  1837. #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
  1838. /******************** Bit definition for ADC_AWD3CR register ****************/
  1839. #define ADC_AWD3CR_AWD3CH_Pos (0U)
  1840. #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
  1841. #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
  1842. #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
  1843. #define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
  1844. #define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
  1845. #define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
  1846. #define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
  1847. #define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
  1848. #define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
  1849. #define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
  1850. #define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
  1851. #define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
  1852. #define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
  1853. #define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
  1854. #define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
  1855. #define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
  1856. #define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
  1857. #define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
  1858. #define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
  1859. #define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
  1860. #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
  1861. /******************** Bit definition for ADC_DIFSEL register ****************/
  1862. #define ADC_DIFSEL_DIFSEL_Pos (0U)
  1863. #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
  1864. #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
  1865. #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
  1866. #define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
  1867. #define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
  1868. #define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
  1869. #define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
  1870. #define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
  1871. #define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
  1872. #define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
  1873. #define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
  1874. #define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
  1875. #define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
  1876. #define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
  1877. #define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
  1878. #define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
  1879. #define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
  1880. #define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
  1881. #define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
  1882. #define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
  1883. #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
  1884. /******************** Bit definition for ADC_CALFACT register ***************/
  1885. #define ADC_CALFACT_CALFACT_S_Pos (0U)
  1886. #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
  1887. #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
  1888. #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
  1889. #define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
  1890. #define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
  1891. #define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
  1892. #define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
  1893. #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
  1894. #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
  1895. #define ADC_CALFACT_CALFACT_D_Pos (16U)
  1896. #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
  1897. #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
  1898. #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
  1899. #define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
  1900. #define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
  1901. #define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
  1902. #define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
  1903. #define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
  1904. #define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
  1905. /************************* ADC Common registers *****************************/
  1906. /******************** Bit definition for ADC_CCR register *******************/
  1907. #define ADC_CCR_CKMODE_Pos (16U)
  1908. #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
  1909. #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
  1910. #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
  1911. #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
  1912. #define ADC_CCR_PRESC_Pos (18U)
  1913. #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
  1914. #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
  1915. #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
  1916. #define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
  1917. #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
  1918. #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
  1919. #define ADC_CCR_VREFEN_Pos (22U)
  1920. #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
  1921. #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
  1922. #define ADC_CCR_TSEN_Pos (23U)
  1923. #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
  1924. #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
  1925. #define ADC_CCR_VBATEN_Pos (24U)
  1926. #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
  1927. #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
  1928. /******************************************************************************/
  1929. /* */
  1930. /* Controller Area Network */
  1931. /* */
  1932. /******************************************************************************/
  1933. /*!<CAN control and status registers */
  1934. /******************* Bit definition for CAN_MCR register ********************/
  1935. #define CAN_MCR_INRQ_Pos (0U)
  1936. #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
  1937. #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
  1938. #define CAN_MCR_SLEEP_Pos (1U)
  1939. #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
  1940. #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
  1941. #define CAN_MCR_TXFP_Pos (2U)
  1942. #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
  1943. #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
  1944. #define CAN_MCR_RFLM_Pos (3U)
  1945. #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
  1946. #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
  1947. #define CAN_MCR_NART_Pos (4U)
  1948. #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
  1949. #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
  1950. #define CAN_MCR_AWUM_Pos (5U)
  1951. #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
  1952. #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
  1953. #define CAN_MCR_ABOM_Pos (6U)
  1954. #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
  1955. #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
  1956. #define CAN_MCR_TTCM_Pos (7U)
  1957. #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
  1958. #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
  1959. #define CAN_MCR_RESET_Pos (15U)
  1960. #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
  1961. #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
  1962. /******************* Bit definition for CAN_MSR register ********************/
  1963. #define CAN_MSR_INAK_Pos (0U)
  1964. #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
  1965. #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
  1966. #define CAN_MSR_SLAK_Pos (1U)
  1967. #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
  1968. #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
  1969. #define CAN_MSR_ERRI_Pos (2U)
  1970. #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
  1971. #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
  1972. #define CAN_MSR_WKUI_Pos (3U)
  1973. #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
  1974. #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
  1975. #define CAN_MSR_SLAKI_Pos (4U)
  1976. #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
  1977. #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
  1978. #define CAN_MSR_TXM_Pos (8U)
  1979. #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
  1980. #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
  1981. #define CAN_MSR_RXM_Pos (9U)
  1982. #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
  1983. #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
  1984. #define CAN_MSR_SAMP_Pos (10U)
  1985. #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
  1986. #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
  1987. #define CAN_MSR_RX_Pos (11U)
  1988. #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
  1989. #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
  1990. /******************* Bit definition for CAN_TSR register ********************/
  1991. #define CAN_TSR_RQCP0_Pos (0U)
  1992. #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
  1993. #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
  1994. #define CAN_TSR_TXOK0_Pos (1U)
  1995. #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
  1996. #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
  1997. #define CAN_TSR_ALST0_Pos (2U)
  1998. #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
  1999. #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
  2000. #define CAN_TSR_TERR0_Pos (3U)
  2001. #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
  2002. #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
  2003. #define CAN_TSR_ABRQ0_Pos (7U)
  2004. #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
  2005. #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
  2006. #define CAN_TSR_RQCP1_Pos (8U)
  2007. #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
  2008. #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
  2009. #define CAN_TSR_TXOK1_Pos (9U)
  2010. #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
  2011. #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
  2012. #define CAN_TSR_ALST1_Pos (10U)
  2013. #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
  2014. #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
  2015. #define CAN_TSR_TERR1_Pos (11U)
  2016. #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
  2017. #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
  2018. #define CAN_TSR_ABRQ1_Pos (15U)
  2019. #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
  2020. #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
  2021. #define CAN_TSR_RQCP2_Pos (16U)
  2022. #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
  2023. #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
  2024. #define CAN_TSR_TXOK2_Pos (17U)
  2025. #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
  2026. #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
  2027. #define CAN_TSR_ALST2_Pos (18U)
  2028. #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
  2029. #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
  2030. #define CAN_TSR_TERR2_Pos (19U)
  2031. #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
  2032. #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
  2033. #define CAN_TSR_ABRQ2_Pos (23U)
  2034. #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
  2035. #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
  2036. #define CAN_TSR_CODE_Pos (24U)
  2037. #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
  2038. #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
  2039. #define CAN_TSR_TME_Pos (26U)
  2040. #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
  2041. #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
  2042. #define CAN_TSR_TME0_Pos (26U)
  2043. #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
  2044. #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
  2045. #define CAN_TSR_TME1_Pos (27U)
  2046. #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
  2047. #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
  2048. #define CAN_TSR_TME2_Pos (28U)
  2049. #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
  2050. #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
  2051. #define CAN_TSR_LOW_Pos (29U)
  2052. #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
  2053. #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
  2054. #define CAN_TSR_LOW0_Pos (29U)
  2055. #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
  2056. #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
  2057. #define CAN_TSR_LOW1_Pos (30U)
  2058. #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
  2059. #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
  2060. #define CAN_TSR_LOW2_Pos (31U)
  2061. #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
  2062. #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
  2063. /******************* Bit definition for CAN_RF0R register *******************/
  2064. #define CAN_RF0R_FMP0_Pos (0U)
  2065. #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
  2066. #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
  2067. #define CAN_RF0R_FULL0_Pos (3U)
  2068. #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
  2069. #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
  2070. #define CAN_RF0R_FOVR0_Pos (4U)
  2071. #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
  2072. #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
  2073. #define CAN_RF0R_RFOM0_Pos (5U)
  2074. #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
  2075. #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
  2076. /******************* Bit definition for CAN_RF1R register *******************/
  2077. #define CAN_RF1R_FMP1_Pos (0U)
  2078. #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
  2079. #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
  2080. #define CAN_RF1R_FULL1_Pos (3U)
  2081. #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
  2082. #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
  2083. #define CAN_RF1R_FOVR1_Pos (4U)
  2084. #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
  2085. #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
  2086. #define CAN_RF1R_RFOM1_Pos (5U)
  2087. #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
  2088. #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
  2089. /******************** Bit definition for CAN_IER register *******************/
  2090. #define CAN_IER_TMEIE_Pos (0U)
  2091. #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
  2092. #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
  2093. #define CAN_IER_FMPIE0_Pos (1U)
  2094. #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
  2095. #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
  2096. #define CAN_IER_FFIE0_Pos (2U)
  2097. #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
  2098. #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
  2099. #define CAN_IER_FOVIE0_Pos (3U)
  2100. #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
  2101. #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
  2102. #define CAN_IER_FMPIE1_Pos (4U)
  2103. #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
  2104. #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
  2105. #define CAN_IER_FFIE1_Pos (5U)
  2106. #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
  2107. #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
  2108. #define CAN_IER_FOVIE1_Pos (6U)
  2109. #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
  2110. #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
  2111. #define CAN_IER_EWGIE_Pos (8U)
  2112. #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
  2113. #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
  2114. #define CAN_IER_EPVIE_Pos (9U)
  2115. #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
  2116. #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
  2117. #define CAN_IER_BOFIE_Pos (10U)
  2118. #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
  2119. #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
  2120. #define CAN_IER_LECIE_Pos (11U)
  2121. #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
  2122. #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
  2123. #define CAN_IER_ERRIE_Pos (15U)
  2124. #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
  2125. #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
  2126. #define CAN_IER_WKUIE_Pos (16U)
  2127. #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
  2128. #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
  2129. #define CAN_IER_SLKIE_Pos (17U)
  2130. #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
  2131. #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
  2132. /******************** Bit definition for CAN_ESR register *******************/
  2133. #define CAN_ESR_EWGF_Pos (0U)
  2134. #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
  2135. #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
  2136. #define CAN_ESR_EPVF_Pos (1U)
  2137. #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
  2138. #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
  2139. #define CAN_ESR_BOFF_Pos (2U)
  2140. #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
  2141. #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
  2142. #define CAN_ESR_LEC_Pos (4U)
  2143. #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
  2144. #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
  2145. #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
  2146. #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
  2147. #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
  2148. #define CAN_ESR_TEC_Pos (16U)
  2149. #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
  2150. #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
  2151. #define CAN_ESR_REC_Pos (24U)
  2152. #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
  2153. #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
  2154. /******************* Bit definition for CAN_BTR register ********************/
  2155. #define CAN_BTR_BRP_Pos (0U)
  2156. #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
  2157. #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
  2158. #define CAN_BTR_TS1_Pos (16U)
  2159. #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
  2160. #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
  2161. #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
  2162. #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
  2163. #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
  2164. #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
  2165. #define CAN_BTR_TS2_Pos (20U)
  2166. #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
  2167. #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
  2168. #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
  2169. #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
  2170. #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
  2171. #define CAN_BTR_SJW_Pos (24U)
  2172. #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
  2173. #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
  2174. #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
  2175. #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
  2176. #define CAN_BTR_LBKM_Pos (30U)
  2177. #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
  2178. #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
  2179. #define CAN_BTR_SILM_Pos (31U)
  2180. #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
  2181. #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
  2182. /*!<Mailbox registers */
  2183. /****************** Bit definition for CAN_TI0R register ********************/
  2184. #define CAN_TI0R_TXRQ_Pos (0U)
  2185. #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
  2186. #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
  2187. #define CAN_TI0R_RTR_Pos (1U)
  2188. #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
  2189. #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
  2190. #define CAN_TI0R_IDE_Pos (2U)
  2191. #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
  2192. #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
  2193. #define CAN_TI0R_EXID_Pos (3U)
  2194. #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
  2195. #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
  2196. #define CAN_TI0R_STID_Pos (21U)
  2197. #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
  2198. #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2199. /****************** Bit definition for CAN_TDT0R register *******************/
  2200. #define CAN_TDT0R_DLC_Pos (0U)
  2201. #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
  2202. #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
  2203. #define CAN_TDT0R_TGT_Pos (8U)
  2204. #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
  2205. #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
  2206. #define CAN_TDT0R_TIME_Pos (16U)
  2207. #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
  2208. #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
  2209. /****************** Bit definition for CAN_TDL0R register *******************/
  2210. #define CAN_TDL0R_DATA0_Pos (0U)
  2211. #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
  2212. #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
  2213. #define CAN_TDL0R_DATA1_Pos (8U)
  2214. #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
  2215. #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
  2216. #define CAN_TDL0R_DATA2_Pos (16U)
  2217. #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
  2218. #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
  2219. #define CAN_TDL0R_DATA3_Pos (24U)
  2220. #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
  2221. #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
  2222. /****************** Bit definition for CAN_TDH0R register *******************/
  2223. #define CAN_TDH0R_DATA4_Pos (0U)
  2224. #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
  2225. #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
  2226. #define CAN_TDH0R_DATA5_Pos (8U)
  2227. #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
  2228. #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
  2229. #define CAN_TDH0R_DATA6_Pos (16U)
  2230. #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
  2231. #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
  2232. #define CAN_TDH0R_DATA7_Pos (24U)
  2233. #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
  2234. #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
  2235. /******************* Bit definition for CAN_TI1R register *******************/
  2236. #define CAN_TI1R_TXRQ_Pos (0U)
  2237. #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
  2238. #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
  2239. #define CAN_TI1R_RTR_Pos (1U)
  2240. #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
  2241. #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
  2242. #define CAN_TI1R_IDE_Pos (2U)
  2243. #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
  2244. #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
  2245. #define CAN_TI1R_EXID_Pos (3U)
  2246. #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
  2247. #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
  2248. #define CAN_TI1R_STID_Pos (21U)
  2249. #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
  2250. #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2251. /******************* Bit definition for CAN_TDT1R register ******************/
  2252. #define CAN_TDT1R_DLC_Pos (0U)
  2253. #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
  2254. #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
  2255. #define CAN_TDT1R_TGT_Pos (8U)
  2256. #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
  2257. #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
  2258. #define CAN_TDT1R_TIME_Pos (16U)
  2259. #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
  2260. #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
  2261. /******************* Bit definition for CAN_TDL1R register ******************/
  2262. #define CAN_TDL1R_DATA0_Pos (0U)
  2263. #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
  2264. #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
  2265. #define CAN_TDL1R_DATA1_Pos (8U)
  2266. #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
  2267. #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
  2268. #define CAN_TDL1R_DATA2_Pos (16U)
  2269. #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
  2270. #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
  2271. #define CAN_TDL1R_DATA3_Pos (24U)
  2272. #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
  2273. #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
  2274. /******************* Bit definition for CAN_TDH1R register ******************/
  2275. #define CAN_TDH1R_DATA4_Pos (0U)
  2276. #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
  2277. #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
  2278. #define CAN_TDH1R_DATA5_Pos (8U)
  2279. #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
  2280. #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
  2281. #define CAN_TDH1R_DATA6_Pos (16U)
  2282. #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
  2283. #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
  2284. #define CAN_TDH1R_DATA7_Pos (24U)
  2285. #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
  2286. #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
  2287. /******************* Bit definition for CAN_TI2R register *******************/
  2288. #define CAN_TI2R_TXRQ_Pos (0U)
  2289. #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
  2290. #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
  2291. #define CAN_TI2R_RTR_Pos (1U)
  2292. #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
  2293. #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
  2294. #define CAN_TI2R_IDE_Pos (2U)
  2295. #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
  2296. #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
  2297. #define CAN_TI2R_EXID_Pos (3U)
  2298. #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
  2299. #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
  2300. #define CAN_TI2R_STID_Pos (21U)
  2301. #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
  2302. #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2303. /******************* Bit definition for CAN_TDT2R register ******************/
  2304. #define CAN_TDT2R_DLC_Pos (0U)
  2305. #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
  2306. #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
  2307. #define CAN_TDT2R_TGT_Pos (8U)
  2308. #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
  2309. #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
  2310. #define CAN_TDT2R_TIME_Pos (16U)
  2311. #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
  2312. #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
  2313. /******************* Bit definition for CAN_TDL2R register ******************/
  2314. #define CAN_TDL2R_DATA0_Pos (0U)
  2315. #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
  2316. #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
  2317. #define CAN_TDL2R_DATA1_Pos (8U)
  2318. #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
  2319. #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
  2320. #define CAN_TDL2R_DATA2_Pos (16U)
  2321. #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
  2322. #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
  2323. #define CAN_TDL2R_DATA3_Pos (24U)
  2324. #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
  2325. #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
  2326. /******************* Bit definition for CAN_TDH2R register ******************/
  2327. #define CAN_TDH2R_DATA4_Pos (0U)
  2328. #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
  2329. #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
  2330. #define CAN_TDH2R_DATA5_Pos (8U)
  2331. #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
  2332. #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
  2333. #define CAN_TDH2R_DATA6_Pos (16U)
  2334. #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
  2335. #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
  2336. #define CAN_TDH2R_DATA7_Pos (24U)
  2337. #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
  2338. #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
  2339. /******************* Bit definition for CAN_RI0R register *******************/
  2340. #define CAN_RI0R_RTR_Pos (1U)
  2341. #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
  2342. #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
  2343. #define CAN_RI0R_IDE_Pos (2U)
  2344. #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
  2345. #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
  2346. #define CAN_RI0R_EXID_Pos (3U)
  2347. #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
  2348. #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
  2349. #define CAN_RI0R_STID_Pos (21U)
  2350. #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
  2351. #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2352. /******************* Bit definition for CAN_RDT0R register ******************/
  2353. #define CAN_RDT0R_DLC_Pos (0U)
  2354. #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
  2355. #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
  2356. #define CAN_RDT0R_FMI_Pos (8U)
  2357. #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
  2358. #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
  2359. #define CAN_RDT0R_TIME_Pos (16U)
  2360. #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
  2361. #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
  2362. /******************* Bit definition for CAN_RDL0R register ******************/
  2363. #define CAN_RDL0R_DATA0_Pos (0U)
  2364. #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
  2365. #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
  2366. #define CAN_RDL0R_DATA1_Pos (8U)
  2367. #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
  2368. #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
  2369. #define CAN_RDL0R_DATA2_Pos (16U)
  2370. #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
  2371. #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
  2372. #define CAN_RDL0R_DATA3_Pos (24U)
  2373. #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
  2374. #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
  2375. /******************* Bit definition for CAN_RDH0R register ******************/
  2376. #define CAN_RDH0R_DATA4_Pos (0U)
  2377. #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
  2378. #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
  2379. #define CAN_RDH0R_DATA5_Pos (8U)
  2380. #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
  2381. #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
  2382. #define CAN_RDH0R_DATA6_Pos (16U)
  2383. #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
  2384. #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
  2385. #define CAN_RDH0R_DATA7_Pos (24U)
  2386. #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
  2387. #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
  2388. /******************* Bit definition for CAN_RI1R register *******************/
  2389. #define CAN_RI1R_RTR_Pos (1U)
  2390. #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
  2391. #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
  2392. #define CAN_RI1R_IDE_Pos (2U)
  2393. #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
  2394. #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
  2395. #define CAN_RI1R_EXID_Pos (3U)
  2396. #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
  2397. #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
  2398. #define CAN_RI1R_STID_Pos (21U)
  2399. #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
  2400. #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2401. /******************* Bit definition for CAN_RDT1R register ******************/
  2402. #define CAN_RDT1R_DLC_Pos (0U)
  2403. #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
  2404. #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
  2405. #define CAN_RDT1R_FMI_Pos (8U)
  2406. #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
  2407. #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
  2408. #define CAN_RDT1R_TIME_Pos (16U)
  2409. #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
  2410. #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
  2411. /******************* Bit definition for CAN_RDL1R register ******************/
  2412. #define CAN_RDL1R_DATA0_Pos (0U)
  2413. #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
  2414. #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
  2415. #define CAN_RDL1R_DATA1_Pos (8U)
  2416. #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
  2417. #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
  2418. #define CAN_RDL1R_DATA2_Pos (16U)
  2419. #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
  2420. #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
  2421. #define CAN_RDL1R_DATA3_Pos (24U)
  2422. #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
  2423. #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
  2424. /******************* Bit definition for CAN_RDH1R register ******************/
  2425. #define CAN_RDH1R_DATA4_Pos (0U)
  2426. #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
  2427. #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
  2428. #define CAN_RDH1R_DATA5_Pos (8U)
  2429. #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
  2430. #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
  2431. #define CAN_RDH1R_DATA6_Pos (16U)
  2432. #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
  2433. #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
  2434. #define CAN_RDH1R_DATA7_Pos (24U)
  2435. #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
  2436. #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
  2437. /*!<CAN filter registers */
  2438. /******************* Bit definition for CAN_FMR register ********************/
  2439. #define CAN_FMR_FINIT_Pos (0U)
  2440. #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
  2441. #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
  2442. /******************* Bit definition for CAN_FM1R register *******************/
  2443. #define CAN_FM1R_FBM_Pos (0U)
  2444. #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
  2445. #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
  2446. #define CAN_FM1R_FBM0_Pos (0U)
  2447. #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
  2448. #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
  2449. #define CAN_FM1R_FBM1_Pos (1U)
  2450. #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
  2451. #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
  2452. #define CAN_FM1R_FBM2_Pos (2U)
  2453. #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
  2454. #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
  2455. #define CAN_FM1R_FBM3_Pos (3U)
  2456. #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
  2457. #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
  2458. #define CAN_FM1R_FBM4_Pos (4U)
  2459. #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
  2460. #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
  2461. #define CAN_FM1R_FBM5_Pos (5U)
  2462. #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
  2463. #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
  2464. #define CAN_FM1R_FBM6_Pos (6U)
  2465. #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
  2466. #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
  2467. #define CAN_FM1R_FBM7_Pos (7U)
  2468. #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
  2469. #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
  2470. #define CAN_FM1R_FBM8_Pos (8U)
  2471. #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
  2472. #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
  2473. #define CAN_FM1R_FBM9_Pos (9U)
  2474. #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
  2475. #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
  2476. #define CAN_FM1R_FBM10_Pos (10U)
  2477. #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
  2478. #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
  2479. #define CAN_FM1R_FBM11_Pos (11U)
  2480. #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
  2481. #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
  2482. #define CAN_FM1R_FBM12_Pos (12U)
  2483. #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
  2484. #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
  2485. #define CAN_FM1R_FBM13_Pos (13U)
  2486. #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
  2487. #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
  2488. /******************* Bit definition for CAN_FS1R register *******************/
  2489. #define CAN_FS1R_FSC_Pos (0U)
  2490. #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
  2491. #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
  2492. #define CAN_FS1R_FSC0_Pos (0U)
  2493. #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
  2494. #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
  2495. #define CAN_FS1R_FSC1_Pos (1U)
  2496. #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
  2497. #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
  2498. #define CAN_FS1R_FSC2_Pos (2U)
  2499. #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
  2500. #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
  2501. #define CAN_FS1R_FSC3_Pos (3U)
  2502. #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
  2503. #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
  2504. #define CAN_FS1R_FSC4_Pos (4U)
  2505. #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
  2506. #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
  2507. #define CAN_FS1R_FSC5_Pos (5U)
  2508. #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
  2509. #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
  2510. #define CAN_FS1R_FSC6_Pos (6U)
  2511. #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
  2512. #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
  2513. #define CAN_FS1R_FSC7_Pos (7U)
  2514. #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
  2515. #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
  2516. #define CAN_FS1R_FSC8_Pos (8U)
  2517. #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
  2518. #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
  2519. #define CAN_FS1R_FSC9_Pos (9U)
  2520. #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
  2521. #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
  2522. #define CAN_FS1R_FSC10_Pos (10U)
  2523. #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
  2524. #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
  2525. #define CAN_FS1R_FSC11_Pos (11U)
  2526. #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
  2527. #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
  2528. #define CAN_FS1R_FSC12_Pos (12U)
  2529. #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
  2530. #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
  2531. #define CAN_FS1R_FSC13_Pos (13U)
  2532. #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
  2533. #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
  2534. /****************** Bit definition for CAN_FFA1R register *******************/
  2535. #define CAN_FFA1R_FFA_Pos (0U)
  2536. #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
  2537. #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
  2538. #define CAN_FFA1R_FFA0_Pos (0U)
  2539. #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
  2540. #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
  2541. #define CAN_FFA1R_FFA1_Pos (1U)
  2542. #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
  2543. #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
  2544. #define CAN_FFA1R_FFA2_Pos (2U)
  2545. #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
  2546. #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
  2547. #define CAN_FFA1R_FFA3_Pos (3U)
  2548. #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
  2549. #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
  2550. #define CAN_FFA1R_FFA4_Pos (4U)
  2551. #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
  2552. #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
  2553. #define CAN_FFA1R_FFA5_Pos (5U)
  2554. #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
  2555. #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
  2556. #define CAN_FFA1R_FFA6_Pos (6U)
  2557. #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
  2558. #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
  2559. #define CAN_FFA1R_FFA7_Pos (7U)
  2560. #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
  2561. #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
  2562. #define CAN_FFA1R_FFA8_Pos (8U)
  2563. #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
  2564. #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
  2565. #define CAN_FFA1R_FFA9_Pos (9U)
  2566. #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
  2567. #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
  2568. #define CAN_FFA1R_FFA10_Pos (10U)
  2569. #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
  2570. #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
  2571. #define CAN_FFA1R_FFA11_Pos (11U)
  2572. #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
  2573. #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
  2574. #define CAN_FFA1R_FFA12_Pos (12U)
  2575. #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
  2576. #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
  2577. #define CAN_FFA1R_FFA13_Pos (13U)
  2578. #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
  2579. #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
  2580. /******************* Bit definition for CAN_FA1R register *******************/
  2581. #define CAN_FA1R_FACT_Pos (0U)
  2582. #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
  2583. #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
  2584. #define CAN_FA1R_FACT0_Pos (0U)
  2585. #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
  2586. #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
  2587. #define CAN_FA1R_FACT1_Pos (1U)
  2588. #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
  2589. #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
  2590. #define CAN_FA1R_FACT2_Pos (2U)
  2591. #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
  2592. #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
  2593. #define CAN_FA1R_FACT3_Pos (3U)
  2594. #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
  2595. #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
  2596. #define CAN_FA1R_FACT4_Pos (4U)
  2597. #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
  2598. #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
  2599. #define CAN_FA1R_FACT5_Pos (5U)
  2600. #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
  2601. #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
  2602. #define CAN_FA1R_FACT6_Pos (6U)
  2603. #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
  2604. #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
  2605. #define CAN_FA1R_FACT7_Pos (7U)
  2606. #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
  2607. #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
  2608. #define CAN_FA1R_FACT8_Pos (8U)
  2609. #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
  2610. #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
  2611. #define CAN_FA1R_FACT9_Pos (9U)
  2612. #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
  2613. #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
  2614. #define CAN_FA1R_FACT10_Pos (10U)
  2615. #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
  2616. #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
  2617. #define CAN_FA1R_FACT11_Pos (11U)
  2618. #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
  2619. #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
  2620. #define CAN_FA1R_FACT12_Pos (12U)
  2621. #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
  2622. #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
  2623. #define CAN_FA1R_FACT13_Pos (13U)
  2624. #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
  2625. #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
  2626. /******************* Bit definition for CAN_F0R1 register *******************/
  2627. #define CAN_F0R1_FB0_Pos (0U)
  2628. #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
  2629. #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
  2630. #define CAN_F0R1_FB1_Pos (1U)
  2631. #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
  2632. #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
  2633. #define CAN_F0R1_FB2_Pos (2U)
  2634. #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
  2635. #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
  2636. #define CAN_F0R1_FB3_Pos (3U)
  2637. #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
  2638. #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
  2639. #define CAN_F0R1_FB4_Pos (4U)
  2640. #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
  2641. #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
  2642. #define CAN_F0R1_FB5_Pos (5U)
  2643. #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
  2644. #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
  2645. #define CAN_F0R1_FB6_Pos (6U)
  2646. #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
  2647. #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
  2648. #define CAN_F0R1_FB7_Pos (7U)
  2649. #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
  2650. #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
  2651. #define CAN_F0R1_FB8_Pos (8U)
  2652. #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
  2653. #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
  2654. #define CAN_F0R1_FB9_Pos (9U)
  2655. #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
  2656. #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
  2657. #define CAN_F0R1_FB10_Pos (10U)
  2658. #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
  2659. #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
  2660. #define CAN_F0R1_FB11_Pos (11U)
  2661. #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
  2662. #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
  2663. #define CAN_F0R1_FB12_Pos (12U)
  2664. #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
  2665. #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
  2666. #define CAN_F0R1_FB13_Pos (13U)
  2667. #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
  2668. #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
  2669. #define CAN_F0R1_FB14_Pos (14U)
  2670. #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
  2671. #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
  2672. #define CAN_F0R1_FB15_Pos (15U)
  2673. #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
  2674. #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
  2675. #define CAN_F0R1_FB16_Pos (16U)
  2676. #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
  2677. #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
  2678. #define CAN_F0R1_FB17_Pos (17U)
  2679. #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
  2680. #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
  2681. #define CAN_F0R1_FB18_Pos (18U)
  2682. #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
  2683. #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
  2684. #define CAN_F0R1_FB19_Pos (19U)
  2685. #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
  2686. #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
  2687. #define CAN_F0R1_FB20_Pos (20U)
  2688. #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
  2689. #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
  2690. #define CAN_F0R1_FB21_Pos (21U)
  2691. #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
  2692. #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
  2693. #define CAN_F0R1_FB22_Pos (22U)
  2694. #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
  2695. #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
  2696. #define CAN_F0R1_FB23_Pos (23U)
  2697. #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
  2698. #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
  2699. #define CAN_F0R1_FB24_Pos (24U)
  2700. #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
  2701. #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
  2702. #define CAN_F0R1_FB25_Pos (25U)
  2703. #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
  2704. #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
  2705. #define CAN_F0R1_FB26_Pos (26U)
  2706. #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
  2707. #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
  2708. #define CAN_F0R1_FB27_Pos (27U)
  2709. #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
  2710. #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
  2711. #define CAN_F0R1_FB28_Pos (28U)
  2712. #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
  2713. #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
  2714. #define CAN_F0R1_FB29_Pos (29U)
  2715. #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
  2716. #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
  2717. #define CAN_F0R1_FB30_Pos (30U)
  2718. #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
  2719. #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
  2720. #define CAN_F0R1_FB31_Pos (31U)
  2721. #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
  2722. #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
  2723. /******************* Bit definition for CAN_F1R1 register *******************/
  2724. #define CAN_F1R1_FB0_Pos (0U)
  2725. #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
  2726. #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
  2727. #define CAN_F1R1_FB1_Pos (1U)
  2728. #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
  2729. #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
  2730. #define CAN_F1R1_FB2_Pos (2U)
  2731. #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
  2732. #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
  2733. #define CAN_F1R1_FB3_Pos (3U)
  2734. #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
  2735. #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
  2736. #define CAN_F1R1_FB4_Pos (4U)
  2737. #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
  2738. #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
  2739. #define CAN_F1R1_FB5_Pos (5U)
  2740. #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
  2741. #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
  2742. #define CAN_F1R1_FB6_Pos (6U)
  2743. #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
  2744. #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
  2745. #define CAN_F1R1_FB7_Pos (7U)
  2746. #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
  2747. #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
  2748. #define CAN_F1R1_FB8_Pos (8U)
  2749. #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
  2750. #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
  2751. #define CAN_F1R1_FB9_Pos (9U)
  2752. #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
  2753. #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
  2754. #define CAN_F1R1_FB10_Pos (10U)
  2755. #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
  2756. #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
  2757. #define CAN_F1R1_FB11_Pos (11U)
  2758. #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
  2759. #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
  2760. #define CAN_F1R1_FB12_Pos (12U)
  2761. #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
  2762. #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
  2763. #define CAN_F1R1_FB13_Pos (13U)
  2764. #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
  2765. #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
  2766. #define CAN_F1R1_FB14_Pos (14U)
  2767. #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
  2768. #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
  2769. #define CAN_F1R1_FB15_Pos (15U)
  2770. #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
  2771. #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
  2772. #define CAN_F1R1_FB16_Pos (16U)
  2773. #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
  2774. #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
  2775. #define CAN_F1R1_FB17_Pos (17U)
  2776. #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
  2777. #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
  2778. #define CAN_F1R1_FB18_Pos (18U)
  2779. #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
  2780. #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
  2781. #define CAN_F1R1_FB19_Pos (19U)
  2782. #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
  2783. #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
  2784. #define CAN_F1R1_FB20_Pos (20U)
  2785. #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
  2786. #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
  2787. #define CAN_F1R1_FB21_Pos (21U)
  2788. #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
  2789. #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
  2790. #define CAN_F1R1_FB22_Pos (22U)
  2791. #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
  2792. #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
  2793. #define CAN_F1R1_FB23_Pos (23U)
  2794. #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
  2795. #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
  2796. #define CAN_F1R1_FB24_Pos (24U)
  2797. #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
  2798. #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
  2799. #define CAN_F1R1_FB25_Pos (25U)
  2800. #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
  2801. #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
  2802. #define CAN_F1R1_FB26_Pos (26U)
  2803. #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
  2804. #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
  2805. #define CAN_F1R1_FB27_Pos (27U)
  2806. #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
  2807. #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
  2808. #define CAN_F1R1_FB28_Pos (28U)
  2809. #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
  2810. #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
  2811. #define CAN_F1R1_FB29_Pos (29U)
  2812. #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
  2813. #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
  2814. #define CAN_F1R1_FB30_Pos (30U)
  2815. #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
  2816. #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
  2817. #define CAN_F1R1_FB31_Pos (31U)
  2818. #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
  2819. #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
  2820. /******************* Bit definition for CAN_F2R1 register *******************/
  2821. #define CAN_F2R1_FB0_Pos (0U)
  2822. #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
  2823. #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
  2824. #define CAN_F2R1_FB1_Pos (1U)
  2825. #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
  2826. #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
  2827. #define CAN_F2R1_FB2_Pos (2U)
  2828. #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
  2829. #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
  2830. #define CAN_F2R1_FB3_Pos (3U)
  2831. #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
  2832. #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
  2833. #define CAN_F2R1_FB4_Pos (4U)
  2834. #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
  2835. #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
  2836. #define CAN_F2R1_FB5_Pos (5U)
  2837. #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
  2838. #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
  2839. #define CAN_F2R1_FB6_Pos (6U)
  2840. #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
  2841. #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
  2842. #define CAN_F2R1_FB7_Pos (7U)
  2843. #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
  2844. #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
  2845. #define CAN_F2R1_FB8_Pos (8U)
  2846. #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
  2847. #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
  2848. #define CAN_F2R1_FB9_Pos (9U)
  2849. #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
  2850. #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
  2851. #define CAN_F2R1_FB10_Pos (10U)
  2852. #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
  2853. #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
  2854. #define CAN_F2R1_FB11_Pos (11U)
  2855. #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
  2856. #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
  2857. #define CAN_F2R1_FB12_Pos (12U)
  2858. #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
  2859. #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
  2860. #define CAN_F2R1_FB13_Pos (13U)
  2861. #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
  2862. #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
  2863. #define CAN_F2R1_FB14_Pos (14U)
  2864. #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
  2865. #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
  2866. #define CAN_F2R1_FB15_Pos (15U)
  2867. #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
  2868. #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
  2869. #define CAN_F2R1_FB16_Pos (16U)
  2870. #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
  2871. #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
  2872. #define CAN_F2R1_FB17_Pos (17U)
  2873. #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
  2874. #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
  2875. #define CAN_F2R1_FB18_Pos (18U)
  2876. #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
  2877. #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
  2878. #define CAN_F2R1_FB19_Pos (19U)
  2879. #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
  2880. #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
  2881. #define CAN_F2R1_FB20_Pos (20U)
  2882. #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
  2883. #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
  2884. #define CAN_F2R1_FB21_Pos (21U)
  2885. #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
  2886. #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
  2887. #define CAN_F2R1_FB22_Pos (22U)
  2888. #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
  2889. #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
  2890. #define CAN_F2R1_FB23_Pos (23U)
  2891. #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
  2892. #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
  2893. #define CAN_F2R1_FB24_Pos (24U)
  2894. #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
  2895. #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
  2896. #define CAN_F2R1_FB25_Pos (25U)
  2897. #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
  2898. #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
  2899. #define CAN_F2R1_FB26_Pos (26U)
  2900. #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
  2901. #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
  2902. #define CAN_F2R1_FB27_Pos (27U)
  2903. #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
  2904. #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
  2905. #define CAN_F2R1_FB28_Pos (28U)
  2906. #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
  2907. #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
  2908. #define CAN_F2R1_FB29_Pos (29U)
  2909. #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
  2910. #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
  2911. #define CAN_F2R1_FB30_Pos (30U)
  2912. #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
  2913. #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
  2914. #define CAN_F2R1_FB31_Pos (31U)
  2915. #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
  2916. #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
  2917. /******************* Bit definition for CAN_F3R1 register *******************/
  2918. #define CAN_F3R1_FB0_Pos (0U)
  2919. #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
  2920. #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
  2921. #define CAN_F3R1_FB1_Pos (1U)
  2922. #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
  2923. #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
  2924. #define CAN_F3R1_FB2_Pos (2U)
  2925. #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
  2926. #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
  2927. #define CAN_F3R1_FB3_Pos (3U)
  2928. #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
  2929. #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
  2930. #define CAN_F3R1_FB4_Pos (4U)
  2931. #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
  2932. #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
  2933. #define CAN_F3R1_FB5_Pos (5U)
  2934. #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
  2935. #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
  2936. #define CAN_F3R1_FB6_Pos (6U)
  2937. #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
  2938. #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
  2939. #define CAN_F3R1_FB7_Pos (7U)
  2940. #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
  2941. #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
  2942. #define CAN_F3R1_FB8_Pos (8U)
  2943. #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
  2944. #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
  2945. #define CAN_F3R1_FB9_Pos (9U)
  2946. #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
  2947. #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
  2948. #define CAN_F3R1_FB10_Pos (10U)
  2949. #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
  2950. #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
  2951. #define CAN_F3R1_FB11_Pos (11U)
  2952. #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
  2953. #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
  2954. #define CAN_F3R1_FB12_Pos (12U)
  2955. #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
  2956. #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
  2957. #define CAN_F3R1_FB13_Pos (13U)
  2958. #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
  2959. #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
  2960. #define CAN_F3R1_FB14_Pos (14U)
  2961. #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
  2962. #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
  2963. #define CAN_F3R1_FB15_Pos (15U)
  2964. #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
  2965. #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
  2966. #define CAN_F3R1_FB16_Pos (16U)
  2967. #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
  2968. #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
  2969. #define CAN_F3R1_FB17_Pos (17U)
  2970. #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
  2971. #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
  2972. #define CAN_F3R1_FB18_Pos (18U)
  2973. #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
  2974. #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
  2975. #define CAN_F3R1_FB19_Pos (19U)
  2976. #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
  2977. #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
  2978. #define CAN_F3R1_FB20_Pos (20U)
  2979. #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
  2980. #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
  2981. #define CAN_F3R1_FB21_Pos (21U)
  2982. #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
  2983. #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
  2984. #define CAN_F3R1_FB22_Pos (22U)
  2985. #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
  2986. #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
  2987. #define CAN_F3R1_FB23_Pos (23U)
  2988. #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
  2989. #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
  2990. #define CAN_F3R1_FB24_Pos (24U)
  2991. #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
  2992. #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
  2993. #define CAN_F3R1_FB25_Pos (25U)
  2994. #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
  2995. #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
  2996. #define CAN_F3R1_FB26_Pos (26U)
  2997. #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
  2998. #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
  2999. #define CAN_F3R1_FB27_Pos (27U)
  3000. #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
  3001. #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
  3002. #define CAN_F3R1_FB28_Pos (28U)
  3003. #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
  3004. #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
  3005. #define CAN_F3R1_FB29_Pos (29U)
  3006. #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
  3007. #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
  3008. #define CAN_F3R1_FB30_Pos (30U)
  3009. #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
  3010. #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
  3011. #define CAN_F3R1_FB31_Pos (31U)
  3012. #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
  3013. #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
  3014. /******************* Bit definition for CAN_F4R1 register *******************/
  3015. #define CAN_F4R1_FB0_Pos (0U)
  3016. #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
  3017. #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
  3018. #define CAN_F4R1_FB1_Pos (1U)
  3019. #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
  3020. #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
  3021. #define CAN_F4R1_FB2_Pos (2U)
  3022. #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
  3023. #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
  3024. #define CAN_F4R1_FB3_Pos (3U)
  3025. #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
  3026. #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
  3027. #define CAN_F4R1_FB4_Pos (4U)
  3028. #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
  3029. #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
  3030. #define CAN_F4R1_FB5_Pos (5U)
  3031. #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
  3032. #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
  3033. #define CAN_F4R1_FB6_Pos (6U)
  3034. #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
  3035. #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
  3036. #define CAN_F4R1_FB7_Pos (7U)
  3037. #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
  3038. #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
  3039. #define CAN_F4R1_FB8_Pos (8U)
  3040. #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
  3041. #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
  3042. #define CAN_F4R1_FB9_Pos (9U)
  3043. #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
  3044. #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
  3045. #define CAN_F4R1_FB10_Pos (10U)
  3046. #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
  3047. #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
  3048. #define CAN_F4R1_FB11_Pos (11U)
  3049. #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
  3050. #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
  3051. #define CAN_F4R1_FB12_Pos (12U)
  3052. #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
  3053. #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
  3054. #define CAN_F4R1_FB13_Pos (13U)
  3055. #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
  3056. #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
  3057. #define CAN_F4R1_FB14_Pos (14U)
  3058. #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
  3059. #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
  3060. #define CAN_F4R1_FB15_Pos (15U)
  3061. #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
  3062. #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
  3063. #define CAN_F4R1_FB16_Pos (16U)
  3064. #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
  3065. #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
  3066. #define CAN_F4R1_FB17_Pos (17U)
  3067. #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
  3068. #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
  3069. #define CAN_F4R1_FB18_Pos (18U)
  3070. #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
  3071. #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
  3072. #define CAN_F4R1_FB19_Pos (19U)
  3073. #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
  3074. #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
  3075. #define CAN_F4R1_FB20_Pos (20U)
  3076. #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
  3077. #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
  3078. #define CAN_F4R1_FB21_Pos (21U)
  3079. #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
  3080. #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
  3081. #define CAN_F4R1_FB22_Pos (22U)
  3082. #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
  3083. #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
  3084. #define CAN_F4R1_FB23_Pos (23U)
  3085. #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
  3086. #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
  3087. #define CAN_F4R1_FB24_Pos (24U)
  3088. #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
  3089. #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
  3090. #define CAN_F4R1_FB25_Pos (25U)
  3091. #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
  3092. #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
  3093. #define CAN_F4R1_FB26_Pos (26U)
  3094. #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
  3095. #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
  3096. #define CAN_F4R1_FB27_Pos (27U)
  3097. #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
  3098. #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
  3099. #define CAN_F4R1_FB28_Pos (28U)
  3100. #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
  3101. #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
  3102. #define CAN_F4R1_FB29_Pos (29U)
  3103. #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
  3104. #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
  3105. #define CAN_F4R1_FB30_Pos (30U)
  3106. #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
  3107. #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
  3108. #define CAN_F4R1_FB31_Pos (31U)
  3109. #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
  3110. #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
  3111. /******************* Bit definition for CAN_F5R1 register *******************/
  3112. #define CAN_F5R1_FB0_Pos (0U)
  3113. #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
  3114. #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
  3115. #define CAN_F5R1_FB1_Pos (1U)
  3116. #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
  3117. #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
  3118. #define CAN_F5R1_FB2_Pos (2U)
  3119. #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
  3120. #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
  3121. #define CAN_F5R1_FB3_Pos (3U)
  3122. #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
  3123. #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
  3124. #define CAN_F5R1_FB4_Pos (4U)
  3125. #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
  3126. #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
  3127. #define CAN_F5R1_FB5_Pos (5U)
  3128. #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
  3129. #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
  3130. #define CAN_F5R1_FB6_Pos (6U)
  3131. #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
  3132. #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
  3133. #define CAN_F5R1_FB7_Pos (7U)
  3134. #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
  3135. #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
  3136. #define CAN_F5R1_FB8_Pos (8U)
  3137. #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
  3138. #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
  3139. #define CAN_F5R1_FB9_Pos (9U)
  3140. #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
  3141. #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
  3142. #define CAN_F5R1_FB10_Pos (10U)
  3143. #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
  3144. #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
  3145. #define CAN_F5R1_FB11_Pos (11U)
  3146. #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
  3147. #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
  3148. #define CAN_F5R1_FB12_Pos (12U)
  3149. #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
  3150. #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
  3151. #define CAN_F5R1_FB13_Pos (13U)
  3152. #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
  3153. #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
  3154. #define CAN_F5R1_FB14_Pos (14U)
  3155. #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
  3156. #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
  3157. #define CAN_F5R1_FB15_Pos (15U)
  3158. #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
  3159. #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
  3160. #define CAN_F5R1_FB16_Pos (16U)
  3161. #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
  3162. #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
  3163. #define CAN_F5R1_FB17_Pos (17U)
  3164. #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
  3165. #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
  3166. #define CAN_F5R1_FB18_Pos (18U)
  3167. #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
  3168. #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
  3169. #define CAN_F5R1_FB19_Pos (19U)
  3170. #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
  3171. #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
  3172. #define CAN_F5R1_FB20_Pos (20U)
  3173. #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
  3174. #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
  3175. #define CAN_F5R1_FB21_Pos (21U)
  3176. #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
  3177. #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
  3178. #define CAN_F5R1_FB22_Pos (22U)
  3179. #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
  3180. #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
  3181. #define CAN_F5R1_FB23_Pos (23U)
  3182. #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
  3183. #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
  3184. #define CAN_F5R1_FB24_Pos (24U)
  3185. #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
  3186. #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
  3187. #define CAN_F5R1_FB25_Pos (25U)
  3188. #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
  3189. #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
  3190. #define CAN_F5R1_FB26_Pos (26U)
  3191. #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
  3192. #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
  3193. #define CAN_F5R1_FB27_Pos (27U)
  3194. #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
  3195. #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
  3196. #define CAN_F5R1_FB28_Pos (28U)
  3197. #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
  3198. #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
  3199. #define CAN_F5R1_FB29_Pos (29U)
  3200. #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
  3201. #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
  3202. #define CAN_F5R1_FB30_Pos (30U)
  3203. #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
  3204. #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
  3205. #define CAN_F5R1_FB31_Pos (31U)
  3206. #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
  3207. #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
  3208. /******************* Bit definition for CAN_F6R1 register *******************/
  3209. #define CAN_F6R1_FB0_Pos (0U)
  3210. #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
  3211. #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
  3212. #define CAN_F6R1_FB1_Pos (1U)
  3213. #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
  3214. #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
  3215. #define CAN_F6R1_FB2_Pos (2U)
  3216. #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
  3217. #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
  3218. #define CAN_F6R1_FB3_Pos (3U)
  3219. #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
  3220. #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
  3221. #define CAN_F6R1_FB4_Pos (4U)
  3222. #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
  3223. #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
  3224. #define CAN_F6R1_FB5_Pos (5U)
  3225. #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
  3226. #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
  3227. #define CAN_F6R1_FB6_Pos (6U)
  3228. #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
  3229. #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
  3230. #define CAN_F6R1_FB7_Pos (7U)
  3231. #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
  3232. #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
  3233. #define CAN_F6R1_FB8_Pos (8U)
  3234. #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
  3235. #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
  3236. #define CAN_F6R1_FB9_Pos (9U)
  3237. #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
  3238. #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
  3239. #define CAN_F6R1_FB10_Pos (10U)
  3240. #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
  3241. #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
  3242. #define CAN_F6R1_FB11_Pos (11U)
  3243. #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
  3244. #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
  3245. #define CAN_F6R1_FB12_Pos (12U)
  3246. #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
  3247. #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
  3248. #define CAN_F6R1_FB13_Pos (13U)
  3249. #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
  3250. #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
  3251. #define CAN_F6R1_FB14_Pos (14U)
  3252. #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
  3253. #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
  3254. #define CAN_F6R1_FB15_Pos (15U)
  3255. #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
  3256. #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
  3257. #define CAN_F6R1_FB16_Pos (16U)
  3258. #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
  3259. #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
  3260. #define CAN_F6R1_FB17_Pos (17U)
  3261. #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
  3262. #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
  3263. #define CAN_F6R1_FB18_Pos (18U)
  3264. #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
  3265. #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
  3266. #define CAN_F6R1_FB19_Pos (19U)
  3267. #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
  3268. #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
  3269. #define CAN_F6R1_FB20_Pos (20U)
  3270. #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
  3271. #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
  3272. #define CAN_F6R1_FB21_Pos (21U)
  3273. #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
  3274. #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
  3275. #define CAN_F6R1_FB22_Pos (22U)
  3276. #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
  3277. #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
  3278. #define CAN_F6R1_FB23_Pos (23U)
  3279. #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
  3280. #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
  3281. #define CAN_F6R1_FB24_Pos (24U)
  3282. #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
  3283. #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
  3284. #define CAN_F6R1_FB25_Pos (25U)
  3285. #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
  3286. #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
  3287. #define CAN_F6R1_FB26_Pos (26U)
  3288. #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
  3289. #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
  3290. #define CAN_F6R1_FB27_Pos (27U)
  3291. #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
  3292. #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
  3293. #define CAN_F6R1_FB28_Pos (28U)
  3294. #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
  3295. #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
  3296. #define CAN_F6R1_FB29_Pos (29U)
  3297. #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
  3298. #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
  3299. #define CAN_F6R1_FB30_Pos (30U)
  3300. #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
  3301. #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
  3302. #define CAN_F6R1_FB31_Pos (31U)
  3303. #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
  3304. #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
  3305. /******************* Bit definition for CAN_F7R1 register *******************/
  3306. #define CAN_F7R1_FB0_Pos (0U)
  3307. #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
  3308. #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
  3309. #define CAN_F7R1_FB1_Pos (1U)
  3310. #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
  3311. #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
  3312. #define CAN_F7R1_FB2_Pos (2U)
  3313. #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
  3314. #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
  3315. #define CAN_F7R1_FB3_Pos (3U)
  3316. #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
  3317. #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
  3318. #define CAN_F7R1_FB4_Pos (4U)
  3319. #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
  3320. #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
  3321. #define CAN_F7R1_FB5_Pos (5U)
  3322. #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
  3323. #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
  3324. #define CAN_F7R1_FB6_Pos (6U)
  3325. #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
  3326. #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
  3327. #define CAN_F7R1_FB7_Pos (7U)
  3328. #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
  3329. #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
  3330. #define CAN_F7R1_FB8_Pos (8U)
  3331. #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
  3332. #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
  3333. #define CAN_F7R1_FB9_Pos (9U)
  3334. #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
  3335. #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
  3336. #define CAN_F7R1_FB10_Pos (10U)
  3337. #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
  3338. #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
  3339. #define CAN_F7R1_FB11_Pos (11U)
  3340. #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
  3341. #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
  3342. #define CAN_F7R1_FB12_Pos (12U)
  3343. #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
  3344. #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
  3345. #define CAN_F7R1_FB13_Pos (13U)
  3346. #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
  3347. #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
  3348. #define CAN_F7R1_FB14_Pos (14U)
  3349. #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
  3350. #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
  3351. #define CAN_F7R1_FB15_Pos (15U)
  3352. #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
  3353. #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
  3354. #define CAN_F7R1_FB16_Pos (16U)
  3355. #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
  3356. #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
  3357. #define CAN_F7R1_FB17_Pos (17U)
  3358. #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
  3359. #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
  3360. #define CAN_F7R1_FB18_Pos (18U)
  3361. #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
  3362. #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
  3363. #define CAN_F7R1_FB19_Pos (19U)
  3364. #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
  3365. #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
  3366. #define CAN_F7R1_FB20_Pos (20U)
  3367. #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
  3368. #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
  3369. #define CAN_F7R1_FB21_Pos (21U)
  3370. #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
  3371. #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
  3372. #define CAN_F7R1_FB22_Pos (22U)
  3373. #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
  3374. #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
  3375. #define CAN_F7R1_FB23_Pos (23U)
  3376. #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
  3377. #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
  3378. #define CAN_F7R1_FB24_Pos (24U)
  3379. #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
  3380. #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
  3381. #define CAN_F7R1_FB25_Pos (25U)
  3382. #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
  3383. #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
  3384. #define CAN_F7R1_FB26_Pos (26U)
  3385. #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
  3386. #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
  3387. #define CAN_F7R1_FB27_Pos (27U)
  3388. #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
  3389. #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
  3390. #define CAN_F7R1_FB28_Pos (28U)
  3391. #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
  3392. #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
  3393. #define CAN_F7R1_FB29_Pos (29U)
  3394. #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
  3395. #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
  3396. #define CAN_F7R1_FB30_Pos (30U)
  3397. #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
  3398. #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
  3399. #define CAN_F7R1_FB31_Pos (31U)
  3400. #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
  3401. #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
  3402. /******************* Bit definition for CAN_F8R1 register *******************/
  3403. #define CAN_F8R1_FB0_Pos (0U)
  3404. #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
  3405. #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
  3406. #define CAN_F8R1_FB1_Pos (1U)
  3407. #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
  3408. #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
  3409. #define CAN_F8R1_FB2_Pos (2U)
  3410. #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
  3411. #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
  3412. #define CAN_F8R1_FB3_Pos (3U)
  3413. #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
  3414. #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
  3415. #define CAN_F8R1_FB4_Pos (4U)
  3416. #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
  3417. #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
  3418. #define CAN_F8R1_FB5_Pos (5U)
  3419. #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
  3420. #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
  3421. #define CAN_F8R1_FB6_Pos (6U)
  3422. #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
  3423. #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
  3424. #define CAN_F8R1_FB7_Pos (7U)
  3425. #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
  3426. #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
  3427. #define CAN_F8R1_FB8_Pos (8U)
  3428. #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
  3429. #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
  3430. #define CAN_F8R1_FB9_Pos (9U)
  3431. #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
  3432. #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
  3433. #define CAN_F8R1_FB10_Pos (10U)
  3434. #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
  3435. #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
  3436. #define CAN_F8R1_FB11_Pos (11U)
  3437. #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
  3438. #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
  3439. #define CAN_F8R1_FB12_Pos (12U)
  3440. #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
  3441. #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
  3442. #define CAN_F8R1_FB13_Pos (13U)
  3443. #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
  3444. #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
  3445. #define CAN_F8R1_FB14_Pos (14U)
  3446. #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
  3447. #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
  3448. #define CAN_F8R1_FB15_Pos (15U)
  3449. #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
  3450. #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
  3451. #define CAN_F8R1_FB16_Pos (16U)
  3452. #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
  3453. #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
  3454. #define CAN_F8R1_FB17_Pos (17U)
  3455. #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
  3456. #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
  3457. #define CAN_F8R1_FB18_Pos (18U)
  3458. #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
  3459. #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
  3460. #define CAN_F8R1_FB19_Pos (19U)
  3461. #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
  3462. #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
  3463. #define CAN_F8R1_FB20_Pos (20U)
  3464. #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
  3465. #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
  3466. #define CAN_F8R1_FB21_Pos (21U)
  3467. #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
  3468. #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
  3469. #define CAN_F8R1_FB22_Pos (22U)
  3470. #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
  3471. #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
  3472. #define CAN_F8R1_FB23_Pos (23U)
  3473. #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
  3474. #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
  3475. #define CAN_F8R1_FB24_Pos (24U)
  3476. #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
  3477. #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
  3478. #define CAN_F8R1_FB25_Pos (25U)
  3479. #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
  3480. #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
  3481. #define CAN_F8R1_FB26_Pos (26U)
  3482. #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
  3483. #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
  3484. #define CAN_F8R1_FB27_Pos (27U)
  3485. #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
  3486. #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
  3487. #define CAN_F8R1_FB28_Pos (28U)
  3488. #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
  3489. #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
  3490. #define CAN_F8R1_FB29_Pos (29U)
  3491. #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
  3492. #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
  3493. #define CAN_F8R1_FB30_Pos (30U)
  3494. #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
  3495. #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
  3496. #define CAN_F8R1_FB31_Pos (31U)
  3497. #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
  3498. #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
  3499. /******************* Bit definition for CAN_F9R1 register *******************/
  3500. #define CAN_F9R1_FB0_Pos (0U)
  3501. #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
  3502. #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
  3503. #define CAN_F9R1_FB1_Pos (1U)
  3504. #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
  3505. #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
  3506. #define CAN_F9R1_FB2_Pos (2U)
  3507. #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
  3508. #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
  3509. #define CAN_F9R1_FB3_Pos (3U)
  3510. #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
  3511. #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
  3512. #define CAN_F9R1_FB4_Pos (4U)
  3513. #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
  3514. #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
  3515. #define CAN_F9R1_FB5_Pos (5U)
  3516. #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
  3517. #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
  3518. #define CAN_F9R1_FB6_Pos (6U)
  3519. #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
  3520. #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
  3521. #define CAN_F9R1_FB7_Pos (7U)
  3522. #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
  3523. #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
  3524. #define CAN_F9R1_FB8_Pos (8U)
  3525. #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
  3526. #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
  3527. #define CAN_F9R1_FB9_Pos (9U)
  3528. #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
  3529. #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
  3530. #define CAN_F9R1_FB10_Pos (10U)
  3531. #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
  3532. #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
  3533. #define CAN_F9R1_FB11_Pos (11U)
  3534. #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
  3535. #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
  3536. #define CAN_F9R1_FB12_Pos (12U)
  3537. #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
  3538. #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
  3539. #define CAN_F9R1_FB13_Pos (13U)
  3540. #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
  3541. #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
  3542. #define CAN_F9R1_FB14_Pos (14U)
  3543. #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
  3544. #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
  3545. #define CAN_F9R1_FB15_Pos (15U)
  3546. #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
  3547. #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
  3548. #define CAN_F9R1_FB16_Pos (16U)
  3549. #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
  3550. #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
  3551. #define CAN_F9R1_FB17_Pos (17U)
  3552. #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
  3553. #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
  3554. #define CAN_F9R1_FB18_Pos (18U)
  3555. #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
  3556. #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
  3557. #define CAN_F9R1_FB19_Pos (19U)
  3558. #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
  3559. #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
  3560. #define CAN_F9R1_FB20_Pos (20U)
  3561. #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
  3562. #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
  3563. #define CAN_F9R1_FB21_Pos (21U)
  3564. #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
  3565. #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
  3566. #define CAN_F9R1_FB22_Pos (22U)
  3567. #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
  3568. #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
  3569. #define CAN_F9R1_FB23_Pos (23U)
  3570. #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
  3571. #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
  3572. #define CAN_F9R1_FB24_Pos (24U)
  3573. #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
  3574. #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
  3575. #define CAN_F9R1_FB25_Pos (25U)
  3576. #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
  3577. #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
  3578. #define CAN_F9R1_FB26_Pos (26U)
  3579. #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
  3580. #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
  3581. #define CAN_F9R1_FB27_Pos (27U)
  3582. #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
  3583. #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
  3584. #define CAN_F9R1_FB28_Pos (28U)
  3585. #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
  3586. #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
  3587. #define CAN_F9R1_FB29_Pos (29U)
  3588. #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
  3589. #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
  3590. #define CAN_F9R1_FB30_Pos (30U)
  3591. #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
  3592. #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
  3593. #define CAN_F9R1_FB31_Pos (31U)
  3594. #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
  3595. #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
  3596. /******************* Bit definition for CAN_F10R1 register ******************/
  3597. #define CAN_F10R1_FB0_Pos (0U)
  3598. #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
  3599. #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
  3600. #define CAN_F10R1_FB1_Pos (1U)
  3601. #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
  3602. #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
  3603. #define CAN_F10R1_FB2_Pos (2U)
  3604. #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
  3605. #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
  3606. #define CAN_F10R1_FB3_Pos (3U)
  3607. #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
  3608. #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
  3609. #define CAN_F10R1_FB4_Pos (4U)
  3610. #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
  3611. #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
  3612. #define CAN_F10R1_FB5_Pos (5U)
  3613. #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
  3614. #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
  3615. #define CAN_F10R1_FB6_Pos (6U)
  3616. #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
  3617. #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
  3618. #define CAN_F10R1_FB7_Pos (7U)
  3619. #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
  3620. #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
  3621. #define CAN_F10R1_FB8_Pos (8U)
  3622. #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
  3623. #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
  3624. #define CAN_F10R1_FB9_Pos (9U)
  3625. #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
  3626. #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
  3627. #define CAN_F10R1_FB10_Pos (10U)
  3628. #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
  3629. #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
  3630. #define CAN_F10R1_FB11_Pos (11U)
  3631. #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
  3632. #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
  3633. #define CAN_F10R1_FB12_Pos (12U)
  3634. #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
  3635. #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
  3636. #define CAN_F10R1_FB13_Pos (13U)
  3637. #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
  3638. #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
  3639. #define CAN_F10R1_FB14_Pos (14U)
  3640. #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
  3641. #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
  3642. #define CAN_F10R1_FB15_Pos (15U)
  3643. #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
  3644. #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
  3645. #define CAN_F10R1_FB16_Pos (16U)
  3646. #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
  3647. #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
  3648. #define CAN_F10R1_FB17_Pos (17U)
  3649. #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
  3650. #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
  3651. #define CAN_F10R1_FB18_Pos (18U)
  3652. #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
  3653. #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
  3654. #define CAN_F10R1_FB19_Pos (19U)
  3655. #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
  3656. #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
  3657. #define CAN_F10R1_FB20_Pos (20U)
  3658. #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
  3659. #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
  3660. #define CAN_F10R1_FB21_Pos (21U)
  3661. #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
  3662. #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
  3663. #define CAN_F10R1_FB22_Pos (22U)
  3664. #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
  3665. #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
  3666. #define CAN_F10R1_FB23_Pos (23U)
  3667. #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
  3668. #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
  3669. #define CAN_F10R1_FB24_Pos (24U)
  3670. #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
  3671. #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
  3672. #define CAN_F10R1_FB25_Pos (25U)
  3673. #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
  3674. #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
  3675. #define CAN_F10R1_FB26_Pos (26U)
  3676. #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
  3677. #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
  3678. #define CAN_F10R1_FB27_Pos (27U)
  3679. #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
  3680. #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
  3681. #define CAN_F10R1_FB28_Pos (28U)
  3682. #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
  3683. #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
  3684. #define CAN_F10R1_FB29_Pos (29U)
  3685. #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
  3686. #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
  3687. #define CAN_F10R1_FB30_Pos (30U)
  3688. #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
  3689. #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
  3690. #define CAN_F10R1_FB31_Pos (31U)
  3691. #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
  3692. #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
  3693. /******************* Bit definition for CAN_F11R1 register ******************/
  3694. #define CAN_F11R1_FB0_Pos (0U)
  3695. #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
  3696. #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
  3697. #define CAN_F11R1_FB1_Pos (1U)
  3698. #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
  3699. #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
  3700. #define CAN_F11R1_FB2_Pos (2U)
  3701. #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
  3702. #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
  3703. #define CAN_F11R1_FB3_Pos (3U)
  3704. #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
  3705. #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
  3706. #define CAN_F11R1_FB4_Pos (4U)
  3707. #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
  3708. #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
  3709. #define CAN_F11R1_FB5_Pos (5U)
  3710. #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
  3711. #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
  3712. #define CAN_F11R1_FB6_Pos (6U)
  3713. #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
  3714. #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
  3715. #define CAN_F11R1_FB7_Pos (7U)
  3716. #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
  3717. #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
  3718. #define CAN_F11R1_FB8_Pos (8U)
  3719. #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
  3720. #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
  3721. #define CAN_F11R1_FB9_Pos (9U)
  3722. #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
  3723. #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
  3724. #define CAN_F11R1_FB10_Pos (10U)
  3725. #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
  3726. #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
  3727. #define CAN_F11R1_FB11_Pos (11U)
  3728. #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
  3729. #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
  3730. #define CAN_F11R1_FB12_Pos (12U)
  3731. #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
  3732. #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
  3733. #define CAN_F11R1_FB13_Pos (13U)
  3734. #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
  3735. #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
  3736. #define CAN_F11R1_FB14_Pos (14U)
  3737. #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
  3738. #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
  3739. #define CAN_F11R1_FB15_Pos (15U)
  3740. #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
  3741. #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
  3742. #define CAN_F11R1_FB16_Pos (16U)
  3743. #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
  3744. #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
  3745. #define CAN_F11R1_FB17_Pos (17U)
  3746. #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
  3747. #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
  3748. #define CAN_F11R1_FB18_Pos (18U)
  3749. #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
  3750. #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
  3751. #define CAN_F11R1_FB19_Pos (19U)
  3752. #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
  3753. #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
  3754. #define CAN_F11R1_FB20_Pos (20U)
  3755. #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
  3756. #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
  3757. #define CAN_F11R1_FB21_Pos (21U)
  3758. #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
  3759. #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
  3760. #define CAN_F11R1_FB22_Pos (22U)
  3761. #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
  3762. #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
  3763. #define CAN_F11R1_FB23_Pos (23U)
  3764. #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
  3765. #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
  3766. #define CAN_F11R1_FB24_Pos (24U)
  3767. #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
  3768. #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
  3769. #define CAN_F11R1_FB25_Pos (25U)
  3770. #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
  3771. #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
  3772. #define CAN_F11R1_FB26_Pos (26U)
  3773. #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
  3774. #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
  3775. #define CAN_F11R1_FB27_Pos (27U)
  3776. #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
  3777. #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
  3778. #define CAN_F11R1_FB28_Pos (28U)
  3779. #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
  3780. #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
  3781. #define CAN_F11R1_FB29_Pos (29U)
  3782. #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
  3783. #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
  3784. #define CAN_F11R1_FB30_Pos (30U)
  3785. #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
  3786. #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
  3787. #define CAN_F11R1_FB31_Pos (31U)
  3788. #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
  3789. #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
  3790. /******************* Bit definition for CAN_F12R1 register ******************/
  3791. #define CAN_F12R1_FB0_Pos (0U)
  3792. #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
  3793. #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
  3794. #define CAN_F12R1_FB1_Pos (1U)
  3795. #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
  3796. #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
  3797. #define CAN_F12R1_FB2_Pos (2U)
  3798. #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
  3799. #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
  3800. #define CAN_F12R1_FB3_Pos (3U)
  3801. #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
  3802. #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
  3803. #define CAN_F12R1_FB4_Pos (4U)
  3804. #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
  3805. #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
  3806. #define CAN_F12R1_FB5_Pos (5U)
  3807. #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
  3808. #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
  3809. #define CAN_F12R1_FB6_Pos (6U)
  3810. #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
  3811. #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
  3812. #define CAN_F12R1_FB7_Pos (7U)
  3813. #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
  3814. #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
  3815. #define CAN_F12R1_FB8_Pos (8U)
  3816. #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
  3817. #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
  3818. #define CAN_F12R1_FB9_Pos (9U)
  3819. #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
  3820. #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
  3821. #define CAN_F12R1_FB10_Pos (10U)
  3822. #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
  3823. #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
  3824. #define CAN_F12R1_FB11_Pos (11U)
  3825. #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
  3826. #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
  3827. #define CAN_F12R1_FB12_Pos (12U)
  3828. #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
  3829. #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
  3830. #define CAN_F12R1_FB13_Pos (13U)
  3831. #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
  3832. #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
  3833. #define CAN_F12R1_FB14_Pos (14U)
  3834. #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
  3835. #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
  3836. #define CAN_F12R1_FB15_Pos (15U)
  3837. #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
  3838. #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
  3839. #define CAN_F12R1_FB16_Pos (16U)
  3840. #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
  3841. #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
  3842. #define CAN_F12R1_FB17_Pos (17U)
  3843. #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
  3844. #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
  3845. #define CAN_F12R1_FB18_Pos (18U)
  3846. #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
  3847. #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
  3848. #define CAN_F12R1_FB19_Pos (19U)
  3849. #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
  3850. #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
  3851. #define CAN_F12R1_FB20_Pos (20U)
  3852. #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
  3853. #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
  3854. #define CAN_F12R1_FB21_Pos (21U)
  3855. #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
  3856. #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
  3857. #define CAN_F12R1_FB22_Pos (22U)
  3858. #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
  3859. #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
  3860. #define CAN_F12R1_FB23_Pos (23U)
  3861. #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
  3862. #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
  3863. #define CAN_F12R1_FB24_Pos (24U)
  3864. #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
  3865. #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
  3866. #define CAN_F12R1_FB25_Pos (25U)
  3867. #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
  3868. #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
  3869. #define CAN_F12R1_FB26_Pos (26U)
  3870. #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
  3871. #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
  3872. #define CAN_F12R1_FB27_Pos (27U)
  3873. #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
  3874. #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
  3875. #define CAN_F12R1_FB28_Pos (28U)
  3876. #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
  3877. #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
  3878. #define CAN_F12R1_FB29_Pos (29U)
  3879. #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
  3880. #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
  3881. #define CAN_F12R1_FB30_Pos (30U)
  3882. #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
  3883. #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
  3884. #define CAN_F12R1_FB31_Pos (31U)
  3885. #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
  3886. #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
  3887. /******************* Bit definition for CAN_F13R1 register ******************/
  3888. #define CAN_F13R1_FB0_Pos (0U)
  3889. #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
  3890. #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
  3891. #define CAN_F13R1_FB1_Pos (1U)
  3892. #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
  3893. #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
  3894. #define CAN_F13R1_FB2_Pos (2U)
  3895. #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
  3896. #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
  3897. #define CAN_F13R1_FB3_Pos (3U)
  3898. #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
  3899. #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
  3900. #define CAN_F13R1_FB4_Pos (4U)
  3901. #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
  3902. #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
  3903. #define CAN_F13R1_FB5_Pos (5U)
  3904. #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
  3905. #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
  3906. #define CAN_F13R1_FB6_Pos (6U)
  3907. #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
  3908. #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
  3909. #define CAN_F13R1_FB7_Pos (7U)
  3910. #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
  3911. #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
  3912. #define CAN_F13R1_FB8_Pos (8U)
  3913. #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
  3914. #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
  3915. #define CAN_F13R1_FB9_Pos (9U)
  3916. #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
  3917. #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
  3918. #define CAN_F13R1_FB10_Pos (10U)
  3919. #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
  3920. #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
  3921. #define CAN_F13R1_FB11_Pos (11U)
  3922. #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
  3923. #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
  3924. #define CAN_F13R1_FB12_Pos (12U)
  3925. #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
  3926. #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
  3927. #define CAN_F13R1_FB13_Pos (13U)
  3928. #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
  3929. #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
  3930. #define CAN_F13R1_FB14_Pos (14U)
  3931. #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
  3932. #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
  3933. #define CAN_F13R1_FB15_Pos (15U)
  3934. #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
  3935. #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
  3936. #define CAN_F13R1_FB16_Pos (16U)
  3937. #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
  3938. #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
  3939. #define CAN_F13R1_FB17_Pos (17U)
  3940. #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
  3941. #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
  3942. #define CAN_F13R1_FB18_Pos (18U)
  3943. #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
  3944. #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
  3945. #define CAN_F13R1_FB19_Pos (19U)
  3946. #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
  3947. #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
  3948. #define CAN_F13R1_FB20_Pos (20U)
  3949. #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
  3950. #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
  3951. #define CAN_F13R1_FB21_Pos (21U)
  3952. #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
  3953. #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
  3954. #define CAN_F13R1_FB22_Pos (22U)
  3955. #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
  3956. #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
  3957. #define CAN_F13R1_FB23_Pos (23U)
  3958. #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
  3959. #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
  3960. #define CAN_F13R1_FB24_Pos (24U)
  3961. #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
  3962. #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
  3963. #define CAN_F13R1_FB25_Pos (25U)
  3964. #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
  3965. #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
  3966. #define CAN_F13R1_FB26_Pos (26U)
  3967. #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
  3968. #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
  3969. #define CAN_F13R1_FB27_Pos (27U)
  3970. #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
  3971. #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
  3972. #define CAN_F13R1_FB28_Pos (28U)
  3973. #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
  3974. #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
  3975. #define CAN_F13R1_FB29_Pos (29U)
  3976. #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
  3977. #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
  3978. #define CAN_F13R1_FB30_Pos (30U)
  3979. #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
  3980. #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
  3981. #define CAN_F13R1_FB31_Pos (31U)
  3982. #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
  3983. #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
  3984. /******************* Bit definition for CAN_F0R2 register *******************/
  3985. #define CAN_F0R2_FB0_Pos (0U)
  3986. #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
  3987. #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
  3988. #define CAN_F0R2_FB1_Pos (1U)
  3989. #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
  3990. #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
  3991. #define CAN_F0R2_FB2_Pos (2U)
  3992. #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
  3993. #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
  3994. #define CAN_F0R2_FB3_Pos (3U)
  3995. #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
  3996. #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
  3997. #define CAN_F0R2_FB4_Pos (4U)
  3998. #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
  3999. #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
  4000. #define CAN_F0R2_FB5_Pos (5U)
  4001. #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
  4002. #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
  4003. #define CAN_F0R2_FB6_Pos (6U)
  4004. #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
  4005. #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
  4006. #define CAN_F0R2_FB7_Pos (7U)
  4007. #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
  4008. #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
  4009. #define CAN_F0R2_FB8_Pos (8U)
  4010. #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
  4011. #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
  4012. #define CAN_F0R2_FB9_Pos (9U)
  4013. #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
  4014. #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
  4015. #define CAN_F0R2_FB10_Pos (10U)
  4016. #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
  4017. #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
  4018. #define CAN_F0R2_FB11_Pos (11U)
  4019. #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
  4020. #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
  4021. #define CAN_F0R2_FB12_Pos (12U)
  4022. #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
  4023. #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
  4024. #define CAN_F0R2_FB13_Pos (13U)
  4025. #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
  4026. #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
  4027. #define CAN_F0R2_FB14_Pos (14U)
  4028. #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
  4029. #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
  4030. #define CAN_F0R2_FB15_Pos (15U)
  4031. #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
  4032. #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
  4033. #define CAN_F0R2_FB16_Pos (16U)
  4034. #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
  4035. #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
  4036. #define CAN_F0R2_FB17_Pos (17U)
  4037. #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
  4038. #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
  4039. #define CAN_F0R2_FB18_Pos (18U)
  4040. #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
  4041. #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
  4042. #define CAN_F0R2_FB19_Pos (19U)
  4043. #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
  4044. #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
  4045. #define CAN_F0R2_FB20_Pos (20U)
  4046. #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
  4047. #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
  4048. #define CAN_F0R2_FB21_Pos (21U)
  4049. #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
  4050. #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
  4051. #define CAN_F0R2_FB22_Pos (22U)
  4052. #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
  4053. #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
  4054. #define CAN_F0R2_FB23_Pos (23U)
  4055. #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
  4056. #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
  4057. #define CAN_F0R2_FB24_Pos (24U)
  4058. #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
  4059. #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
  4060. #define CAN_F0R2_FB25_Pos (25U)
  4061. #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
  4062. #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
  4063. #define CAN_F0R2_FB26_Pos (26U)
  4064. #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
  4065. #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
  4066. #define CAN_F0R2_FB27_Pos (27U)
  4067. #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
  4068. #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
  4069. #define CAN_F0R2_FB28_Pos (28U)
  4070. #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
  4071. #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
  4072. #define CAN_F0R2_FB29_Pos (29U)
  4073. #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
  4074. #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
  4075. #define CAN_F0R2_FB30_Pos (30U)
  4076. #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
  4077. #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
  4078. #define CAN_F0R2_FB31_Pos (31U)
  4079. #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
  4080. #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
  4081. /******************* Bit definition for CAN_F1R2 register *******************/
  4082. #define CAN_F1R2_FB0_Pos (0U)
  4083. #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
  4084. #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
  4085. #define CAN_F1R2_FB1_Pos (1U)
  4086. #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
  4087. #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
  4088. #define CAN_F1R2_FB2_Pos (2U)
  4089. #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
  4090. #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
  4091. #define CAN_F1R2_FB3_Pos (3U)
  4092. #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
  4093. #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
  4094. #define CAN_F1R2_FB4_Pos (4U)
  4095. #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
  4096. #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
  4097. #define CAN_F1R2_FB5_Pos (5U)
  4098. #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
  4099. #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
  4100. #define CAN_F1R2_FB6_Pos (6U)
  4101. #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
  4102. #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
  4103. #define CAN_F1R2_FB7_Pos (7U)
  4104. #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
  4105. #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
  4106. #define CAN_F1R2_FB8_Pos (8U)
  4107. #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
  4108. #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
  4109. #define CAN_F1R2_FB9_Pos (9U)
  4110. #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
  4111. #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
  4112. #define CAN_F1R2_FB10_Pos (10U)
  4113. #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
  4114. #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
  4115. #define CAN_F1R2_FB11_Pos (11U)
  4116. #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
  4117. #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
  4118. #define CAN_F1R2_FB12_Pos (12U)
  4119. #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
  4120. #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
  4121. #define CAN_F1R2_FB13_Pos (13U)
  4122. #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
  4123. #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
  4124. #define CAN_F1R2_FB14_Pos (14U)
  4125. #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
  4126. #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
  4127. #define CAN_F1R2_FB15_Pos (15U)
  4128. #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
  4129. #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
  4130. #define CAN_F1R2_FB16_Pos (16U)
  4131. #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
  4132. #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
  4133. #define CAN_F1R2_FB17_Pos (17U)
  4134. #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
  4135. #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
  4136. #define CAN_F1R2_FB18_Pos (18U)
  4137. #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
  4138. #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
  4139. #define CAN_F1R2_FB19_Pos (19U)
  4140. #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
  4141. #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
  4142. #define CAN_F1R2_FB20_Pos (20U)
  4143. #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
  4144. #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
  4145. #define CAN_F1R2_FB21_Pos (21U)
  4146. #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
  4147. #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
  4148. #define CAN_F1R2_FB22_Pos (22U)
  4149. #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
  4150. #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
  4151. #define CAN_F1R2_FB23_Pos (23U)
  4152. #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
  4153. #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
  4154. #define CAN_F1R2_FB24_Pos (24U)
  4155. #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
  4156. #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
  4157. #define CAN_F1R2_FB25_Pos (25U)
  4158. #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
  4159. #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
  4160. #define CAN_F1R2_FB26_Pos (26U)
  4161. #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
  4162. #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
  4163. #define CAN_F1R2_FB27_Pos (27U)
  4164. #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
  4165. #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
  4166. #define CAN_F1R2_FB28_Pos (28U)
  4167. #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
  4168. #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
  4169. #define CAN_F1R2_FB29_Pos (29U)
  4170. #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
  4171. #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
  4172. #define CAN_F1R2_FB30_Pos (30U)
  4173. #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
  4174. #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
  4175. #define CAN_F1R2_FB31_Pos (31U)
  4176. #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
  4177. #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
  4178. /******************* Bit definition for CAN_F2R2 register *******************/
  4179. #define CAN_F2R2_FB0_Pos (0U)
  4180. #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
  4181. #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
  4182. #define CAN_F2R2_FB1_Pos (1U)
  4183. #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
  4184. #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
  4185. #define CAN_F2R2_FB2_Pos (2U)
  4186. #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
  4187. #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
  4188. #define CAN_F2R2_FB3_Pos (3U)
  4189. #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
  4190. #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
  4191. #define CAN_F2R2_FB4_Pos (4U)
  4192. #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
  4193. #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
  4194. #define CAN_F2R2_FB5_Pos (5U)
  4195. #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
  4196. #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
  4197. #define CAN_F2R2_FB6_Pos (6U)
  4198. #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
  4199. #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
  4200. #define CAN_F2R2_FB7_Pos (7U)
  4201. #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
  4202. #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
  4203. #define CAN_F2R2_FB8_Pos (8U)
  4204. #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
  4205. #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
  4206. #define CAN_F2R2_FB9_Pos (9U)
  4207. #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
  4208. #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
  4209. #define CAN_F2R2_FB10_Pos (10U)
  4210. #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
  4211. #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
  4212. #define CAN_F2R2_FB11_Pos (11U)
  4213. #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
  4214. #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
  4215. #define CAN_F2R2_FB12_Pos (12U)
  4216. #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
  4217. #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
  4218. #define CAN_F2R2_FB13_Pos (13U)
  4219. #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
  4220. #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
  4221. #define CAN_F2R2_FB14_Pos (14U)
  4222. #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
  4223. #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
  4224. #define CAN_F2R2_FB15_Pos (15U)
  4225. #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
  4226. #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
  4227. #define CAN_F2R2_FB16_Pos (16U)
  4228. #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
  4229. #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
  4230. #define CAN_F2R2_FB17_Pos (17U)
  4231. #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
  4232. #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
  4233. #define CAN_F2R2_FB18_Pos (18U)
  4234. #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
  4235. #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
  4236. #define CAN_F2R2_FB19_Pos (19U)
  4237. #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
  4238. #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
  4239. #define CAN_F2R2_FB20_Pos (20U)
  4240. #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
  4241. #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
  4242. #define CAN_F2R2_FB21_Pos (21U)
  4243. #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
  4244. #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
  4245. #define CAN_F2R2_FB22_Pos (22U)
  4246. #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
  4247. #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
  4248. #define CAN_F2R2_FB23_Pos (23U)
  4249. #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
  4250. #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
  4251. #define CAN_F2R2_FB24_Pos (24U)
  4252. #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
  4253. #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
  4254. #define CAN_F2R2_FB25_Pos (25U)
  4255. #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
  4256. #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
  4257. #define CAN_F2R2_FB26_Pos (26U)
  4258. #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
  4259. #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
  4260. #define CAN_F2R2_FB27_Pos (27U)
  4261. #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
  4262. #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
  4263. #define CAN_F2R2_FB28_Pos (28U)
  4264. #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
  4265. #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
  4266. #define CAN_F2R2_FB29_Pos (29U)
  4267. #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
  4268. #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
  4269. #define CAN_F2R2_FB30_Pos (30U)
  4270. #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
  4271. #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
  4272. #define CAN_F2R2_FB31_Pos (31U)
  4273. #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
  4274. #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
  4275. /******************* Bit definition for CAN_F3R2 register *******************/
  4276. #define CAN_F3R2_FB0_Pos (0U)
  4277. #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
  4278. #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
  4279. #define CAN_F3R2_FB1_Pos (1U)
  4280. #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
  4281. #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
  4282. #define CAN_F3R2_FB2_Pos (2U)
  4283. #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
  4284. #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
  4285. #define CAN_F3R2_FB3_Pos (3U)
  4286. #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
  4287. #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
  4288. #define CAN_F3R2_FB4_Pos (4U)
  4289. #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
  4290. #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
  4291. #define CAN_F3R2_FB5_Pos (5U)
  4292. #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
  4293. #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
  4294. #define CAN_F3R2_FB6_Pos (6U)
  4295. #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
  4296. #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
  4297. #define CAN_F3R2_FB7_Pos (7U)
  4298. #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
  4299. #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
  4300. #define CAN_F3R2_FB8_Pos (8U)
  4301. #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
  4302. #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
  4303. #define CAN_F3R2_FB9_Pos (9U)
  4304. #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
  4305. #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
  4306. #define CAN_F3R2_FB10_Pos (10U)
  4307. #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
  4308. #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
  4309. #define CAN_F3R2_FB11_Pos (11U)
  4310. #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
  4311. #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
  4312. #define CAN_F3R2_FB12_Pos (12U)
  4313. #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
  4314. #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
  4315. #define CAN_F3R2_FB13_Pos (13U)
  4316. #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
  4317. #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
  4318. #define CAN_F3R2_FB14_Pos (14U)
  4319. #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
  4320. #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
  4321. #define CAN_F3R2_FB15_Pos (15U)
  4322. #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
  4323. #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
  4324. #define CAN_F3R2_FB16_Pos (16U)
  4325. #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
  4326. #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
  4327. #define CAN_F3R2_FB17_Pos (17U)
  4328. #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
  4329. #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
  4330. #define CAN_F3R2_FB18_Pos (18U)
  4331. #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
  4332. #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
  4333. #define CAN_F3R2_FB19_Pos (19U)
  4334. #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
  4335. #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
  4336. #define CAN_F3R2_FB20_Pos (20U)
  4337. #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
  4338. #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
  4339. #define CAN_F3R2_FB21_Pos (21U)
  4340. #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
  4341. #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
  4342. #define CAN_F3R2_FB22_Pos (22U)
  4343. #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
  4344. #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
  4345. #define CAN_F3R2_FB23_Pos (23U)
  4346. #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
  4347. #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
  4348. #define CAN_F3R2_FB24_Pos (24U)
  4349. #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
  4350. #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
  4351. #define CAN_F3R2_FB25_Pos (25U)
  4352. #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
  4353. #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
  4354. #define CAN_F3R2_FB26_Pos (26U)
  4355. #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
  4356. #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
  4357. #define CAN_F3R2_FB27_Pos (27U)
  4358. #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
  4359. #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
  4360. #define CAN_F3R2_FB28_Pos (28U)
  4361. #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
  4362. #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
  4363. #define CAN_F3R2_FB29_Pos (29U)
  4364. #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
  4365. #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
  4366. #define CAN_F3R2_FB30_Pos (30U)
  4367. #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
  4368. #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
  4369. #define CAN_F3R2_FB31_Pos (31U)
  4370. #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
  4371. #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
  4372. /******************* Bit definition for CAN_F4R2 register *******************/
  4373. #define CAN_F4R2_FB0_Pos (0U)
  4374. #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
  4375. #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
  4376. #define CAN_F4R2_FB1_Pos (1U)
  4377. #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
  4378. #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
  4379. #define CAN_F4R2_FB2_Pos (2U)
  4380. #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
  4381. #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
  4382. #define CAN_F4R2_FB3_Pos (3U)
  4383. #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
  4384. #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
  4385. #define CAN_F4R2_FB4_Pos (4U)
  4386. #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
  4387. #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
  4388. #define CAN_F4R2_FB5_Pos (5U)
  4389. #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
  4390. #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
  4391. #define CAN_F4R2_FB6_Pos (6U)
  4392. #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
  4393. #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
  4394. #define CAN_F4R2_FB7_Pos (7U)
  4395. #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
  4396. #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
  4397. #define CAN_F4R2_FB8_Pos (8U)
  4398. #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
  4399. #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
  4400. #define CAN_F4R2_FB9_Pos (9U)
  4401. #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
  4402. #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
  4403. #define CAN_F4R2_FB10_Pos (10U)
  4404. #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
  4405. #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
  4406. #define CAN_F4R2_FB11_Pos (11U)
  4407. #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
  4408. #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
  4409. #define CAN_F4R2_FB12_Pos (12U)
  4410. #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
  4411. #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
  4412. #define CAN_F4R2_FB13_Pos (13U)
  4413. #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
  4414. #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
  4415. #define CAN_F4R2_FB14_Pos (14U)
  4416. #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
  4417. #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
  4418. #define CAN_F4R2_FB15_Pos (15U)
  4419. #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
  4420. #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
  4421. #define CAN_F4R2_FB16_Pos (16U)
  4422. #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
  4423. #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
  4424. #define CAN_F4R2_FB17_Pos (17U)
  4425. #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
  4426. #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
  4427. #define CAN_F4R2_FB18_Pos (18U)
  4428. #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
  4429. #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
  4430. #define CAN_F4R2_FB19_Pos (19U)
  4431. #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
  4432. #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
  4433. #define CAN_F4R2_FB20_Pos (20U)
  4434. #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
  4435. #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
  4436. #define CAN_F4R2_FB21_Pos (21U)
  4437. #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
  4438. #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
  4439. #define CAN_F4R2_FB22_Pos (22U)
  4440. #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
  4441. #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
  4442. #define CAN_F4R2_FB23_Pos (23U)
  4443. #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
  4444. #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
  4445. #define CAN_F4R2_FB24_Pos (24U)
  4446. #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
  4447. #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
  4448. #define CAN_F4R2_FB25_Pos (25U)
  4449. #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
  4450. #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
  4451. #define CAN_F4R2_FB26_Pos (26U)
  4452. #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
  4453. #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
  4454. #define CAN_F4R2_FB27_Pos (27U)
  4455. #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
  4456. #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
  4457. #define CAN_F4R2_FB28_Pos (28U)
  4458. #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
  4459. #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
  4460. #define CAN_F4R2_FB29_Pos (29U)
  4461. #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
  4462. #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
  4463. #define CAN_F4R2_FB30_Pos (30U)
  4464. #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
  4465. #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
  4466. #define CAN_F4R2_FB31_Pos (31U)
  4467. #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
  4468. #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
  4469. /******************* Bit definition for CAN_F5R2 register *******************/
  4470. #define CAN_F5R2_FB0_Pos (0U)
  4471. #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
  4472. #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
  4473. #define CAN_F5R2_FB1_Pos (1U)
  4474. #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
  4475. #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
  4476. #define CAN_F5R2_FB2_Pos (2U)
  4477. #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
  4478. #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
  4479. #define CAN_F5R2_FB3_Pos (3U)
  4480. #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
  4481. #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
  4482. #define CAN_F5R2_FB4_Pos (4U)
  4483. #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
  4484. #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
  4485. #define CAN_F5R2_FB5_Pos (5U)
  4486. #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
  4487. #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
  4488. #define CAN_F5R2_FB6_Pos (6U)
  4489. #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
  4490. #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
  4491. #define CAN_F5R2_FB7_Pos (7U)
  4492. #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
  4493. #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
  4494. #define CAN_F5R2_FB8_Pos (8U)
  4495. #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
  4496. #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
  4497. #define CAN_F5R2_FB9_Pos (9U)
  4498. #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
  4499. #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
  4500. #define CAN_F5R2_FB10_Pos (10U)
  4501. #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
  4502. #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
  4503. #define CAN_F5R2_FB11_Pos (11U)
  4504. #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
  4505. #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
  4506. #define CAN_F5R2_FB12_Pos (12U)
  4507. #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
  4508. #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
  4509. #define CAN_F5R2_FB13_Pos (13U)
  4510. #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
  4511. #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
  4512. #define CAN_F5R2_FB14_Pos (14U)
  4513. #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
  4514. #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
  4515. #define CAN_F5R2_FB15_Pos (15U)
  4516. #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
  4517. #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
  4518. #define CAN_F5R2_FB16_Pos (16U)
  4519. #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
  4520. #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
  4521. #define CAN_F5R2_FB17_Pos (17U)
  4522. #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
  4523. #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
  4524. #define CAN_F5R2_FB18_Pos (18U)
  4525. #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
  4526. #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
  4527. #define CAN_F5R2_FB19_Pos (19U)
  4528. #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
  4529. #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
  4530. #define CAN_F5R2_FB20_Pos (20U)
  4531. #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
  4532. #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
  4533. #define CAN_F5R2_FB21_Pos (21U)
  4534. #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
  4535. #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
  4536. #define CAN_F5R2_FB22_Pos (22U)
  4537. #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
  4538. #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
  4539. #define CAN_F5R2_FB23_Pos (23U)
  4540. #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
  4541. #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
  4542. #define CAN_F5R2_FB24_Pos (24U)
  4543. #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
  4544. #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
  4545. #define CAN_F5R2_FB25_Pos (25U)
  4546. #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
  4547. #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
  4548. #define CAN_F5R2_FB26_Pos (26U)
  4549. #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
  4550. #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
  4551. #define CAN_F5R2_FB27_Pos (27U)
  4552. #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
  4553. #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
  4554. #define CAN_F5R2_FB28_Pos (28U)
  4555. #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
  4556. #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
  4557. #define CAN_F5R2_FB29_Pos (29U)
  4558. #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
  4559. #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
  4560. #define CAN_F5R2_FB30_Pos (30U)
  4561. #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
  4562. #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
  4563. #define CAN_F5R2_FB31_Pos (31U)
  4564. #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
  4565. #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
  4566. /******************* Bit definition for CAN_F6R2 register *******************/
  4567. #define CAN_F6R2_FB0_Pos (0U)
  4568. #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
  4569. #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
  4570. #define CAN_F6R2_FB1_Pos (1U)
  4571. #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
  4572. #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
  4573. #define CAN_F6R2_FB2_Pos (2U)
  4574. #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
  4575. #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
  4576. #define CAN_F6R2_FB3_Pos (3U)
  4577. #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
  4578. #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
  4579. #define CAN_F6R2_FB4_Pos (4U)
  4580. #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
  4581. #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
  4582. #define CAN_F6R2_FB5_Pos (5U)
  4583. #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
  4584. #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
  4585. #define CAN_F6R2_FB6_Pos (6U)
  4586. #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
  4587. #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
  4588. #define CAN_F6R2_FB7_Pos (7U)
  4589. #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
  4590. #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
  4591. #define CAN_F6R2_FB8_Pos (8U)
  4592. #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
  4593. #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
  4594. #define CAN_F6R2_FB9_Pos (9U)
  4595. #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
  4596. #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
  4597. #define CAN_F6R2_FB10_Pos (10U)
  4598. #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
  4599. #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
  4600. #define CAN_F6R2_FB11_Pos (11U)
  4601. #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
  4602. #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
  4603. #define CAN_F6R2_FB12_Pos (12U)
  4604. #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
  4605. #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
  4606. #define CAN_F6R2_FB13_Pos (13U)
  4607. #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
  4608. #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
  4609. #define CAN_F6R2_FB14_Pos (14U)
  4610. #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
  4611. #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
  4612. #define CAN_F6R2_FB15_Pos (15U)
  4613. #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
  4614. #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
  4615. #define CAN_F6R2_FB16_Pos (16U)
  4616. #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
  4617. #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
  4618. #define CAN_F6R2_FB17_Pos (17U)
  4619. #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
  4620. #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
  4621. #define CAN_F6R2_FB18_Pos (18U)
  4622. #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
  4623. #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
  4624. #define CAN_F6R2_FB19_Pos (19U)
  4625. #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
  4626. #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
  4627. #define CAN_F6R2_FB20_Pos (20U)
  4628. #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
  4629. #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
  4630. #define CAN_F6R2_FB21_Pos (21U)
  4631. #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
  4632. #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
  4633. #define CAN_F6R2_FB22_Pos (22U)
  4634. #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
  4635. #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
  4636. #define CAN_F6R2_FB23_Pos (23U)
  4637. #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
  4638. #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
  4639. #define CAN_F6R2_FB24_Pos (24U)
  4640. #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
  4641. #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
  4642. #define CAN_F6R2_FB25_Pos (25U)
  4643. #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
  4644. #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
  4645. #define CAN_F6R2_FB26_Pos (26U)
  4646. #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
  4647. #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
  4648. #define CAN_F6R2_FB27_Pos (27U)
  4649. #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
  4650. #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
  4651. #define CAN_F6R2_FB28_Pos (28U)
  4652. #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
  4653. #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
  4654. #define CAN_F6R2_FB29_Pos (29U)
  4655. #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
  4656. #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
  4657. #define CAN_F6R2_FB30_Pos (30U)
  4658. #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
  4659. #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
  4660. #define CAN_F6R2_FB31_Pos (31U)
  4661. #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
  4662. #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
  4663. /******************* Bit definition for CAN_F7R2 register *******************/
  4664. #define CAN_F7R2_FB0_Pos (0U)
  4665. #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
  4666. #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
  4667. #define CAN_F7R2_FB1_Pos (1U)
  4668. #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
  4669. #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
  4670. #define CAN_F7R2_FB2_Pos (2U)
  4671. #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
  4672. #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
  4673. #define CAN_F7R2_FB3_Pos (3U)
  4674. #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
  4675. #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
  4676. #define CAN_F7R2_FB4_Pos (4U)
  4677. #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
  4678. #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
  4679. #define CAN_F7R2_FB5_Pos (5U)
  4680. #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
  4681. #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
  4682. #define CAN_F7R2_FB6_Pos (6U)
  4683. #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
  4684. #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
  4685. #define CAN_F7R2_FB7_Pos (7U)
  4686. #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
  4687. #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
  4688. #define CAN_F7R2_FB8_Pos (8U)
  4689. #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
  4690. #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
  4691. #define CAN_F7R2_FB9_Pos (9U)
  4692. #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
  4693. #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
  4694. #define CAN_F7R2_FB10_Pos (10U)
  4695. #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
  4696. #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
  4697. #define CAN_F7R2_FB11_Pos (11U)
  4698. #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
  4699. #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
  4700. #define CAN_F7R2_FB12_Pos (12U)
  4701. #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
  4702. #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
  4703. #define CAN_F7R2_FB13_Pos (13U)
  4704. #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
  4705. #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
  4706. #define CAN_F7R2_FB14_Pos (14U)
  4707. #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
  4708. #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
  4709. #define CAN_F7R2_FB15_Pos (15U)
  4710. #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
  4711. #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
  4712. #define CAN_F7R2_FB16_Pos (16U)
  4713. #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
  4714. #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
  4715. #define CAN_F7R2_FB17_Pos (17U)
  4716. #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
  4717. #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
  4718. #define CAN_F7R2_FB18_Pos (18U)
  4719. #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
  4720. #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
  4721. #define CAN_F7R2_FB19_Pos (19U)
  4722. #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
  4723. #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
  4724. #define CAN_F7R2_FB20_Pos (20U)
  4725. #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
  4726. #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
  4727. #define CAN_F7R2_FB21_Pos (21U)
  4728. #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
  4729. #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
  4730. #define CAN_F7R2_FB22_Pos (22U)
  4731. #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
  4732. #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
  4733. #define CAN_F7R2_FB23_Pos (23U)
  4734. #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
  4735. #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
  4736. #define CAN_F7R2_FB24_Pos (24U)
  4737. #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
  4738. #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
  4739. #define CAN_F7R2_FB25_Pos (25U)
  4740. #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
  4741. #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
  4742. #define CAN_F7R2_FB26_Pos (26U)
  4743. #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
  4744. #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
  4745. #define CAN_F7R2_FB27_Pos (27U)
  4746. #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
  4747. #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
  4748. #define CAN_F7R2_FB28_Pos (28U)
  4749. #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
  4750. #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
  4751. #define CAN_F7R2_FB29_Pos (29U)
  4752. #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
  4753. #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
  4754. #define CAN_F7R2_FB30_Pos (30U)
  4755. #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
  4756. #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
  4757. #define CAN_F7R2_FB31_Pos (31U)
  4758. #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
  4759. #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
  4760. /******************* Bit definition for CAN_F8R2 register *******************/
  4761. #define CAN_F8R2_FB0_Pos (0U)
  4762. #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
  4763. #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
  4764. #define CAN_F8R2_FB1_Pos (1U)
  4765. #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
  4766. #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
  4767. #define CAN_F8R2_FB2_Pos (2U)
  4768. #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
  4769. #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
  4770. #define CAN_F8R2_FB3_Pos (3U)
  4771. #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
  4772. #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
  4773. #define CAN_F8R2_FB4_Pos (4U)
  4774. #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
  4775. #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
  4776. #define CAN_F8R2_FB5_Pos (5U)
  4777. #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
  4778. #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
  4779. #define CAN_F8R2_FB6_Pos (6U)
  4780. #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
  4781. #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
  4782. #define CAN_F8R2_FB7_Pos (7U)
  4783. #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
  4784. #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
  4785. #define CAN_F8R2_FB8_Pos (8U)
  4786. #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
  4787. #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
  4788. #define CAN_F8R2_FB9_Pos (9U)
  4789. #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
  4790. #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
  4791. #define CAN_F8R2_FB10_Pos (10U)
  4792. #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
  4793. #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
  4794. #define CAN_F8R2_FB11_Pos (11U)
  4795. #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
  4796. #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
  4797. #define CAN_F8R2_FB12_Pos (12U)
  4798. #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
  4799. #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
  4800. #define CAN_F8R2_FB13_Pos (13U)
  4801. #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
  4802. #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
  4803. #define CAN_F8R2_FB14_Pos (14U)
  4804. #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
  4805. #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
  4806. #define CAN_F8R2_FB15_Pos (15U)
  4807. #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
  4808. #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
  4809. #define CAN_F8R2_FB16_Pos (16U)
  4810. #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
  4811. #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
  4812. #define CAN_F8R2_FB17_Pos (17U)
  4813. #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
  4814. #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
  4815. #define CAN_F8R2_FB18_Pos (18U)
  4816. #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
  4817. #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
  4818. #define CAN_F8R2_FB19_Pos (19U)
  4819. #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
  4820. #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
  4821. #define CAN_F8R2_FB20_Pos (20U)
  4822. #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
  4823. #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
  4824. #define CAN_F8R2_FB21_Pos (21U)
  4825. #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
  4826. #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
  4827. #define CAN_F8R2_FB22_Pos (22U)
  4828. #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
  4829. #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
  4830. #define CAN_F8R2_FB23_Pos (23U)
  4831. #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
  4832. #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
  4833. #define CAN_F8R2_FB24_Pos (24U)
  4834. #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
  4835. #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
  4836. #define CAN_F8R2_FB25_Pos (25U)
  4837. #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
  4838. #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
  4839. #define CAN_F8R2_FB26_Pos (26U)
  4840. #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
  4841. #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
  4842. #define CAN_F8R2_FB27_Pos (27U)
  4843. #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
  4844. #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
  4845. #define CAN_F8R2_FB28_Pos (28U)
  4846. #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
  4847. #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
  4848. #define CAN_F8R2_FB29_Pos (29U)
  4849. #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
  4850. #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
  4851. #define CAN_F8R2_FB30_Pos (30U)
  4852. #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
  4853. #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
  4854. #define CAN_F8R2_FB31_Pos (31U)
  4855. #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
  4856. #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
  4857. /******************* Bit definition for CAN_F9R2 register *******************/
  4858. #define CAN_F9R2_FB0_Pos (0U)
  4859. #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
  4860. #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
  4861. #define CAN_F9R2_FB1_Pos (1U)
  4862. #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
  4863. #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
  4864. #define CAN_F9R2_FB2_Pos (2U)
  4865. #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
  4866. #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
  4867. #define CAN_F9R2_FB3_Pos (3U)
  4868. #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
  4869. #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
  4870. #define CAN_F9R2_FB4_Pos (4U)
  4871. #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
  4872. #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
  4873. #define CAN_F9R2_FB5_Pos (5U)
  4874. #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
  4875. #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
  4876. #define CAN_F9R2_FB6_Pos (6U)
  4877. #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
  4878. #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
  4879. #define CAN_F9R2_FB7_Pos (7U)
  4880. #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
  4881. #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
  4882. #define CAN_F9R2_FB8_Pos (8U)
  4883. #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
  4884. #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
  4885. #define CAN_F9R2_FB9_Pos (9U)
  4886. #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
  4887. #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
  4888. #define CAN_F9R2_FB10_Pos (10U)
  4889. #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
  4890. #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
  4891. #define CAN_F9R2_FB11_Pos (11U)
  4892. #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
  4893. #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
  4894. #define CAN_F9R2_FB12_Pos (12U)
  4895. #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
  4896. #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
  4897. #define CAN_F9R2_FB13_Pos (13U)
  4898. #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
  4899. #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
  4900. #define CAN_F9R2_FB14_Pos (14U)
  4901. #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
  4902. #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
  4903. #define CAN_F9R2_FB15_Pos (15U)
  4904. #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
  4905. #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
  4906. #define CAN_F9R2_FB16_Pos (16U)
  4907. #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
  4908. #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
  4909. #define CAN_F9R2_FB17_Pos (17U)
  4910. #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
  4911. #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
  4912. #define CAN_F9R2_FB18_Pos (18U)
  4913. #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
  4914. #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
  4915. #define CAN_F9R2_FB19_Pos (19U)
  4916. #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
  4917. #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
  4918. #define CAN_F9R2_FB20_Pos (20U)
  4919. #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
  4920. #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
  4921. #define CAN_F9R2_FB21_Pos (21U)
  4922. #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
  4923. #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
  4924. #define CAN_F9R2_FB22_Pos (22U)
  4925. #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
  4926. #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
  4927. #define CAN_F9R2_FB23_Pos (23U)
  4928. #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
  4929. #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
  4930. #define CAN_F9R2_FB24_Pos (24U)
  4931. #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
  4932. #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
  4933. #define CAN_F9R2_FB25_Pos (25U)
  4934. #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
  4935. #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
  4936. #define CAN_F9R2_FB26_Pos (26U)
  4937. #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
  4938. #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
  4939. #define CAN_F9R2_FB27_Pos (27U)
  4940. #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
  4941. #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
  4942. #define CAN_F9R2_FB28_Pos (28U)
  4943. #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
  4944. #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
  4945. #define CAN_F9R2_FB29_Pos (29U)
  4946. #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
  4947. #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
  4948. #define CAN_F9R2_FB30_Pos (30U)
  4949. #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
  4950. #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
  4951. #define CAN_F9R2_FB31_Pos (31U)
  4952. #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
  4953. #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
  4954. /******************* Bit definition for CAN_F10R2 register ******************/
  4955. #define CAN_F10R2_FB0_Pos (0U)
  4956. #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
  4957. #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
  4958. #define CAN_F10R2_FB1_Pos (1U)
  4959. #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
  4960. #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
  4961. #define CAN_F10R2_FB2_Pos (2U)
  4962. #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
  4963. #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
  4964. #define CAN_F10R2_FB3_Pos (3U)
  4965. #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
  4966. #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
  4967. #define CAN_F10R2_FB4_Pos (4U)
  4968. #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
  4969. #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
  4970. #define CAN_F10R2_FB5_Pos (5U)
  4971. #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
  4972. #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
  4973. #define CAN_F10R2_FB6_Pos (6U)
  4974. #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
  4975. #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
  4976. #define CAN_F10R2_FB7_Pos (7U)
  4977. #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
  4978. #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
  4979. #define CAN_F10R2_FB8_Pos (8U)
  4980. #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
  4981. #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
  4982. #define CAN_F10R2_FB9_Pos (9U)
  4983. #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
  4984. #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
  4985. #define CAN_F10R2_FB10_Pos (10U)
  4986. #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
  4987. #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
  4988. #define CAN_F10R2_FB11_Pos (11U)
  4989. #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
  4990. #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
  4991. #define CAN_F10R2_FB12_Pos (12U)
  4992. #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
  4993. #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
  4994. #define CAN_F10R2_FB13_Pos (13U)
  4995. #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
  4996. #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
  4997. #define CAN_F10R2_FB14_Pos (14U)
  4998. #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
  4999. #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
  5000. #define CAN_F10R2_FB15_Pos (15U)
  5001. #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
  5002. #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
  5003. #define CAN_F10R2_FB16_Pos (16U)
  5004. #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
  5005. #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
  5006. #define CAN_F10R2_FB17_Pos (17U)
  5007. #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
  5008. #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
  5009. #define CAN_F10R2_FB18_Pos (18U)
  5010. #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
  5011. #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
  5012. #define CAN_F10R2_FB19_Pos (19U)
  5013. #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
  5014. #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
  5015. #define CAN_F10R2_FB20_Pos (20U)
  5016. #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
  5017. #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
  5018. #define CAN_F10R2_FB21_Pos (21U)
  5019. #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
  5020. #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
  5021. #define CAN_F10R2_FB22_Pos (22U)
  5022. #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
  5023. #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
  5024. #define CAN_F10R2_FB23_Pos (23U)
  5025. #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
  5026. #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
  5027. #define CAN_F10R2_FB24_Pos (24U)
  5028. #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
  5029. #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
  5030. #define CAN_F10R2_FB25_Pos (25U)
  5031. #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
  5032. #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
  5033. #define CAN_F10R2_FB26_Pos (26U)
  5034. #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
  5035. #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
  5036. #define CAN_F10R2_FB27_Pos (27U)
  5037. #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
  5038. #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
  5039. #define CAN_F10R2_FB28_Pos (28U)
  5040. #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
  5041. #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
  5042. #define CAN_F10R2_FB29_Pos (29U)
  5043. #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
  5044. #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
  5045. #define CAN_F10R2_FB30_Pos (30U)
  5046. #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
  5047. #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
  5048. #define CAN_F10R2_FB31_Pos (31U)
  5049. #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
  5050. #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
  5051. /******************* Bit definition for CAN_F11R2 register ******************/
  5052. #define CAN_F11R2_FB0_Pos (0U)
  5053. #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
  5054. #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
  5055. #define CAN_F11R2_FB1_Pos (1U)
  5056. #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
  5057. #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
  5058. #define CAN_F11R2_FB2_Pos (2U)
  5059. #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
  5060. #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
  5061. #define CAN_F11R2_FB3_Pos (3U)
  5062. #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
  5063. #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
  5064. #define CAN_F11R2_FB4_Pos (4U)
  5065. #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
  5066. #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
  5067. #define CAN_F11R2_FB5_Pos (5U)
  5068. #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
  5069. #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
  5070. #define CAN_F11R2_FB6_Pos (6U)
  5071. #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
  5072. #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
  5073. #define CAN_F11R2_FB7_Pos (7U)
  5074. #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
  5075. #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
  5076. #define CAN_F11R2_FB8_Pos (8U)
  5077. #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
  5078. #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
  5079. #define CAN_F11R2_FB9_Pos (9U)
  5080. #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
  5081. #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
  5082. #define CAN_F11R2_FB10_Pos (10U)
  5083. #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
  5084. #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
  5085. #define CAN_F11R2_FB11_Pos (11U)
  5086. #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
  5087. #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
  5088. #define CAN_F11R2_FB12_Pos (12U)
  5089. #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
  5090. #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
  5091. #define CAN_F11R2_FB13_Pos (13U)
  5092. #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
  5093. #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
  5094. #define CAN_F11R2_FB14_Pos (14U)
  5095. #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
  5096. #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
  5097. #define CAN_F11R2_FB15_Pos (15U)
  5098. #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
  5099. #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
  5100. #define CAN_F11R2_FB16_Pos (16U)
  5101. #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
  5102. #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
  5103. #define CAN_F11R2_FB17_Pos (17U)
  5104. #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
  5105. #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
  5106. #define CAN_F11R2_FB18_Pos (18U)
  5107. #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
  5108. #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
  5109. #define CAN_F11R2_FB19_Pos (19U)
  5110. #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
  5111. #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
  5112. #define CAN_F11R2_FB20_Pos (20U)
  5113. #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
  5114. #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
  5115. #define CAN_F11R2_FB21_Pos (21U)
  5116. #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
  5117. #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
  5118. #define CAN_F11R2_FB22_Pos (22U)
  5119. #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
  5120. #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
  5121. #define CAN_F11R2_FB23_Pos (23U)
  5122. #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
  5123. #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
  5124. #define CAN_F11R2_FB24_Pos (24U)
  5125. #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
  5126. #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
  5127. #define CAN_F11R2_FB25_Pos (25U)
  5128. #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
  5129. #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
  5130. #define CAN_F11R2_FB26_Pos (26U)
  5131. #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
  5132. #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
  5133. #define CAN_F11R2_FB27_Pos (27U)
  5134. #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
  5135. #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
  5136. #define CAN_F11R2_FB28_Pos (28U)
  5137. #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
  5138. #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
  5139. #define CAN_F11R2_FB29_Pos (29U)
  5140. #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
  5141. #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
  5142. #define CAN_F11R2_FB30_Pos (30U)
  5143. #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
  5144. #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
  5145. #define CAN_F11R2_FB31_Pos (31U)
  5146. #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
  5147. #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
  5148. /******************* Bit definition for CAN_F12R2 register ******************/
  5149. #define CAN_F12R2_FB0_Pos (0U)
  5150. #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
  5151. #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
  5152. #define CAN_F12R2_FB1_Pos (1U)
  5153. #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
  5154. #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
  5155. #define CAN_F12R2_FB2_Pos (2U)
  5156. #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
  5157. #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
  5158. #define CAN_F12R2_FB3_Pos (3U)
  5159. #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
  5160. #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
  5161. #define CAN_F12R2_FB4_Pos (4U)
  5162. #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
  5163. #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
  5164. #define CAN_F12R2_FB5_Pos (5U)
  5165. #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
  5166. #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
  5167. #define CAN_F12R2_FB6_Pos (6U)
  5168. #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
  5169. #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
  5170. #define CAN_F12R2_FB7_Pos (7U)
  5171. #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
  5172. #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
  5173. #define CAN_F12R2_FB8_Pos (8U)
  5174. #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
  5175. #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
  5176. #define CAN_F12R2_FB9_Pos (9U)
  5177. #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
  5178. #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
  5179. #define CAN_F12R2_FB10_Pos (10U)
  5180. #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
  5181. #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
  5182. #define CAN_F12R2_FB11_Pos (11U)
  5183. #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
  5184. #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
  5185. #define CAN_F12R2_FB12_Pos (12U)
  5186. #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
  5187. #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
  5188. #define CAN_F12R2_FB13_Pos (13U)
  5189. #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
  5190. #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
  5191. #define CAN_F12R2_FB14_Pos (14U)
  5192. #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
  5193. #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
  5194. #define CAN_F12R2_FB15_Pos (15U)
  5195. #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
  5196. #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
  5197. #define CAN_F12R2_FB16_Pos (16U)
  5198. #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
  5199. #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
  5200. #define CAN_F12R2_FB17_Pos (17U)
  5201. #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
  5202. #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
  5203. #define CAN_F12R2_FB18_Pos (18U)
  5204. #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
  5205. #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
  5206. #define CAN_F12R2_FB19_Pos (19U)
  5207. #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
  5208. #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
  5209. #define CAN_F12R2_FB20_Pos (20U)
  5210. #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
  5211. #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
  5212. #define CAN_F12R2_FB21_Pos (21U)
  5213. #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
  5214. #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
  5215. #define CAN_F12R2_FB22_Pos (22U)
  5216. #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
  5217. #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
  5218. #define CAN_F12R2_FB23_Pos (23U)
  5219. #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
  5220. #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
  5221. #define CAN_F12R2_FB24_Pos (24U)
  5222. #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
  5223. #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
  5224. #define CAN_F12R2_FB25_Pos (25U)
  5225. #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
  5226. #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
  5227. #define CAN_F12R2_FB26_Pos (26U)
  5228. #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
  5229. #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
  5230. #define CAN_F12R2_FB27_Pos (27U)
  5231. #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
  5232. #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
  5233. #define CAN_F12R2_FB28_Pos (28U)
  5234. #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
  5235. #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
  5236. #define CAN_F12R2_FB29_Pos (29U)
  5237. #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
  5238. #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
  5239. #define CAN_F12R2_FB30_Pos (30U)
  5240. #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
  5241. #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
  5242. #define CAN_F12R2_FB31_Pos (31U)
  5243. #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
  5244. #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
  5245. /******************* Bit definition for CAN_F13R2 register ******************/
  5246. #define CAN_F13R2_FB0_Pos (0U)
  5247. #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
  5248. #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
  5249. #define CAN_F13R2_FB1_Pos (1U)
  5250. #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
  5251. #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
  5252. #define CAN_F13R2_FB2_Pos (2U)
  5253. #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
  5254. #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
  5255. #define CAN_F13R2_FB3_Pos (3U)
  5256. #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
  5257. #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
  5258. #define CAN_F13R2_FB4_Pos (4U)
  5259. #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
  5260. #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
  5261. #define CAN_F13R2_FB5_Pos (5U)
  5262. #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
  5263. #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
  5264. #define CAN_F13R2_FB6_Pos (6U)
  5265. #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
  5266. #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
  5267. #define CAN_F13R2_FB7_Pos (7U)
  5268. #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
  5269. #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
  5270. #define CAN_F13R2_FB8_Pos (8U)
  5271. #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
  5272. #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
  5273. #define CAN_F13R2_FB9_Pos (9U)
  5274. #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
  5275. #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
  5276. #define CAN_F13R2_FB10_Pos (10U)
  5277. #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
  5278. #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
  5279. #define CAN_F13R2_FB11_Pos (11U)
  5280. #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
  5281. #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
  5282. #define CAN_F13R2_FB12_Pos (12U)
  5283. #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
  5284. #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
  5285. #define CAN_F13R2_FB13_Pos (13U)
  5286. #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
  5287. #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
  5288. #define CAN_F13R2_FB14_Pos (14U)
  5289. #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
  5290. #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
  5291. #define CAN_F13R2_FB15_Pos (15U)
  5292. #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
  5293. #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
  5294. #define CAN_F13R2_FB16_Pos (16U)
  5295. #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
  5296. #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
  5297. #define CAN_F13R2_FB17_Pos (17U)
  5298. #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
  5299. #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
  5300. #define CAN_F13R2_FB18_Pos (18U)
  5301. #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
  5302. #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
  5303. #define CAN_F13R2_FB19_Pos (19U)
  5304. #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
  5305. #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
  5306. #define CAN_F13R2_FB20_Pos (20U)
  5307. #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
  5308. #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
  5309. #define CAN_F13R2_FB21_Pos (21U)
  5310. #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
  5311. #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
  5312. #define CAN_F13R2_FB22_Pos (22U)
  5313. #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
  5314. #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
  5315. #define CAN_F13R2_FB23_Pos (23U)
  5316. #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
  5317. #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
  5318. #define CAN_F13R2_FB24_Pos (24U)
  5319. #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
  5320. #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
  5321. #define CAN_F13R2_FB25_Pos (25U)
  5322. #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
  5323. #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
  5324. #define CAN_F13R2_FB26_Pos (26U)
  5325. #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
  5326. #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
  5327. #define CAN_F13R2_FB27_Pos (27U)
  5328. #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
  5329. #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
  5330. #define CAN_F13R2_FB28_Pos (28U)
  5331. #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
  5332. #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
  5333. #define CAN_F13R2_FB29_Pos (29U)
  5334. #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
  5335. #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
  5336. #define CAN_F13R2_FB30_Pos (30U)
  5337. #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
  5338. #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
  5339. #define CAN_F13R2_FB31_Pos (31U)
  5340. #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
  5341. #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
  5342. /******************************************************************************/
  5343. /* */
  5344. /* CRC calculation unit */
  5345. /* */
  5346. /******************************************************************************/
  5347. /******************* Bit definition for CRC_DR register *********************/
  5348. #define CRC_DR_DR_Pos (0U)
  5349. #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
  5350. #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
  5351. /******************* Bit definition for CRC_IDR register ********************/
  5352. #define CRC_IDR_IDR_Pos (0U)
  5353. #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
  5354. #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
  5355. /******************** Bit definition for CRC_CR register ********************/
  5356. #define CRC_CR_RESET_Pos (0U)
  5357. #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
  5358. #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
  5359. #define CRC_CR_POLYSIZE_Pos (3U)
  5360. #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
  5361. #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
  5362. #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
  5363. #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
  5364. #define CRC_CR_REV_IN_Pos (5U)
  5365. #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
  5366. #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
  5367. #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
  5368. #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
  5369. #define CRC_CR_REV_OUT_Pos (7U)
  5370. #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
  5371. #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
  5372. /******************* Bit definition for CRC_INIT register *******************/
  5373. #define CRC_INIT_INIT_Pos (0U)
  5374. #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
  5375. #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
  5376. /******************* Bit definition for CRC_POL register ********************/
  5377. #define CRC_POL_POL_Pos (0U)
  5378. #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
  5379. #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
  5380. /******************************************************************************/
  5381. /* */
  5382. /* CRS Clock Recovery System */
  5383. /******************************************************************************/
  5384. /******************* Bit definition for CRS_CR register *********************/
  5385. #define CRS_CR_SYNCOKIE_Pos (0U)
  5386. #define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
  5387. #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
  5388. #define CRS_CR_SYNCWARNIE_Pos (1U)
  5389. #define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
  5390. #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
  5391. #define CRS_CR_ERRIE_Pos (2U)
  5392. #define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
  5393. #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
  5394. #define CRS_CR_ESYNCIE_Pos (3U)
  5395. #define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
  5396. #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
  5397. #define CRS_CR_CEN_Pos (5U)
  5398. #define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
  5399. #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
  5400. #define CRS_CR_AUTOTRIMEN_Pos (6U)
  5401. #define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
  5402. #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
  5403. #define CRS_CR_SWSYNC_Pos (7U)
  5404. #define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
  5405. #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
  5406. #define CRS_CR_TRIM_Pos (8U)
  5407. #define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
  5408. #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
  5409. /******************* Bit definition for CRS_CFGR register *********************/
  5410. #define CRS_CFGR_RELOAD_Pos (0U)
  5411. #define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
  5412. #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
  5413. #define CRS_CFGR_FELIM_Pos (16U)
  5414. #define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
  5415. #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
  5416. #define CRS_CFGR_SYNCDIV_Pos (24U)
  5417. #define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
  5418. #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
  5419. #define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
  5420. #define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
  5421. #define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
  5422. #define CRS_CFGR_SYNCSRC_Pos (28U)
  5423. #define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
  5424. #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
  5425. #define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
  5426. #define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
  5427. #define CRS_CFGR_SYNCPOL_Pos (31U)
  5428. #define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
  5429. #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
  5430. /******************* Bit definition for CRS_ISR register *********************/
  5431. #define CRS_ISR_SYNCOKF_Pos (0U)
  5432. #define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
  5433. #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
  5434. #define CRS_ISR_SYNCWARNF_Pos (1U)
  5435. #define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
  5436. #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
  5437. #define CRS_ISR_ERRF_Pos (2U)
  5438. #define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
  5439. #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
  5440. #define CRS_ISR_ESYNCF_Pos (3U)
  5441. #define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
  5442. #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
  5443. #define CRS_ISR_SYNCERR_Pos (8U)
  5444. #define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
  5445. #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
  5446. #define CRS_ISR_SYNCMISS_Pos (9U)
  5447. #define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
  5448. #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
  5449. #define CRS_ISR_TRIMOVF_Pos (10U)
  5450. #define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
  5451. #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
  5452. #define CRS_ISR_FEDIR_Pos (15U)
  5453. #define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
  5454. #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
  5455. #define CRS_ISR_FECAP_Pos (16U)
  5456. #define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
  5457. #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
  5458. /******************* Bit definition for CRS_ICR register *********************/
  5459. #define CRS_ICR_SYNCOKC_Pos (0U)
  5460. #define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
  5461. #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
  5462. #define CRS_ICR_SYNCWARNC_Pos (1U)
  5463. #define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
  5464. #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
  5465. #define CRS_ICR_ERRC_Pos (2U)
  5466. #define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
  5467. #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
  5468. #define CRS_ICR_ESYNCC_Pos (3U)
  5469. #define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
  5470. #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
  5471. /******************************************************************************/
  5472. /* */
  5473. /* Digital to Analog Converter */
  5474. /* */
  5475. /******************************************************************************/
  5476. /*
  5477. * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
  5478. */
  5479. #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
  5480. /******************** Bit definition for DAC_CR register ********************/
  5481. #define DAC_CR_EN1_Pos (0U)
  5482. #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
  5483. #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
  5484. #define DAC_CR_TEN1_Pos (2U)
  5485. #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
  5486. #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
  5487. #define DAC_CR_TSEL1_Pos (3U)
  5488. #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
  5489. #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
  5490. #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
  5491. #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
  5492. #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
  5493. #define DAC_CR_WAVE1_Pos (6U)
  5494. #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
  5495. #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
  5496. #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
  5497. #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
  5498. #define DAC_CR_MAMP1_Pos (8U)
  5499. #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
  5500. #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
  5501. #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
  5502. #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
  5503. #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
  5504. #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
  5505. #define DAC_CR_DMAEN1_Pos (12U)
  5506. #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
  5507. #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
  5508. #define DAC_CR_DMAUDRIE1_Pos (13U)
  5509. #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
  5510. #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
  5511. #define DAC_CR_CEN1_Pos (14U)
  5512. #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
  5513. #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
  5514. #define DAC_CR_EN2_Pos (16U)
  5515. #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
  5516. #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
  5517. #define DAC_CR_TEN2_Pos (18U)
  5518. #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
  5519. #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
  5520. #define DAC_CR_TSEL2_Pos (19U)
  5521. #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
  5522. #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
  5523. #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
  5524. #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
  5525. #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
  5526. #define DAC_CR_WAVE2_Pos (22U)
  5527. #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
  5528. #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
  5529. #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
  5530. #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
  5531. #define DAC_CR_MAMP2_Pos (24U)
  5532. #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
  5533. #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
  5534. #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
  5535. #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
  5536. #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
  5537. #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
  5538. #define DAC_CR_DMAEN2_Pos (28U)
  5539. #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
  5540. #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
  5541. #define DAC_CR_DMAUDRIE2_Pos (29U)
  5542. #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
  5543. #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
  5544. #define DAC_CR_CEN2_Pos (30U)
  5545. #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
  5546. #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
  5547. /***************** Bit definition for DAC_SWTRIGR register ******************/
  5548. #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
  5549. #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
  5550. #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
  5551. #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
  5552. #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
  5553. #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
  5554. /***************** Bit definition for DAC_DHR12R1 register ******************/
  5555. #define DAC_DHR12R1_DACC1DHR_Pos (0U)
  5556. #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
  5557. #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
  5558. /***************** Bit definition for DAC_DHR12L1 register ******************/
  5559. #define DAC_DHR12L1_DACC1DHR_Pos (4U)
  5560. #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
  5561. #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
  5562. /****************** Bit definition for DAC_DHR8R1 register ******************/
  5563. #define DAC_DHR8R1_DACC1DHR_Pos (0U)
  5564. #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
  5565. #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
  5566. /***************** Bit definition for DAC_DHR12R2 register ******************/
  5567. #define DAC_DHR12R2_DACC2DHR_Pos (0U)
  5568. #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
  5569. #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
  5570. /***************** Bit definition for DAC_DHR12L2 register ******************/
  5571. #define DAC_DHR12L2_DACC2DHR_Pos (4U)
  5572. #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
  5573. #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
  5574. /****************** Bit definition for DAC_DHR8R2 register ******************/
  5575. #define DAC_DHR8R2_DACC2DHR_Pos (0U)
  5576. #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
  5577. #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
  5578. /***************** Bit definition for DAC_DHR12RD register ******************/
  5579. #define DAC_DHR12RD_DACC1DHR_Pos (0U)
  5580. #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
  5581. #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
  5582. #define DAC_DHR12RD_DACC2DHR_Pos (16U)
  5583. #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
  5584. #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
  5585. /***************** Bit definition for DAC_DHR12LD register ******************/
  5586. #define DAC_DHR12LD_DACC1DHR_Pos (4U)
  5587. #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
  5588. #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
  5589. #define DAC_DHR12LD_DACC2DHR_Pos (20U)
  5590. #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
  5591. #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
  5592. /****************** Bit definition for DAC_DHR8RD register ******************/
  5593. #define DAC_DHR8RD_DACC1DHR_Pos (0U)
  5594. #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
  5595. #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
  5596. #define DAC_DHR8RD_DACC2DHR_Pos (8U)
  5597. #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
  5598. #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
  5599. /******************* Bit definition for DAC_DOR1 register *******************/
  5600. #define DAC_DOR1_DACC1DOR_Pos (0U)
  5601. #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
  5602. #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
  5603. /******************* Bit definition for DAC_DOR2 register *******************/
  5604. #define DAC_DOR2_DACC2DOR_Pos (0U)
  5605. #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
  5606. #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
  5607. /******************** Bit definition for DAC_SR register ********************/
  5608. #define DAC_SR_DMAUDR1_Pos (13U)
  5609. #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
  5610. #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
  5611. #define DAC_SR_CAL_FLAG1_Pos (14U)
  5612. #define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
  5613. #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
  5614. #define DAC_SR_BWST1_Pos (15U)
  5615. #define DAC_SR_BWST1_Msk (0x1U << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
  5616. #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
  5617. #define DAC_SR_DMAUDR2_Pos (29U)
  5618. #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
  5619. #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
  5620. #define DAC_SR_CAL_FLAG2_Pos (30U)
  5621. #define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
  5622. #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
  5623. #define DAC_SR_BWST2_Pos (31U)
  5624. #define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
  5625. #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
  5626. /******************* Bit definition for DAC_CCR register ********************/
  5627. #define DAC_CCR_OTRIM1_Pos (0U)
  5628. #define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
  5629. #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
  5630. #define DAC_CCR_OTRIM2_Pos (16U)
  5631. #define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
  5632. #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
  5633. /******************* Bit definition for DAC_MCR register *******************/
  5634. #define DAC_MCR_MODE1_Pos (0U)
  5635. #define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
  5636. #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
  5637. #define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
  5638. #define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
  5639. #define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
  5640. #define DAC_MCR_MODE2_Pos (16U)
  5641. #define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
  5642. #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
  5643. #define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
  5644. #define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
  5645. #define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
  5646. /****************** Bit definition for DAC_SHSR1 register ******************/
  5647. #define DAC_SHSR1_TSAMPLE1_Pos (0U)
  5648. #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
  5649. #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
  5650. /****************** Bit definition for DAC_SHSR2 register ******************/
  5651. #define DAC_SHSR2_TSAMPLE2_Pos (0U)
  5652. #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
  5653. #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
  5654. /****************** Bit definition for DAC_SHHR register ******************/
  5655. #define DAC_SHHR_THOLD1_Pos (0U)
  5656. #define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
  5657. #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
  5658. #define DAC_SHHR_THOLD2_Pos (16U)
  5659. #define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
  5660. #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
  5661. /****************** Bit definition for DAC_SHRR register ******************/
  5662. #define DAC_SHRR_TREFRESH1_Pos (0U)
  5663. #define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
  5664. #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
  5665. #define DAC_SHRR_TREFRESH2_Pos (16U)
  5666. #define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
  5667. #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
  5668. /******************************************************************************/
  5669. /* */
  5670. /* DMA Controller (DMA) */
  5671. /* */
  5672. /******************************************************************************/
  5673. /******************* Bit definition for DMA_ISR register ********************/
  5674. #define DMA_ISR_GIF1_Pos (0U)
  5675. #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
  5676. #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
  5677. #define DMA_ISR_TCIF1_Pos (1U)
  5678. #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
  5679. #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
  5680. #define DMA_ISR_HTIF1_Pos (2U)
  5681. #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
  5682. #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
  5683. #define DMA_ISR_TEIF1_Pos (3U)
  5684. #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
  5685. #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
  5686. #define DMA_ISR_GIF2_Pos (4U)
  5687. #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
  5688. #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
  5689. #define DMA_ISR_TCIF2_Pos (5U)
  5690. #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
  5691. #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
  5692. #define DMA_ISR_HTIF2_Pos (6U)
  5693. #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
  5694. #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
  5695. #define DMA_ISR_TEIF2_Pos (7U)
  5696. #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
  5697. #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
  5698. #define DMA_ISR_GIF3_Pos (8U)
  5699. #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
  5700. #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
  5701. #define DMA_ISR_TCIF3_Pos (9U)
  5702. #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
  5703. #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
  5704. #define DMA_ISR_HTIF3_Pos (10U)
  5705. #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
  5706. #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
  5707. #define DMA_ISR_TEIF3_Pos (11U)
  5708. #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
  5709. #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
  5710. #define DMA_ISR_GIF4_Pos (12U)
  5711. #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
  5712. #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
  5713. #define DMA_ISR_TCIF4_Pos (13U)
  5714. #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
  5715. #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
  5716. #define DMA_ISR_HTIF4_Pos (14U)
  5717. #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
  5718. #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
  5719. #define DMA_ISR_TEIF4_Pos (15U)
  5720. #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
  5721. #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
  5722. #define DMA_ISR_GIF5_Pos (16U)
  5723. #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
  5724. #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
  5725. #define DMA_ISR_TCIF5_Pos (17U)
  5726. #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
  5727. #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
  5728. #define DMA_ISR_HTIF5_Pos (18U)
  5729. #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
  5730. #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
  5731. #define DMA_ISR_TEIF5_Pos (19U)
  5732. #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
  5733. #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
  5734. #define DMA_ISR_GIF6_Pos (20U)
  5735. #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
  5736. #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
  5737. #define DMA_ISR_TCIF6_Pos (21U)
  5738. #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
  5739. #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
  5740. #define DMA_ISR_HTIF6_Pos (22U)
  5741. #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
  5742. #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
  5743. #define DMA_ISR_TEIF6_Pos (23U)
  5744. #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
  5745. #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
  5746. #define DMA_ISR_GIF7_Pos (24U)
  5747. #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
  5748. #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
  5749. #define DMA_ISR_TCIF7_Pos (25U)
  5750. #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
  5751. #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
  5752. #define DMA_ISR_HTIF7_Pos (26U)
  5753. #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
  5754. #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
  5755. #define DMA_ISR_TEIF7_Pos (27U)
  5756. #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
  5757. #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
  5758. /******************* Bit definition for DMA_IFCR register *******************/
  5759. #define DMA_IFCR_CGIF1_Pos (0U)
  5760. #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
  5761. #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
  5762. #define DMA_IFCR_CTCIF1_Pos (1U)
  5763. #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
  5764. #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
  5765. #define DMA_IFCR_CHTIF1_Pos (2U)
  5766. #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
  5767. #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
  5768. #define DMA_IFCR_CTEIF1_Pos (3U)
  5769. #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
  5770. #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
  5771. #define DMA_IFCR_CGIF2_Pos (4U)
  5772. #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
  5773. #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
  5774. #define DMA_IFCR_CTCIF2_Pos (5U)
  5775. #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
  5776. #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
  5777. #define DMA_IFCR_CHTIF2_Pos (6U)
  5778. #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
  5779. #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
  5780. #define DMA_IFCR_CTEIF2_Pos (7U)
  5781. #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
  5782. #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
  5783. #define DMA_IFCR_CGIF3_Pos (8U)
  5784. #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
  5785. #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
  5786. #define DMA_IFCR_CTCIF3_Pos (9U)
  5787. #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
  5788. #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
  5789. #define DMA_IFCR_CHTIF3_Pos (10U)
  5790. #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
  5791. #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
  5792. #define DMA_IFCR_CTEIF3_Pos (11U)
  5793. #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
  5794. #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
  5795. #define DMA_IFCR_CGIF4_Pos (12U)
  5796. #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
  5797. #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
  5798. #define DMA_IFCR_CTCIF4_Pos (13U)
  5799. #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
  5800. #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
  5801. #define DMA_IFCR_CHTIF4_Pos (14U)
  5802. #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
  5803. #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
  5804. #define DMA_IFCR_CTEIF4_Pos (15U)
  5805. #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
  5806. #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
  5807. #define DMA_IFCR_CGIF5_Pos (16U)
  5808. #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
  5809. #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
  5810. #define DMA_IFCR_CTCIF5_Pos (17U)
  5811. #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
  5812. #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
  5813. #define DMA_IFCR_CHTIF5_Pos (18U)
  5814. #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
  5815. #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
  5816. #define DMA_IFCR_CTEIF5_Pos (19U)
  5817. #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
  5818. #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
  5819. #define DMA_IFCR_CGIF6_Pos (20U)
  5820. #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
  5821. #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
  5822. #define DMA_IFCR_CTCIF6_Pos (21U)
  5823. #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
  5824. #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
  5825. #define DMA_IFCR_CHTIF6_Pos (22U)
  5826. #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
  5827. #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
  5828. #define DMA_IFCR_CTEIF6_Pos (23U)
  5829. #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
  5830. #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
  5831. #define DMA_IFCR_CGIF7_Pos (24U)
  5832. #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
  5833. #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
  5834. #define DMA_IFCR_CTCIF7_Pos (25U)
  5835. #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
  5836. #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
  5837. #define DMA_IFCR_CHTIF7_Pos (26U)
  5838. #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
  5839. #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
  5840. #define DMA_IFCR_CTEIF7_Pos (27U)
  5841. #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
  5842. #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
  5843. /******************* Bit definition for DMA_CCR register ********************/
  5844. #define DMA_CCR_EN_Pos (0U)
  5845. #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
  5846. #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
  5847. #define DMA_CCR_TCIE_Pos (1U)
  5848. #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
  5849. #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
  5850. #define DMA_CCR_HTIE_Pos (2U)
  5851. #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
  5852. #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
  5853. #define DMA_CCR_TEIE_Pos (3U)
  5854. #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
  5855. #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
  5856. #define DMA_CCR_DIR_Pos (4U)
  5857. #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
  5858. #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
  5859. #define DMA_CCR_CIRC_Pos (5U)
  5860. #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
  5861. #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
  5862. #define DMA_CCR_PINC_Pos (6U)
  5863. #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
  5864. #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
  5865. #define DMA_CCR_MINC_Pos (7U)
  5866. #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
  5867. #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
  5868. #define DMA_CCR_PSIZE_Pos (8U)
  5869. #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
  5870. #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
  5871. #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
  5872. #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
  5873. #define DMA_CCR_MSIZE_Pos (10U)
  5874. #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
  5875. #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
  5876. #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
  5877. #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
  5878. #define DMA_CCR_PL_Pos (12U)
  5879. #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
  5880. #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
  5881. #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
  5882. #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
  5883. #define DMA_CCR_MEM2MEM_Pos (14U)
  5884. #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
  5885. #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
  5886. /****************** Bit definition for DMA_CNDTR register *******************/
  5887. #define DMA_CNDTR_NDT_Pos (0U)
  5888. #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
  5889. #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
  5890. /****************** Bit definition for DMA_CPAR register ********************/
  5891. #define DMA_CPAR_PA_Pos (0U)
  5892. #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
  5893. #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
  5894. /****************** Bit definition for DMA_CMAR register ********************/
  5895. #define DMA_CMAR_MA_Pos (0U)
  5896. #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
  5897. #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
  5898. /******************* Bit definition for DMA_CSELR register *******************/
  5899. #define DMA_CSELR_C1S_Pos (0U)
  5900. #define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
  5901. #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
  5902. #define DMA_CSELR_C2S_Pos (4U)
  5903. #define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
  5904. #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
  5905. #define DMA_CSELR_C3S_Pos (8U)
  5906. #define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
  5907. #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
  5908. #define DMA_CSELR_C4S_Pos (12U)
  5909. #define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
  5910. #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
  5911. #define DMA_CSELR_C5S_Pos (16U)
  5912. #define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
  5913. #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
  5914. #define DMA_CSELR_C6S_Pos (20U)
  5915. #define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
  5916. #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
  5917. #define DMA_CSELR_C7S_Pos (24U)
  5918. #define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
  5919. #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
  5920. /******************************************************************************/
  5921. /* */
  5922. /* External Interrupt/Event Controller */
  5923. /* */
  5924. /******************************************************************************/
  5925. /******************* Bit definition for EXTI_IMR1 register ******************/
  5926. #define EXTI_IMR1_IM0_Pos (0U)
  5927. #define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
  5928. #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
  5929. #define EXTI_IMR1_IM1_Pos (1U)
  5930. #define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
  5931. #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
  5932. #define EXTI_IMR1_IM2_Pos (2U)
  5933. #define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
  5934. #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
  5935. #define EXTI_IMR1_IM3_Pos (3U)
  5936. #define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
  5937. #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
  5938. #define EXTI_IMR1_IM4_Pos (4U)
  5939. #define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
  5940. #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
  5941. #define EXTI_IMR1_IM5_Pos (5U)
  5942. #define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
  5943. #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
  5944. #define EXTI_IMR1_IM6_Pos (6U)
  5945. #define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
  5946. #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
  5947. #define EXTI_IMR1_IM7_Pos (7U)
  5948. #define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
  5949. #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
  5950. #define EXTI_IMR1_IM8_Pos (8U)
  5951. #define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
  5952. #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
  5953. #define EXTI_IMR1_IM9_Pos (9U)
  5954. #define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
  5955. #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
  5956. #define EXTI_IMR1_IM10_Pos (10U)
  5957. #define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
  5958. #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
  5959. #define EXTI_IMR1_IM11_Pos (11U)
  5960. #define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
  5961. #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
  5962. #define EXTI_IMR1_IM12_Pos (12U)
  5963. #define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
  5964. #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
  5965. #define EXTI_IMR1_IM13_Pos (13U)
  5966. #define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
  5967. #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
  5968. #define EXTI_IMR1_IM14_Pos (14U)
  5969. #define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
  5970. #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
  5971. #define EXTI_IMR1_IM15_Pos (15U)
  5972. #define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
  5973. #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
  5974. #define EXTI_IMR1_IM16_Pos (16U)
  5975. #define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
  5976. #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
  5977. #define EXTI_IMR1_IM17_Pos (17U)
  5978. #define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
  5979. #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
  5980. #define EXTI_IMR1_IM18_Pos (18U)
  5981. #define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
  5982. #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
  5983. #define EXTI_IMR1_IM19_Pos (19U)
  5984. #define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
  5985. #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
  5986. #define EXTI_IMR1_IM20_Pos (20U)
  5987. #define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
  5988. #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
  5989. #define EXTI_IMR1_IM21_Pos (21U)
  5990. #define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
  5991. #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
  5992. #define EXTI_IMR1_IM22_Pos (22U)
  5993. #define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
  5994. #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
  5995. #define EXTI_IMR1_IM23_Pos (23U)
  5996. #define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
  5997. #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
  5998. #define EXTI_IMR1_IM24_Pos (24U)
  5999. #define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
  6000. #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
  6001. #define EXTI_IMR1_IM25_Pos (25U)
  6002. #define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
  6003. #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
  6004. #define EXTI_IMR1_IM26_Pos (26U)
  6005. #define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
  6006. #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
  6007. #define EXTI_IMR1_IM27_Pos (27U)
  6008. #define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
  6009. #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
  6010. #define EXTI_IMR1_IM28_Pos (28U)
  6011. #define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
  6012. #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
  6013. #define EXTI_IMR1_IM31_Pos (31U)
  6014. #define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
  6015. #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
  6016. #define EXTI_IMR1_IM_Pos (0U)
  6017. #define EXTI_IMR1_IM_Msk (0x9FFFFFFFU << EXTI_IMR1_IM_Pos) /*!< 0x9FFFFFFF */
  6018. #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
  6019. /******************* Bit definition for EXTI_EMR1 register ******************/
  6020. #define EXTI_EMR1_EM0_Pos (0U)
  6021. #define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
  6022. #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
  6023. #define EXTI_EMR1_EM1_Pos (1U)
  6024. #define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
  6025. #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
  6026. #define EXTI_EMR1_EM2_Pos (2U)
  6027. #define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
  6028. #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
  6029. #define EXTI_EMR1_EM3_Pos (3U)
  6030. #define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
  6031. #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
  6032. #define EXTI_EMR1_EM4_Pos (4U)
  6033. #define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
  6034. #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
  6035. #define EXTI_EMR1_EM5_Pos (5U)
  6036. #define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
  6037. #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
  6038. #define EXTI_EMR1_EM6_Pos (6U)
  6039. #define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
  6040. #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
  6041. #define EXTI_EMR1_EM7_Pos (7U)
  6042. #define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
  6043. #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
  6044. #define EXTI_EMR1_EM8_Pos (8U)
  6045. #define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
  6046. #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
  6047. #define EXTI_EMR1_EM9_Pos (9U)
  6048. #define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
  6049. #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
  6050. #define EXTI_EMR1_EM10_Pos (10U)
  6051. #define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
  6052. #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
  6053. #define EXTI_EMR1_EM11_Pos (11U)
  6054. #define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
  6055. #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
  6056. #define EXTI_EMR1_EM12_Pos (12U)
  6057. #define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
  6058. #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
  6059. #define EXTI_EMR1_EM13_Pos (13U)
  6060. #define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
  6061. #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
  6062. #define EXTI_EMR1_EM14_Pos (14U)
  6063. #define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
  6064. #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
  6065. #define EXTI_EMR1_EM15_Pos (15U)
  6066. #define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
  6067. #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
  6068. #define EXTI_EMR1_EM16_Pos (16U)
  6069. #define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
  6070. #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
  6071. #define EXTI_EMR1_EM17_Pos (17U)
  6072. #define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
  6073. #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
  6074. #define EXTI_EMR1_EM18_Pos (18U)
  6075. #define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
  6076. #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
  6077. #define EXTI_EMR1_EM19_Pos (19U)
  6078. #define EXTI_EMR1_EM19_Msk (0x1U << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
  6079. #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
  6080. #define EXTI_EMR1_EM20_Pos (20U)
  6081. #define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
  6082. #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
  6083. #define EXTI_EMR1_EM21_Pos (21U)
  6084. #define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
  6085. #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
  6086. #define EXTI_EMR1_EM22_Pos (22U)
  6087. #define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
  6088. #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
  6089. #define EXTI_EMR1_EM23_Pos (23U)
  6090. #define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
  6091. #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
  6092. #define EXTI_EMR1_EM24_Pos (24U)
  6093. #define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
  6094. #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
  6095. #define EXTI_EMR1_EM25_Pos (25U)
  6096. #define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
  6097. #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
  6098. #define EXTI_EMR1_EM26_Pos (26U)
  6099. #define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
  6100. #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
  6101. #define EXTI_EMR1_EM27_Pos (27U)
  6102. #define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
  6103. #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
  6104. #define EXTI_EMR1_EM28_Pos (28U)
  6105. #define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
  6106. #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
  6107. #define EXTI_EMR1_EM31_Pos (31U)
  6108. #define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
  6109. #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
  6110. /****************** Bit definition for EXTI_RTSR1 register ******************/
  6111. #define EXTI_RTSR1_RT0_Pos (0U)
  6112. #define EXTI_RTSR1_RT0_Msk (0x1U << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
  6113. #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
  6114. #define EXTI_RTSR1_RT1_Pos (1U)
  6115. #define EXTI_RTSR1_RT1_Msk (0x1U << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
  6116. #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
  6117. #define EXTI_RTSR1_RT2_Pos (2U)
  6118. #define EXTI_RTSR1_RT2_Msk (0x1U << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
  6119. #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
  6120. #define EXTI_RTSR1_RT3_Pos (3U)
  6121. #define EXTI_RTSR1_RT3_Msk (0x1U << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
  6122. #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
  6123. #define EXTI_RTSR1_RT4_Pos (4U)
  6124. #define EXTI_RTSR1_RT4_Msk (0x1U << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
  6125. #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
  6126. #define EXTI_RTSR1_RT5_Pos (5U)
  6127. #define EXTI_RTSR1_RT5_Msk (0x1U << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
  6128. #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
  6129. #define EXTI_RTSR1_RT6_Pos (6U)
  6130. #define EXTI_RTSR1_RT6_Msk (0x1U << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
  6131. #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
  6132. #define EXTI_RTSR1_RT7_Pos (7U)
  6133. #define EXTI_RTSR1_RT7_Msk (0x1U << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
  6134. #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
  6135. #define EXTI_RTSR1_RT8_Pos (8U)
  6136. #define EXTI_RTSR1_RT8_Msk (0x1U << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
  6137. #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
  6138. #define EXTI_RTSR1_RT9_Pos (9U)
  6139. #define EXTI_RTSR1_RT9_Msk (0x1U << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
  6140. #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
  6141. #define EXTI_RTSR1_RT10_Pos (10U)
  6142. #define EXTI_RTSR1_RT10_Msk (0x1U << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
  6143. #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
  6144. #define EXTI_RTSR1_RT11_Pos (11U)
  6145. #define EXTI_RTSR1_RT11_Msk (0x1U << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
  6146. #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
  6147. #define EXTI_RTSR1_RT12_Pos (12U)
  6148. #define EXTI_RTSR1_RT12_Msk (0x1U << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
  6149. #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
  6150. #define EXTI_RTSR1_RT13_Pos (13U)
  6151. #define EXTI_RTSR1_RT13_Msk (0x1U << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
  6152. #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
  6153. #define EXTI_RTSR1_RT14_Pos (14U)
  6154. #define EXTI_RTSR1_RT14_Msk (0x1U << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
  6155. #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
  6156. #define EXTI_RTSR1_RT15_Pos (15U)
  6157. #define EXTI_RTSR1_RT15_Msk (0x1U << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
  6158. #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
  6159. #define EXTI_RTSR1_RT16_Pos (16U)
  6160. #define EXTI_RTSR1_RT16_Msk (0x1U << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
  6161. #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
  6162. #define EXTI_RTSR1_RT18_Pos (18U)
  6163. #define EXTI_RTSR1_RT18_Msk (0x1U << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
  6164. #define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
  6165. #define EXTI_RTSR1_RT19_Pos (19U)
  6166. #define EXTI_RTSR1_RT19_Msk (0x1U << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
  6167. #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
  6168. #define EXTI_RTSR1_RT20_Pos (20U)
  6169. #define EXTI_RTSR1_RT20_Msk (0x1U << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
  6170. #define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
  6171. #define EXTI_RTSR1_RT21_Pos (21U)
  6172. #define EXTI_RTSR1_RT21_Msk (0x1U << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
  6173. #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
  6174. #define EXTI_RTSR1_RT22_Pos (22U)
  6175. #define EXTI_RTSR1_RT22_Msk (0x1U << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
  6176. #define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
  6177. /****************** Bit definition for EXTI_FTSR1 register ******************/
  6178. #define EXTI_FTSR1_FT0_Pos (0U)
  6179. #define EXTI_FTSR1_FT0_Msk (0x1U << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
  6180. #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
  6181. #define EXTI_FTSR1_FT1_Pos (1U)
  6182. #define EXTI_FTSR1_FT1_Msk (0x1U << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
  6183. #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
  6184. #define EXTI_FTSR1_FT2_Pos (2U)
  6185. #define EXTI_FTSR1_FT2_Msk (0x1U << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
  6186. #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
  6187. #define EXTI_FTSR1_FT3_Pos (3U)
  6188. #define EXTI_FTSR1_FT3_Msk (0x1U << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
  6189. #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
  6190. #define EXTI_FTSR1_FT4_Pos (4U)
  6191. #define EXTI_FTSR1_FT4_Msk (0x1U << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
  6192. #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
  6193. #define EXTI_FTSR1_FT5_Pos (5U)
  6194. #define EXTI_FTSR1_FT5_Msk (0x1U << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
  6195. #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
  6196. #define EXTI_FTSR1_FT6_Pos (6U)
  6197. #define EXTI_FTSR1_FT6_Msk (0x1U << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
  6198. #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
  6199. #define EXTI_FTSR1_FT7_Pos (7U)
  6200. #define EXTI_FTSR1_FT7_Msk (0x1U << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
  6201. #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
  6202. #define EXTI_FTSR1_FT8_Pos (8U)
  6203. #define EXTI_FTSR1_FT8_Msk (0x1U << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
  6204. #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
  6205. #define EXTI_FTSR1_FT9_Pos (9U)
  6206. #define EXTI_FTSR1_FT9_Msk (0x1U << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
  6207. #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
  6208. #define EXTI_FTSR1_FT10_Pos (10U)
  6209. #define EXTI_FTSR1_FT10_Msk (0x1U << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
  6210. #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
  6211. #define EXTI_FTSR1_FT11_Pos (11U)
  6212. #define EXTI_FTSR1_FT11_Msk (0x1U << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
  6213. #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
  6214. #define EXTI_FTSR1_FT12_Pos (12U)
  6215. #define EXTI_FTSR1_FT12_Msk (0x1U << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
  6216. #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
  6217. #define EXTI_FTSR1_FT13_Pos (13U)
  6218. #define EXTI_FTSR1_FT13_Msk (0x1U << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
  6219. #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
  6220. #define EXTI_FTSR1_FT14_Pos (14U)
  6221. #define EXTI_FTSR1_FT14_Msk (0x1U << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
  6222. #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
  6223. #define EXTI_FTSR1_FT15_Pos (15U)
  6224. #define EXTI_FTSR1_FT15_Msk (0x1U << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
  6225. #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
  6226. #define EXTI_FTSR1_FT16_Pos (16U)
  6227. #define EXTI_FTSR1_FT16_Msk (0x1U << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
  6228. #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
  6229. #define EXTI_FTSR1_FT18_Pos (18U)
  6230. #define EXTI_FTSR1_FT18_Msk (0x1U << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
  6231. #define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */
  6232. #define EXTI_FTSR1_FT19_Pos (19U)
  6233. #define EXTI_FTSR1_FT19_Msk (0x1U << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
  6234. #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
  6235. #define EXTI_FTSR1_FT20_Pos (20U)
  6236. #define EXTI_FTSR1_FT20_Msk (0x1U << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
  6237. #define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
  6238. #define EXTI_FTSR1_FT21_Pos (21U)
  6239. #define EXTI_FTSR1_FT21_Msk (0x1U << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
  6240. #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
  6241. #define EXTI_FTSR1_FT22_Pos (22U)
  6242. #define EXTI_FTSR1_FT22_Msk (0x1U << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
  6243. #define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
  6244. /****************** Bit definition for EXTI_SWIER1 register *****************/
  6245. #define EXTI_SWIER1_SWI0_Pos (0U)
  6246. #define EXTI_SWIER1_SWI0_Msk (0x1U << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
  6247. #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
  6248. #define EXTI_SWIER1_SWI1_Pos (1U)
  6249. #define EXTI_SWIER1_SWI1_Msk (0x1U << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
  6250. #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
  6251. #define EXTI_SWIER1_SWI2_Pos (2U)
  6252. #define EXTI_SWIER1_SWI2_Msk (0x1U << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
  6253. #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
  6254. #define EXTI_SWIER1_SWI3_Pos (3U)
  6255. #define EXTI_SWIER1_SWI3_Msk (0x1U << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
  6256. #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
  6257. #define EXTI_SWIER1_SWI4_Pos (4U)
  6258. #define EXTI_SWIER1_SWI4_Msk (0x1U << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
  6259. #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
  6260. #define EXTI_SWIER1_SWI5_Pos (5U)
  6261. #define EXTI_SWIER1_SWI5_Msk (0x1U << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
  6262. #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
  6263. #define EXTI_SWIER1_SWI6_Pos (6U)
  6264. #define EXTI_SWIER1_SWI6_Msk (0x1U << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
  6265. #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
  6266. #define EXTI_SWIER1_SWI7_Pos (7U)
  6267. #define EXTI_SWIER1_SWI7_Msk (0x1U << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
  6268. #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
  6269. #define EXTI_SWIER1_SWI8_Pos (8U)
  6270. #define EXTI_SWIER1_SWI8_Msk (0x1U << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
  6271. #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
  6272. #define EXTI_SWIER1_SWI9_Pos (9U)
  6273. #define EXTI_SWIER1_SWI9_Msk (0x1U << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
  6274. #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
  6275. #define EXTI_SWIER1_SWI10_Pos (10U)
  6276. #define EXTI_SWIER1_SWI10_Msk (0x1U << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
  6277. #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
  6278. #define EXTI_SWIER1_SWI11_Pos (11U)
  6279. #define EXTI_SWIER1_SWI11_Msk (0x1U << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
  6280. #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
  6281. #define EXTI_SWIER1_SWI12_Pos (12U)
  6282. #define EXTI_SWIER1_SWI12_Msk (0x1U << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
  6283. #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
  6284. #define EXTI_SWIER1_SWI13_Pos (13U)
  6285. #define EXTI_SWIER1_SWI13_Msk (0x1U << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
  6286. #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
  6287. #define EXTI_SWIER1_SWI14_Pos (14U)
  6288. #define EXTI_SWIER1_SWI14_Msk (0x1U << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
  6289. #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
  6290. #define EXTI_SWIER1_SWI15_Pos (15U)
  6291. #define EXTI_SWIER1_SWI15_Msk (0x1U << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
  6292. #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
  6293. #define EXTI_SWIER1_SWI16_Pos (16U)
  6294. #define EXTI_SWIER1_SWI16_Msk (0x1U << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
  6295. #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
  6296. #define EXTI_SWIER1_SWI18_Pos (18U)
  6297. #define EXTI_SWIER1_SWI18_Msk (0x1U << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
  6298. #define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
  6299. #define EXTI_SWIER1_SWI19_Pos (19U)
  6300. #define EXTI_SWIER1_SWI19_Msk (0x1U << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
  6301. #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
  6302. #define EXTI_SWIER1_SWI20_Pos (20U)
  6303. #define EXTI_SWIER1_SWI20_Msk (0x1U << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
  6304. #define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
  6305. #define EXTI_SWIER1_SWI21_Pos (21U)
  6306. #define EXTI_SWIER1_SWI21_Msk (0x1U << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
  6307. #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
  6308. #define EXTI_SWIER1_SWI22_Pos (22U)
  6309. #define EXTI_SWIER1_SWI22_Msk (0x1U << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
  6310. #define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
  6311. /******************* Bit definition for EXTI_PR1 register *******************/
  6312. #define EXTI_PR1_PIF0_Pos (0U)
  6313. #define EXTI_PR1_PIF0_Msk (0x1U << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
  6314. #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
  6315. #define EXTI_PR1_PIF1_Pos (1U)
  6316. #define EXTI_PR1_PIF1_Msk (0x1U << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
  6317. #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
  6318. #define EXTI_PR1_PIF2_Pos (2U)
  6319. #define EXTI_PR1_PIF2_Msk (0x1U << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
  6320. #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
  6321. #define EXTI_PR1_PIF3_Pos (3U)
  6322. #define EXTI_PR1_PIF3_Msk (0x1U << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
  6323. #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
  6324. #define EXTI_PR1_PIF4_Pos (4U)
  6325. #define EXTI_PR1_PIF4_Msk (0x1U << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
  6326. #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
  6327. #define EXTI_PR1_PIF5_Pos (5U)
  6328. #define EXTI_PR1_PIF5_Msk (0x1U << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
  6329. #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
  6330. #define EXTI_PR1_PIF6_Pos (6U)
  6331. #define EXTI_PR1_PIF6_Msk (0x1U << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
  6332. #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
  6333. #define EXTI_PR1_PIF7_Pos (7U)
  6334. #define EXTI_PR1_PIF7_Msk (0x1U << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
  6335. #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
  6336. #define EXTI_PR1_PIF8_Pos (8U)
  6337. #define EXTI_PR1_PIF8_Msk (0x1U << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
  6338. #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
  6339. #define EXTI_PR1_PIF9_Pos (9U)
  6340. #define EXTI_PR1_PIF9_Msk (0x1U << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
  6341. #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
  6342. #define EXTI_PR1_PIF10_Pos (10U)
  6343. #define EXTI_PR1_PIF10_Msk (0x1U << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
  6344. #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
  6345. #define EXTI_PR1_PIF11_Pos (11U)
  6346. #define EXTI_PR1_PIF11_Msk (0x1U << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
  6347. #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
  6348. #define EXTI_PR1_PIF12_Pos (12U)
  6349. #define EXTI_PR1_PIF12_Msk (0x1U << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
  6350. #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
  6351. #define EXTI_PR1_PIF13_Pos (13U)
  6352. #define EXTI_PR1_PIF13_Msk (0x1U << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
  6353. #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
  6354. #define EXTI_PR1_PIF14_Pos (14U)
  6355. #define EXTI_PR1_PIF14_Msk (0x1U << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
  6356. #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
  6357. #define EXTI_PR1_PIF15_Pos (15U)
  6358. #define EXTI_PR1_PIF15_Msk (0x1U << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
  6359. #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
  6360. #define EXTI_PR1_PIF16_Pos (16U)
  6361. #define EXTI_PR1_PIF16_Msk (0x1U << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
  6362. #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
  6363. #define EXTI_PR1_PIF18_Pos (18U)
  6364. #define EXTI_PR1_PIF18_Msk (0x1U << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */
  6365. #define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */
  6366. #define EXTI_PR1_PIF19_Pos (19U)
  6367. #define EXTI_PR1_PIF19_Msk (0x1U << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
  6368. #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
  6369. #define EXTI_PR1_PIF20_Pos (20U)
  6370. #define EXTI_PR1_PIF20_Msk (0x1U << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
  6371. #define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
  6372. #define EXTI_PR1_PIF21_Pos (21U)
  6373. #define EXTI_PR1_PIF21_Msk (0x1U << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
  6374. #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
  6375. #define EXTI_PR1_PIF22_Pos (22U)
  6376. #define EXTI_PR1_PIF22_Msk (0x1U << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
  6377. #define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
  6378. /******************* Bit definition for EXTI_IMR2 register ******************/
  6379. #define EXTI_IMR2_IM32_Pos (0U)
  6380. #define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
  6381. #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
  6382. #define EXTI_IMR2_IM33_Pos (1U)
  6383. #define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
  6384. #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
  6385. #define EXTI_IMR2_IM34_Pos (2U)
  6386. #define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
  6387. #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
  6388. #define EXTI_IMR2_IM35_Pos (3U)
  6389. #define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
  6390. #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
  6391. #define EXTI_IMR2_IM37_Pos (5U)
  6392. #define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
  6393. #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
  6394. #define EXTI_IMR2_IM38_Pos (6U)
  6395. #define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
  6396. #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
  6397. #define EXTI_IMR2_IM_Pos (0U)
  6398. #define EXTI_IMR2_IM_Msk (0x6FU << EXTI_IMR2_IM_Pos) /*!< 0x0000006F */
  6399. #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
  6400. /******************* Bit definition for EXTI_EMR2 register ******************/
  6401. #define EXTI_EMR2_EM32_Pos (0U)
  6402. #define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
  6403. #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
  6404. #define EXTI_EMR2_EM33_Pos (1U)
  6405. #define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
  6406. #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
  6407. #define EXTI_EMR2_EM34_Pos (2U)
  6408. #define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
  6409. #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
  6410. #define EXTI_EMR2_EM35_Pos (3U)
  6411. #define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
  6412. #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
  6413. #define EXTI_EMR2_EM37_Pos (5U)
  6414. #define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
  6415. #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
  6416. #define EXTI_EMR2_EM38_Pos (6U)
  6417. #define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
  6418. #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
  6419. #define EXTI_EMR2_EM_Pos (0U)
  6420. #define EXTI_EMR2_EM_Msk (0x6FU << EXTI_EMR2_EM_Pos) /*!< 0x0000006F */
  6421. #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
  6422. /****************** Bit definition for EXTI_RTSR2 register ******************/
  6423. #define EXTI_RTSR2_RT35_Pos (3U)
  6424. #define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
  6425. #define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
  6426. #define EXTI_RTSR2_RT37_Pos (5U)
  6427. #define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
  6428. #define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
  6429. #define EXTI_RTSR2_RT38_Pos (6U)
  6430. #define EXTI_RTSR2_RT38_Msk (0x1U << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
  6431. #define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
  6432. /****************** Bit definition for EXTI_FTSR2 register ******************/
  6433. #define EXTI_FTSR2_FT35_Pos (3U)
  6434. #define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
  6435. #define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
  6436. #define EXTI_FTSR2_FT37_Pos (5U)
  6437. #define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
  6438. #define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
  6439. #define EXTI_FTSR2_FT38_Pos (6U)
  6440. #define EXTI_FTSR2_FT38_Msk (0x1U << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
  6441. #define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
  6442. /****************** Bit definition for EXTI_SWIER2 register *****************/
  6443. #define EXTI_SWIER2_SWI35_Pos (3U)
  6444. #define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
  6445. #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
  6446. #define EXTI_SWIER2_SWI37_Pos (5U)
  6447. #define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
  6448. #define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
  6449. #define EXTI_SWIER2_SWI38_Pos (6U)
  6450. #define EXTI_SWIER2_SWI38_Msk (0x1U << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
  6451. #define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
  6452. /******************* Bit definition for EXTI_PR2 register *******************/
  6453. #define EXTI_PR2_PIF35_Pos (3U)
  6454. #define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
  6455. #define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
  6456. #define EXTI_PR2_PIF37_Pos (5U)
  6457. #define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
  6458. #define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
  6459. #define EXTI_PR2_PIF38_Pos (6U)
  6460. #define EXTI_PR2_PIF38_Msk (0x1U << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
  6461. #define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
  6462. /******************************************************************************/
  6463. /* */
  6464. /* FLASH */
  6465. /* */
  6466. /******************************************************************************/
  6467. /******************* Bits definition for FLASH_ACR register *****************/
  6468. #define FLASH_ACR_LATENCY_Pos (0U)
  6469. #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
  6470. #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
  6471. #define FLASH_ACR_LATENCY_0WS (0x00000000U)
  6472. #define FLASH_ACR_LATENCY_1WS (0x00000001U)
  6473. #define FLASH_ACR_LATENCY_2WS (0x00000002U)
  6474. #define FLASH_ACR_LATENCY_3WS (0x00000003U)
  6475. #define FLASH_ACR_LATENCY_4WS (0x00000004U)
  6476. #define FLASH_ACR_PRFTEN_Pos (8U)
  6477. #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
  6478. #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
  6479. #define FLASH_ACR_ICEN_Pos (9U)
  6480. #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
  6481. #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
  6482. #define FLASH_ACR_DCEN_Pos (10U)
  6483. #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
  6484. #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
  6485. #define FLASH_ACR_ICRST_Pos (11U)
  6486. #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
  6487. #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
  6488. #define FLASH_ACR_DCRST_Pos (12U)
  6489. #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
  6490. #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
  6491. #define FLASH_ACR_RUN_PD_Pos (13U)
  6492. #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
  6493. #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
  6494. #define FLASH_ACR_SLEEP_PD_Pos (14U)
  6495. #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
  6496. #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
  6497. /******************* Bits definition for FLASH_SR register ******************/
  6498. #define FLASH_SR_EOP_Pos (0U)
  6499. #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
  6500. #define FLASH_SR_EOP FLASH_SR_EOP_Msk
  6501. #define FLASH_SR_OPERR_Pos (1U)
  6502. #define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
  6503. #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
  6504. #define FLASH_SR_PROGERR_Pos (3U)
  6505. #define FLASH_SR_PROGERR_Msk (0x1U << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
  6506. #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
  6507. #define FLASH_SR_WRPERR_Pos (4U)
  6508. #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
  6509. #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
  6510. #define FLASH_SR_PGAERR_Pos (5U)
  6511. #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
  6512. #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
  6513. #define FLASH_SR_SIZERR_Pos (6U)
  6514. #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
  6515. #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
  6516. #define FLASH_SR_PGSERR_Pos (7U)
  6517. #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
  6518. #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
  6519. #define FLASH_SR_MISERR_Pos (8U)
  6520. #define FLASH_SR_MISERR_Msk (0x1U << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
  6521. #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
  6522. #define FLASH_SR_FASTERR_Pos (9U)
  6523. #define FLASH_SR_FASTERR_Msk (0x1U << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
  6524. #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
  6525. #define FLASH_SR_RDERR_Pos (14U)
  6526. #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
  6527. #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
  6528. #define FLASH_SR_OPTVERR_Pos (15U)
  6529. #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
  6530. #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
  6531. #define FLASH_SR_BSY_Pos (16U)
  6532. #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
  6533. #define FLASH_SR_BSY FLASH_SR_BSY_Msk
  6534. #define FLASH_SR_PEMPTY_Pos (17U)
  6535. #define FLASH_SR_PEMPTY_Msk (0x1U << FLASH_SR_PEMPTY_Pos) /*!< 0x00020000 */
  6536. #define FLASH_SR_PEMPTY FLASH_SR_PEMPTY_Msk
  6537. /******************* Bits definition for FLASH_CR register ******************/
  6538. #define FLASH_CR_PG_Pos (0U)
  6539. #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
  6540. #define FLASH_CR_PG FLASH_CR_PG_Msk
  6541. #define FLASH_CR_PER_Pos (1U)
  6542. #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
  6543. #define FLASH_CR_PER FLASH_CR_PER_Msk
  6544. #define FLASH_CR_MER1_Pos (2U)
  6545. #define FLASH_CR_MER1_Msk (0x1U << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
  6546. #define FLASH_CR_MER1 FLASH_CR_MER1_Msk
  6547. #define FLASH_CR_PNB_Pos (3U)
  6548. #define FLASH_CR_PNB_Msk (0xFFU << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
  6549. #define FLASH_CR_PNB FLASH_CR_PNB_Msk
  6550. #define FLASH_CR_STRT_Pos (16U)
  6551. #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
  6552. #define FLASH_CR_STRT FLASH_CR_STRT_Msk
  6553. #define FLASH_CR_OPTSTRT_Pos (17U)
  6554. #define FLASH_CR_OPTSTRT_Msk (0x1U << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
  6555. #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
  6556. #define FLASH_CR_FSTPG_Pos (18U)
  6557. #define FLASH_CR_FSTPG_Msk (0x1U << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
  6558. #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
  6559. #define FLASH_CR_EOPIE_Pos (24U)
  6560. #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
  6561. #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
  6562. #define FLASH_CR_ERRIE_Pos (25U)
  6563. #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
  6564. #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
  6565. #define FLASH_CR_RDERRIE_Pos (26U)
  6566. #define FLASH_CR_RDERRIE_Msk (0x1U << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
  6567. #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
  6568. #define FLASH_CR_OBL_LAUNCH_Pos (27U)
  6569. #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
  6570. #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
  6571. #define FLASH_CR_OPTLOCK_Pos (30U)
  6572. #define FLASH_CR_OPTLOCK_Msk (0x1U << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
  6573. #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
  6574. #define FLASH_CR_LOCK_Pos (31U)
  6575. #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
  6576. #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
  6577. /******************* Bits definition for FLASH_ECCR register ***************/
  6578. #define FLASH_ECCR_ADDR_ECC_Pos (0U)
  6579. #define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
  6580. #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
  6581. #define FLASH_ECCR_SYSF_ECC_Pos (20U)
  6582. #define FLASH_ECCR_SYSF_ECC_Msk (0x1U << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
  6583. #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
  6584. #define FLASH_ECCR_ECCIE_Pos (24U)
  6585. #define FLASH_ECCR_ECCIE_Msk (0x1U << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
  6586. #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
  6587. #define FLASH_ECCR_ECCC_Pos (30U)
  6588. #define FLASH_ECCR_ECCC_Msk (0x1U << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
  6589. #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
  6590. #define FLASH_ECCR_ECCD_Pos (31U)
  6591. #define FLASH_ECCR_ECCD_Msk (0x1U << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
  6592. #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
  6593. /******************* Bits definition for FLASH_OPTR register ***************/
  6594. #define FLASH_OPTR_RDP_Pos (0U)
  6595. #define FLASH_OPTR_RDP_Msk (0xFFU << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
  6596. #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
  6597. #define FLASH_OPTR_BOR_LEV_Pos (8U)
  6598. #define FLASH_OPTR_BOR_LEV_Msk (0x7U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
  6599. #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
  6600. #define FLASH_OPTR_BOR_LEV_0 (0x0U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
  6601. #define FLASH_OPTR_BOR_LEV_1 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
  6602. #define FLASH_OPTR_BOR_LEV_2 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
  6603. #define FLASH_OPTR_BOR_LEV_3 (0x3U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
  6604. #define FLASH_OPTR_BOR_LEV_4 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
  6605. #define FLASH_OPTR_nRST_STOP_Pos (12U)
  6606. #define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
  6607. #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
  6608. #define FLASH_OPTR_nRST_STDBY_Pos (13U)
  6609. #define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
  6610. #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
  6611. #define FLASH_OPTR_nRST_SHDW_Pos (14U)
  6612. #define FLASH_OPTR_nRST_SHDW_Msk (0x1U << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
  6613. #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
  6614. #define FLASH_OPTR_IWDG_SW_Pos (16U)
  6615. #define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
  6616. #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
  6617. #define FLASH_OPTR_IWDG_STOP_Pos (17U)
  6618. #define FLASH_OPTR_IWDG_STOP_Msk (0x1U << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
  6619. #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
  6620. #define FLASH_OPTR_IWDG_STDBY_Pos (18U)
  6621. #define FLASH_OPTR_IWDG_STDBY_Msk (0x1U << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
  6622. #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
  6623. #define FLASH_OPTR_WWDG_SW_Pos (19U)
  6624. #define FLASH_OPTR_WWDG_SW_Msk (0x1U << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
  6625. #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
  6626. #define FLASH_OPTR_nBOOT1_Pos (23U)
  6627. #define FLASH_OPTR_nBOOT1_Msk (0x1U << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
  6628. #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
  6629. #define FLASH_OPTR_SRAM2_PE_Pos (24U)
  6630. #define FLASH_OPTR_SRAM2_PE_Msk (0x1U << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
  6631. #define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
  6632. #define FLASH_OPTR_SRAM2_RST_Pos (25U)
  6633. #define FLASH_OPTR_SRAM2_RST_Msk (0x1U << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
  6634. #define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
  6635. #define FLASH_OPTR_nSWBOOT0_Pos (26U)
  6636. #define FLASH_OPTR_nSWBOOT0_Msk (0x1U << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
  6637. #define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
  6638. #define FLASH_OPTR_nBOOT0_Pos (27U)
  6639. #define FLASH_OPTR_nBOOT0_Msk (0x1U << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
  6640. #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
  6641. /****************** Bits definition for FLASH_PCROP1SR register **********/
  6642. #define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
  6643. #define FLASH_PCROP1SR_PCROP1_STRT_Msk (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
  6644. #define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
  6645. /****************** Bits definition for FLASH_PCROP1ER register ***********/
  6646. #define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
  6647. #define FLASH_PCROP1ER_PCROP1_END_Msk (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
  6648. #define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
  6649. #define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
  6650. #define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
  6651. #define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
  6652. /****************** Bits definition for FLASH_WRP1AR register ***************/
  6653. #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
  6654. #define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
  6655. #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
  6656. #define FLASH_WRP1AR_WRP1A_END_Pos (16U)
  6657. #define FLASH_WRP1AR_WRP1A_END_Msk (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
  6658. #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
  6659. /****************** Bits definition for FLASH_WRPB1R register ***************/
  6660. #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
  6661. #define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
  6662. #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
  6663. #define FLASH_WRP1BR_WRP1B_END_Pos (16U)
  6664. #define FLASH_WRP1BR_WRP1B_END_Msk (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
  6665. #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
  6666. /******************************************************************************/
  6667. /* */
  6668. /* General Purpose IOs (GPIO) */
  6669. /* */
  6670. /******************************************************************************/
  6671. /****************** Bits definition for GPIO_MODER register *****************/
  6672. #define GPIO_MODER_MODE0_Pos (0U)
  6673. #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
  6674. #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
  6675. #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
  6676. #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
  6677. #define GPIO_MODER_MODE1_Pos (2U)
  6678. #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
  6679. #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
  6680. #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
  6681. #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
  6682. #define GPIO_MODER_MODE2_Pos (4U)
  6683. #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
  6684. #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
  6685. #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
  6686. #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
  6687. #define GPIO_MODER_MODE3_Pos (6U)
  6688. #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
  6689. #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
  6690. #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
  6691. #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
  6692. #define GPIO_MODER_MODE4_Pos (8U)
  6693. #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
  6694. #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
  6695. #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
  6696. #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
  6697. #define GPIO_MODER_MODE5_Pos (10U)
  6698. #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
  6699. #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
  6700. #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
  6701. #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
  6702. #define GPIO_MODER_MODE6_Pos (12U)
  6703. #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
  6704. #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
  6705. #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
  6706. #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
  6707. #define GPIO_MODER_MODE7_Pos (14U)
  6708. #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
  6709. #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
  6710. #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
  6711. #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
  6712. #define GPIO_MODER_MODE8_Pos (16U)
  6713. #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
  6714. #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
  6715. #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
  6716. #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
  6717. #define GPIO_MODER_MODE9_Pos (18U)
  6718. #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
  6719. #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
  6720. #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
  6721. #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
  6722. #define GPIO_MODER_MODE10_Pos (20U)
  6723. #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
  6724. #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
  6725. #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
  6726. #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
  6727. #define GPIO_MODER_MODE11_Pos (22U)
  6728. #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
  6729. #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
  6730. #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
  6731. #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
  6732. #define GPIO_MODER_MODE12_Pos (24U)
  6733. #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
  6734. #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
  6735. #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
  6736. #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
  6737. #define GPIO_MODER_MODE13_Pos (26U)
  6738. #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
  6739. #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
  6740. #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
  6741. #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
  6742. #define GPIO_MODER_MODE14_Pos (28U)
  6743. #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
  6744. #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
  6745. #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
  6746. #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
  6747. #define GPIO_MODER_MODE15_Pos (30U)
  6748. #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
  6749. #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
  6750. #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
  6751. #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
  6752. /* Legacy defines */
  6753. #define GPIO_MODER_MODER0 GPIO_MODER_MODE0
  6754. #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
  6755. #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
  6756. #define GPIO_MODER_MODER1 GPIO_MODER_MODE1
  6757. #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
  6758. #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
  6759. #define GPIO_MODER_MODER2 GPIO_MODER_MODE2
  6760. #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
  6761. #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
  6762. #define GPIO_MODER_MODER3 GPIO_MODER_MODE3
  6763. #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
  6764. #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
  6765. #define GPIO_MODER_MODER4 GPIO_MODER_MODE4
  6766. #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
  6767. #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
  6768. #define GPIO_MODER_MODER5 GPIO_MODER_MODE5
  6769. #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
  6770. #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
  6771. #define GPIO_MODER_MODER6 GPIO_MODER_MODE6
  6772. #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
  6773. #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
  6774. #define GPIO_MODER_MODER7 GPIO_MODER_MODE7
  6775. #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
  6776. #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
  6777. #define GPIO_MODER_MODER8 GPIO_MODER_MODE8
  6778. #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
  6779. #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
  6780. #define GPIO_MODER_MODER9 GPIO_MODER_MODE9
  6781. #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
  6782. #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
  6783. #define GPIO_MODER_MODER10 GPIO_MODER_MODE10
  6784. #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
  6785. #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
  6786. #define GPIO_MODER_MODER11 GPIO_MODER_MODE11
  6787. #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
  6788. #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
  6789. #define GPIO_MODER_MODER12 GPIO_MODER_MODE12
  6790. #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
  6791. #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
  6792. #define GPIO_MODER_MODER13 GPIO_MODER_MODE13
  6793. #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
  6794. #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
  6795. #define GPIO_MODER_MODER14 GPIO_MODER_MODE14
  6796. #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
  6797. #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
  6798. #define GPIO_MODER_MODER15 GPIO_MODER_MODE15
  6799. #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
  6800. #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
  6801. /****************** Bits definition for GPIO_OTYPER register ****************/
  6802. #define GPIO_OTYPER_OT0_Pos (0U)
  6803. #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
  6804. #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
  6805. #define GPIO_OTYPER_OT1_Pos (1U)
  6806. #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
  6807. #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
  6808. #define GPIO_OTYPER_OT2_Pos (2U)
  6809. #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
  6810. #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
  6811. #define GPIO_OTYPER_OT3_Pos (3U)
  6812. #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
  6813. #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
  6814. #define GPIO_OTYPER_OT4_Pos (4U)
  6815. #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
  6816. #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
  6817. #define GPIO_OTYPER_OT5_Pos (5U)
  6818. #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
  6819. #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
  6820. #define GPIO_OTYPER_OT6_Pos (6U)
  6821. #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
  6822. #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
  6823. #define GPIO_OTYPER_OT7_Pos (7U)
  6824. #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
  6825. #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
  6826. #define GPIO_OTYPER_OT8_Pos (8U)
  6827. #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
  6828. #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
  6829. #define GPIO_OTYPER_OT9_Pos (9U)
  6830. #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
  6831. #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
  6832. #define GPIO_OTYPER_OT10_Pos (10U)
  6833. #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
  6834. #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
  6835. #define GPIO_OTYPER_OT11_Pos (11U)
  6836. #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
  6837. #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
  6838. #define GPIO_OTYPER_OT12_Pos (12U)
  6839. #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
  6840. #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
  6841. #define GPIO_OTYPER_OT13_Pos (13U)
  6842. #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
  6843. #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
  6844. #define GPIO_OTYPER_OT14_Pos (14U)
  6845. #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
  6846. #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
  6847. #define GPIO_OTYPER_OT15_Pos (15U)
  6848. #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
  6849. #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
  6850. /* Legacy defines */
  6851. #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
  6852. #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
  6853. #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
  6854. #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
  6855. #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
  6856. #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
  6857. #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
  6858. #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
  6859. #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
  6860. #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
  6861. #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
  6862. #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
  6863. #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
  6864. #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
  6865. #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
  6866. #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
  6867. /****************** Bits definition for GPIO_OSPEEDR register ***************/
  6868. #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
  6869. #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
  6870. #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
  6871. #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
  6872. #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
  6873. #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
  6874. #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
  6875. #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
  6876. #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
  6877. #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
  6878. #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
  6879. #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
  6880. #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
  6881. #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
  6882. #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
  6883. #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
  6884. #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
  6885. #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
  6886. #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
  6887. #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
  6888. #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
  6889. #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
  6890. #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
  6891. #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
  6892. #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
  6893. #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
  6894. #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
  6895. #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
  6896. #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
  6897. #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
  6898. #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
  6899. #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
  6900. #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
  6901. #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
  6902. #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
  6903. #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
  6904. #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
  6905. #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
  6906. #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
  6907. #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
  6908. #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
  6909. #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
  6910. #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
  6911. #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
  6912. #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
  6913. #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
  6914. #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
  6915. #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
  6916. #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
  6917. #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
  6918. #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
  6919. #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
  6920. #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
  6921. #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
  6922. #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
  6923. #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
  6924. #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
  6925. #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
  6926. #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
  6927. #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
  6928. #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
  6929. #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
  6930. #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
  6931. #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
  6932. #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
  6933. #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
  6934. #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
  6935. #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
  6936. #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
  6937. #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
  6938. #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
  6939. #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
  6940. #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
  6941. #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
  6942. #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
  6943. #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
  6944. #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
  6945. #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
  6946. #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
  6947. #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
  6948. /* Legacy defines */
  6949. #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
  6950. #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
  6951. #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
  6952. #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
  6953. #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
  6954. #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
  6955. #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
  6956. #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
  6957. #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
  6958. #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
  6959. #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
  6960. #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
  6961. #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
  6962. #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
  6963. #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
  6964. #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
  6965. #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
  6966. #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
  6967. #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
  6968. #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
  6969. #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
  6970. #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
  6971. #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
  6972. #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
  6973. #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
  6974. #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
  6975. #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
  6976. #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
  6977. #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
  6978. #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
  6979. #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
  6980. #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
  6981. #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
  6982. #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
  6983. #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
  6984. #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
  6985. #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
  6986. #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
  6987. #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
  6988. #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
  6989. #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
  6990. #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
  6991. #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
  6992. #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
  6993. #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
  6994. #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
  6995. #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
  6996. #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
  6997. /****************** Bits definition for GPIO_PUPDR register *****************/
  6998. #define GPIO_PUPDR_PUPD0_Pos (0U)
  6999. #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
  7000. #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
  7001. #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
  7002. #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
  7003. #define GPIO_PUPDR_PUPD1_Pos (2U)
  7004. #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
  7005. #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
  7006. #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
  7007. #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
  7008. #define GPIO_PUPDR_PUPD2_Pos (4U)
  7009. #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
  7010. #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
  7011. #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
  7012. #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
  7013. #define GPIO_PUPDR_PUPD3_Pos (6U)
  7014. #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
  7015. #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
  7016. #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
  7017. #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
  7018. #define GPIO_PUPDR_PUPD4_Pos (8U)
  7019. #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
  7020. #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
  7021. #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
  7022. #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
  7023. #define GPIO_PUPDR_PUPD5_Pos (10U)
  7024. #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
  7025. #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
  7026. #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
  7027. #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
  7028. #define GPIO_PUPDR_PUPD6_Pos (12U)
  7029. #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
  7030. #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
  7031. #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
  7032. #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
  7033. #define GPIO_PUPDR_PUPD7_Pos (14U)
  7034. #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
  7035. #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
  7036. #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
  7037. #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
  7038. #define GPIO_PUPDR_PUPD8_Pos (16U)
  7039. #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
  7040. #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
  7041. #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
  7042. #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
  7043. #define GPIO_PUPDR_PUPD9_Pos (18U)
  7044. #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
  7045. #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
  7046. #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
  7047. #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
  7048. #define GPIO_PUPDR_PUPD10_Pos (20U)
  7049. #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
  7050. #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
  7051. #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
  7052. #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
  7053. #define GPIO_PUPDR_PUPD11_Pos (22U)
  7054. #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
  7055. #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
  7056. #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
  7057. #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
  7058. #define GPIO_PUPDR_PUPD12_Pos (24U)
  7059. #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
  7060. #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
  7061. #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
  7062. #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
  7063. #define GPIO_PUPDR_PUPD13_Pos (26U)
  7064. #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
  7065. #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
  7066. #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
  7067. #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
  7068. #define GPIO_PUPDR_PUPD14_Pos (28U)
  7069. #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
  7070. #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
  7071. #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
  7072. #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
  7073. #define GPIO_PUPDR_PUPD15_Pos (30U)
  7074. #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
  7075. #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
  7076. #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
  7077. #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
  7078. /* Legacy defines */
  7079. #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
  7080. #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
  7081. #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
  7082. #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
  7083. #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
  7084. #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
  7085. #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
  7086. #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
  7087. #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
  7088. #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
  7089. #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
  7090. #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
  7091. #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
  7092. #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
  7093. #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
  7094. #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
  7095. #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
  7096. #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
  7097. #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
  7098. #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
  7099. #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
  7100. #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
  7101. #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
  7102. #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
  7103. #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
  7104. #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
  7105. #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
  7106. #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
  7107. #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
  7108. #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
  7109. #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
  7110. #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
  7111. #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
  7112. #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
  7113. #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
  7114. #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
  7115. #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
  7116. #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
  7117. #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
  7118. #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
  7119. #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
  7120. #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
  7121. #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
  7122. #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
  7123. #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
  7124. #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
  7125. #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
  7126. #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
  7127. /****************** Bits definition for GPIO_IDR register *******************/
  7128. #define GPIO_IDR_ID0_Pos (0U)
  7129. #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
  7130. #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
  7131. #define GPIO_IDR_ID1_Pos (1U)
  7132. #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
  7133. #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
  7134. #define GPIO_IDR_ID2_Pos (2U)
  7135. #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
  7136. #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
  7137. #define GPIO_IDR_ID3_Pos (3U)
  7138. #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
  7139. #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
  7140. #define GPIO_IDR_ID4_Pos (4U)
  7141. #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
  7142. #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
  7143. #define GPIO_IDR_ID5_Pos (5U)
  7144. #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
  7145. #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
  7146. #define GPIO_IDR_ID6_Pos (6U)
  7147. #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
  7148. #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
  7149. #define GPIO_IDR_ID7_Pos (7U)
  7150. #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
  7151. #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
  7152. #define GPIO_IDR_ID8_Pos (8U)
  7153. #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
  7154. #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
  7155. #define GPIO_IDR_ID9_Pos (9U)
  7156. #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
  7157. #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
  7158. #define GPIO_IDR_ID10_Pos (10U)
  7159. #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
  7160. #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
  7161. #define GPIO_IDR_ID11_Pos (11U)
  7162. #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
  7163. #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
  7164. #define GPIO_IDR_ID12_Pos (12U)
  7165. #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
  7166. #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
  7167. #define GPIO_IDR_ID13_Pos (13U)
  7168. #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
  7169. #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
  7170. #define GPIO_IDR_ID14_Pos (14U)
  7171. #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
  7172. #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
  7173. #define GPIO_IDR_ID15_Pos (15U)
  7174. #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
  7175. #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
  7176. /* Legacy defines */
  7177. #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
  7178. #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
  7179. #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
  7180. #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
  7181. #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
  7182. #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
  7183. #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
  7184. #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
  7185. #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
  7186. #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
  7187. #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
  7188. #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
  7189. #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
  7190. #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
  7191. #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
  7192. #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
  7193. /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
  7194. #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
  7195. #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
  7196. #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
  7197. #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
  7198. #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
  7199. #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
  7200. #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
  7201. #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
  7202. #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
  7203. #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
  7204. #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
  7205. #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
  7206. #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
  7207. #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
  7208. #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
  7209. #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
  7210. /****************** Bits definition for GPIO_ODR register *******************/
  7211. #define GPIO_ODR_OD0_Pos (0U)
  7212. #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
  7213. #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
  7214. #define GPIO_ODR_OD1_Pos (1U)
  7215. #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
  7216. #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
  7217. #define GPIO_ODR_OD2_Pos (2U)
  7218. #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
  7219. #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
  7220. #define GPIO_ODR_OD3_Pos (3U)
  7221. #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
  7222. #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
  7223. #define GPIO_ODR_OD4_Pos (4U)
  7224. #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
  7225. #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
  7226. #define GPIO_ODR_OD5_Pos (5U)
  7227. #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
  7228. #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
  7229. #define GPIO_ODR_OD6_Pos (6U)
  7230. #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
  7231. #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
  7232. #define GPIO_ODR_OD7_Pos (7U)
  7233. #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
  7234. #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
  7235. #define GPIO_ODR_OD8_Pos (8U)
  7236. #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
  7237. #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
  7238. #define GPIO_ODR_OD9_Pos (9U)
  7239. #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
  7240. #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
  7241. #define GPIO_ODR_OD10_Pos (10U)
  7242. #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
  7243. #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
  7244. #define GPIO_ODR_OD11_Pos (11U)
  7245. #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
  7246. #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
  7247. #define GPIO_ODR_OD12_Pos (12U)
  7248. #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
  7249. #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
  7250. #define GPIO_ODR_OD13_Pos (13U)
  7251. #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
  7252. #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
  7253. #define GPIO_ODR_OD14_Pos (14U)
  7254. #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
  7255. #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
  7256. #define GPIO_ODR_OD15_Pos (15U)
  7257. #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
  7258. #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
  7259. /* Legacy defines */
  7260. #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
  7261. #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
  7262. #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
  7263. #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
  7264. #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
  7265. #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
  7266. #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
  7267. #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
  7268. #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
  7269. #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
  7270. #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
  7271. #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
  7272. #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
  7273. #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
  7274. #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
  7275. #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
  7276. /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
  7277. #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
  7278. #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
  7279. #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
  7280. #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
  7281. #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
  7282. #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
  7283. #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
  7284. #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
  7285. #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
  7286. #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
  7287. #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
  7288. #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
  7289. #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
  7290. #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
  7291. #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
  7292. #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
  7293. /****************** Bits definition for GPIO_BSRR register ******************/
  7294. #define GPIO_BSRR_BS0_Pos (0U)
  7295. #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
  7296. #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
  7297. #define GPIO_BSRR_BS1_Pos (1U)
  7298. #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
  7299. #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
  7300. #define GPIO_BSRR_BS2_Pos (2U)
  7301. #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
  7302. #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
  7303. #define GPIO_BSRR_BS3_Pos (3U)
  7304. #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
  7305. #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
  7306. #define GPIO_BSRR_BS4_Pos (4U)
  7307. #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
  7308. #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
  7309. #define GPIO_BSRR_BS5_Pos (5U)
  7310. #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
  7311. #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
  7312. #define GPIO_BSRR_BS6_Pos (6U)
  7313. #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
  7314. #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
  7315. #define GPIO_BSRR_BS7_Pos (7U)
  7316. #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
  7317. #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
  7318. #define GPIO_BSRR_BS8_Pos (8U)
  7319. #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
  7320. #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
  7321. #define GPIO_BSRR_BS9_Pos (9U)
  7322. #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
  7323. #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
  7324. #define GPIO_BSRR_BS10_Pos (10U)
  7325. #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
  7326. #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
  7327. #define GPIO_BSRR_BS11_Pos (11U)
  7328. #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
  7329. #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
  7330. #define GPIO_BSRR_BS12_Pos (12U)
  7331. #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
  7332. #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
  7333. #define GPIO_BSRR_BS13_Pos (13U)
  7334. #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
  7335. #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
  7336. #define GPIO_BSRR_BS14_Pos (14U)
  7337. #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
  7338. #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
  7339. #define GPIO_BSRR_BS15_Pos (15U)
  7340. #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
  7341. #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
  7342. #define GPIO_BSRR_BR0_Pos (16U)
  7343. #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
  7344. #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
  7345. #define GPIO_BSRR_BR1_Pos (17U)
  7346. #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
  7347. #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
  7348. #define GPIO_BSRR_BR2_Pos (18U)
  7349. #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
  7350. #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
  7351. #define GPIO_BSRR_BR3_Pos (19U)
  7352. #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
  7353. #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
  7354. #define GPIO_BSRR_BR4_Pos (20U)
  7355. #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
  7356. #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
  7357. #define GPIO_BSRR_BR5_Pos (21U)
  7358. #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
  7359. #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
  7360. #define GPIO_BSRR_BR6_Pos (22U)
  7361. #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
  7362. #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
  7363. #define GPIO_BSRR_BR7_Pos (23U)
  7364. #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
  7365. #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
  7366. #define GPIO_BSRR_BR8_Pos (24U)
  7367. #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
  7368. #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
  7369. #define GPIO_BSRR_BR9_Pos (25U)
  7370. #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
  7371. #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
  7372. #define GPIO_BSRR_BR10_Pos (26U)
  7373. #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
  7374. #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
  7375. #define GPIO_BSRR_BR11_Pos (27U)
  7376. #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
  7377. #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
  7378. #define GPIO_BSRR_BR12_Pos (28U)
  7379. #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
  7380. #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
  7381. #define GPIO_BSRR_BR13_Pos (29U)
  7382. #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
  7383. #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
  7384. #define GPIO_BSRR_BR14_Pos (30U)
  7385. #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
  7386. #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
  7387. #define GPIO_BSRR_BR15_Pos (31U)
  7388. #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
  7389. #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
  7390. /* Legacy defines */
  7391. #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
  7392. #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
  7393. #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
  7394. #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
  7395. #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
  7396. #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
  7397. #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
  7398. #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
  7399. #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
  7400. #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
  7401. #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
  7402. #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
  7403. #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
  7404. #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
  7405. #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
  7406. #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
  7407. #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
  7408. #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
  7409. #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
  7410. #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
  7411. #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
  7412. #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
  7413. #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
  7414. #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
  7415. #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
  7416. #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
  7417. #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
  7418. #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
  7419. #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
  7420. #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
  7421. #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
  7422. #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
  7423. /****************** Bit definition for GPIO_LCKR register *********************/
  7424. #define GPIO_LCKR_LCK0_Pos (0U)
  7425. #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
  7426. #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
  7427. #define GPIO_LCKR_LCK1_Pos (1U)
  7428. #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
  7429. #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
  7430. #define GPIO_LCKR_LCK2_Pos (2U)
  7431. #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
  7432. #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
  7433. #define GPIO_LCKR_LCK3_Pos (3U)
  7434. #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
  7435. #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
  7436. #define GPIO_LCKR_LCK4_Pos (4U)
  7437. #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
  7438. #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
  7439. #define GPIO_LCKR_LCK5_Pos (5U)
  7440. #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
  7441. #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
  7442. #define GPIO_LCKR_LCK6_Pos (6U)
  7443. #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
  7444. #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
  7445. #define GPIO_LCKR_LCK7_Pos (7U)
  7446. #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
  7447. #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
  7448. #define GPIO_LCKR_LCK8_Pos (8U)
  7449. #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
  7450. #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
  7451. #define GPIO_LCKR_LCK9_Pos (9U)
  7452. #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
  7453. #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
  7454. #define GPIO_LCKR_LCK10_Pos (10U)
  7455. #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
  7456. #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
  7457. #define GPIO_LCKR_LCK11_Pos (11U)
  7458. #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
  7459. #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
  7460. #define GPIO_LCKR_LCK12_Pos (12U)
  7461. #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
  7462. #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
  7463. #define GPIO_LCKR_LCK13_Pos (13U)
  7464. #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
  7465. #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
  7466. #define GPIO_LCKR_LCK14_Pos (14U)
  7467. #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
  7468. #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
  7469. #define GPIO_LCKR_LCK15_Pos (15U)
  7470. #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
  7471. #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
  7472. #define GPIO_LCKR_LCKK_Pos (16U)
  7473. #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
  7474. #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
  7475. /****************** Bit definition for GPIO_AFRL register *********************/
  7476. #define GPIO_AFRL_AFSEL0_Pos (0U)
  7477. #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
  7478. #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
  7479. #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
  7480. #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
  7481. #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
  7482. #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
  7483. #define GPIO_AFRL_AFSEL1_Pos (4U)
  7484. #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
  7485. #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
  7486. #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
  7487. #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
  7488. #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
  7489. #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
  7490. #define GPIO_AFRL_AFSEL2_Pos (8U)
  7491. #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
  7492. #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
  7493. #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
  7494. #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
  7495. #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
  7496. #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
  7497. #define GPIO_AFRL_AFSEL3_Pos (12U)
  7498. #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
  7499. #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
  7500. #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
  7501. #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
  7502. #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
  7503. #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
  7504. #define GPIO_AFRL_AFSEL4_Pos (16U)
  7505. #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
  7506. #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
  7507. #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
  7508. #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
  7509. #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
  7510. #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
  7511. #define GPIO_AFRL_AFSEL5_Pos (20U)
  7512. #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
  7513. #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
  7514. #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
  7515. #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
  7516. #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
  7517. #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
  7518. #define GPIO_AFRL_AFSEL6_Pos (24U)
  7519. #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
  7520. #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
  7521. #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
  7522. #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
  7523. #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
  7524. #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
  7525. #define GPIO_AFRL_AFSEL7_Pos (28U)
  7526. #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
  7527. #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
  7528. #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
  7529. #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
  7530. #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
  7531. #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
  7532. /* Legacy defines */
  7533. #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
  7534. #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
  7535. #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
  7536. #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
  7537. #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
  7538. #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
  7539. #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
  7540. #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
  7541. /****************** Bit definition for GPIO_AFRH register *********************/
  7542. #define GPIO_AFRH_AFSEL8_Pos (0U)
  7543. #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
  7544. #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
  7545. #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
  7546. #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
  7547. #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
  7548. #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
  7549. #define GPIO_AFRH_AFSEL9_Pos (4U)
  7550. #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
  7551. #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
  7552. #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
  7553. #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
  7554. #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
  7555. #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
  7556. #define GPIO_AFRH_AFSEL10_Pos (8U)
  7557. #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
  7558. #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
  7559. #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
  7560. #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
  7561. #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
  7562. #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
  7563. #define GPIO_AFRH_AFSEL11_Pos (12U)
  7564. #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
  7565. #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
  7566. #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
  7567. #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
  7568. #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
  7569. #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
  7570. #define GPIO_AFRH_AFSEL12_Pos (16U)
  7571. #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
  7572. #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
  7573. #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
  7574. #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
  7575. #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
  7576. #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
  7577. #define GPIO_AFRH_AFSEL13_Pos (20U)
  7578. #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
  7579. #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
  7580. #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
  7581. #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
  7582. #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
  7583. #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
  7584. #define GPIO_AFRH_AFSEL14_Pos (24U)
  7585. #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
  7586. #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
  7587. #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
  7588. #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
  7589. #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
  7590. #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
  7591. #define GPIO_AFRH_AFSEL15_Pos (28U)
  7592. #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
  7593. #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
  7594. #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
  7595. #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
  7596. #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
  7597. #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
  7598. /* Legacy defines */
  7599. #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
  7600. #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
  7601. #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
  7602. #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
  7603. #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
  7604. #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
  7605. #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
  7606. #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
  7607. /****************** Bits definition for GPIO_BRR register ******************/
  7608. #define GPIO_BRR_BR0_Pos (0U)
  7609. #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
  7610. #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
  7611. #define GPIO_BRR_BR1_Pos (1U)
  7612. #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
  7613. #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
  7614. #define GPIO_BRR_BR2_Pos (2U)
  7615. #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
  7616. #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
  7617. #define GPIO_BRR_BR3_Pos (3U)
  7618. #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
  7619. #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
  7620. #define GPIO_BRR_BR4_Pos (4U)
  7621. #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
  7622. #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
  7623. #define GPIO_BRR_BR5_Pos (5U)
  7624. #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
  7625. #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
  7626. #define GPIO_BRR_BR6_Pos (6U)
  7627. #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
  7628. #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
  7629. #define GPIO_BRR_BR7_Pos (7U)
  7630. #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
  7631. #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
  7632. #define GPIO_BRR_BR8_Pos (8U)
  7633. #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
  7634. #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
  7635. #define GPIO_BRR_BR9_Pos (9U)
  7636. #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
  7637. #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
  7638. #define GPIO_BRR_BR10_Pos (10U)
  7639. #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
  7640. #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
  7641. #define GPIO_BRR_BR11_Pos (11U)
  7642. #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
  7643. #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
  7644. #define GPIO_BRR_BR12_Pos (12U)
  7645. #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
  7646. #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
  7647. #define GPIO_BRR_BR13_Pos (13U)
  7648. #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
  7649. #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
  7650. #define GPIO_BRR_BR14_Pos (14U)
  7651. #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
  7652. #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
  7653. #define GPIO_BRR_BR15_Pos (15U)
  7654. #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
  7655. #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
  7656. /* Legacy defines */
  7657. #define GPIO_BRR_BR_0 GPIO_BRR_BR0
  7658. #define GPIO_BRR_BR_1 GPIO_BRR_BR1
  7659. #define GPIO_BRR_BR_2 GPIO_BRR_BR2
  7660. #define GPIO_BRR_BR_3 GPIO_BRR_BR3
  7661. #define GPIO_BRR_BR_4 GPIO_BRR_BR4
  7662. #define GPIO_BRR_BR_5 GPIO_BRR_BR5
  7663. #define GPIO_BRR_BR_6 GPIO_BRR_BR6
  7664. #define GPIO_BRR_BR_7 GPIO_BRR_BR7
  7665. #define GPIO_BRR_BR_8 GPIO_BRR_BR8
  7666. #define GPIO_BRR_BR_9 GPIO_BRR_BR9
  7667. #define GPIO_BRR_BR_10 GPIO_BRR_BR10
  7668. #define GPIO_BRR_BR_11 GPIO_BRR_BR11
  7669. #define GPIO_BRR_BR_12 GPIO_BRR_BR12
  7670. #define GPIO_BRR_BR_13 GPIO_BRR_BR13
  7671. #define GPIO_BRR_BR_14 GPIO_BRR_BR14
  7672. #define GPIO_BRR_BR_15 GPIO_BRR_BR15
  7673. /******************************************************************************/
  7674. /* */
  7675. /* Inter-integrated Circuit Interface (I2C) */
  7676. /* */
  7677. /******************************************************************************/
  7678. /******************* Bit definition for I2C_CR1 register *******************/
  7679. #define I2C_CR1_PE_Pos (0U)
  7680. #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
  7681. #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
  7682. #define I2C_CR1_TXIE_Pos (1U)
  7683. #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
  7684. #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
  7685. #define I2C_CR1_RXIE_Pos (2U)
  7686. #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
  7687. #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
  7688. #define I2C_CR1_ADDRIE_Pos (3U)
  7689. #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
  7690. #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
  7691. #define I2C_CR1_NACKIE_Pos (4U)
  7692. #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
  7693. #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
  7694. #define I2C_CR1_STOPIE_Pos (5U)
  7695. #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
  7696. #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
  7697. #define I2C_CR1_TCIE_Pos (6U)
  7698. #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
  7699. #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
  7700. #define I2C_CR1_ERRIE_Pos (7U)
  7701. #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
  7702. #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
  7703. #define I2C_CR1_DNF_Pos (8U)
  7704. #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
  7705. #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
  7706. #define I2C_CR1_ANFOFF_Pos (12U)
  7707. #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
  7708. #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
  7709. #define I2C_CR1_SWRST_Pos (13U)
  7710. #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
  7711. #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
  7712. #define I2C_CR1_TXDMAEN_Pos (14U)
  7713. #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
  7714. #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
  7715. #define I2C_CR1_RXDMAEN_Pos (15U)
  7716. #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
  7717. #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
  7718. #define I2C_CR1_SBC_Pos (16U)
  7719. #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
  7720. #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
  7721. #define I2C_CR1_NOSTRETCH_Pos (17U)
  7722. #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
  7723. #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
  7724. #define I2C_CR1_WUPEN_Pos (18U)
  7725. #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
  7726. #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
  7727. #define I2C_CR1_GCEN_Pos (19U)
  7728. #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
  7729. #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
  7730. #define I2C_CR1_SMBHEN_Pos (20U)
  7731. #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
  7732. #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
  7733. #define I2C_CR1_SMBDEN_Pos (21U)
  7734. #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
  7735. #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
  7736. #define I2C_CR1_ALERTEN_Pos (22U)
  7737. #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
  7738. #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
  7739. #define I2C_CR1_PECEN_Pos (23U)
  7740. #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
  7741. #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
  7742. /****************** Bit definition for I2C_CR2 register ********************/
  7743. #define I2C_CR2_SADD_Pos (0U)
  7744. #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
  7745. #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
  7746. #define I2C_CR2_RD_WRN_Pos (10U)
  7747. #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
  7748. #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
  7749. #define I2C_CR2_ADD10_Pos (11U)
  7750. #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
  7751. #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
  7752. #define I2C_CR2_HEAD10R_Pos (12U)
  7753. #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
  7754. #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
  7755. #define I2C_CR2_START_Pos (13U)
  7756. #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
  7757. #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
  7758. #define I2C_CR2_STOP_Pos (14U)
  7759. #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
  7760. #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
  7761. #define I2C_CR2_NACK_Pos (15U)
  7762. #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
  7763. #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
  7764. #define I2C_CR2_NBYTES_Pos (16U)
  7765. #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
  7766. #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
  7767. #define I2C_CR2_RELOAD_Pos (24U)
  7768. #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
  7769. #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
  7770. #define I2C_CR2_AUTOEND_Pos (25U)
  7771. #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
  7772. #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
  7773. #define I2C_CR2_PECBYTE_Pos (26U)
  7774. #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
  7775. #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
  7776. /******************* Bit definition for I2C_OAR1 register ******************/
  7777. #define I2C_OAR1_OA1_Pos (0U)
  7778. #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
  7779. #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
  7780. #define I2C_OAR1_OA1MODE_Pos (10U)
  7781. #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
  7782. #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
  7783. #define I2C_OAR1_OA1EN_Pos (15U)
  7784. #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
  7785. #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
  7786. /******************* Bit definition for I2C_OAR2 register ******************/
  7787. #define I2C_OAR2_OA2_Pos (1U)
  7788. #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
  7789. #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
  7790. #define I2C_OAR2_OA2MSK_Pos (8U)
  7791. #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
  7792. #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
  7793. #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
  7794. #define I2C_OAR2_OA2MASK01_Pos (8U)
  7795. #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
  7796. #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
  7797. #define I2C_OAR2_OA2MASK02_Pos (9U)
  7798. #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
  7799. #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
  7800. #define I2C_OAR2_OA2MASK03_Pos (8U)
  7801. #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
  7802. #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
  7803. #define I2C_OAR2_OA2MASK04_Pos (10U)
  7804. #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
  7805. #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
  7806. #define I2C_OAR2_OA2MASK05_Pos (8U)
  7807. #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
  7808. #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
  7809. #define I2C_OAR2_OA2MASK06_Pos (9U)
  7810. #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
  7811. #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
  7812. #define I2C_OAR2_OA2MASK07_Pos (8U)
  7813. #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
  7814. #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
  7815. #define I2C_OAR2_OA2EN_Pos (15U)
  7816. #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
  7817. #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
  7818. /******************* Bit definition for I2C_TIMINGR register *******************/
  7819. #define I2C_TIMINGR_SCLL_Pos (0U)
  7820. #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
  7821. #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
  7822. #define I2C_TIMINGR_SCLH_Pos (8U)
  7823. #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
  7824. #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
  7825. #define I2C_TIMINGR_SDADEL_Pos (16U)
  7826. #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
  7827. #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
  7828. #define I2C_TIMINGR_SCLDEL_Pos (20U)
  7829. #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
  7830. #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
  7831. #define I2C_TIMINGR_PRESC_Pos (28U)
  7832. #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
  7833. #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
  7834. /******************* Bit definition for I2C_TIMEOUTR register *******************/
  7835. #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
  7836. #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
  7837. #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
  7838. #define I2C_TIMEOUTR_TIDLE_Pos (12U)
  7839. #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
  7840. #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
  7841. #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
  7842. #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
  7843. #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
  7844. #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
  7845. #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
  7846. #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
  7847. #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
  7848. #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
  7849. #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
  7850. /****************** Bit definition for I2C_ISR register *********************/
  7851. #define I2C_ISR_TXE_Pos (0U)
  7852. #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
  7853. #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
  7854. #define I2C_ISR_TXIS_Pos (1U)
  7855. #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
  7856. #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
  7857. #define I2C_ISR_RXNE_Pos (2U)
  7858. #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
  7859. #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
  7860. #define I2C_ISR_ADDR_Pos (3U)
  7861. #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
  7862. #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
  7863. #define I2C_ISR_NACKF_Pos (4U)
  7864. #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
  7865. #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
  7866. #define I2C_ISR_STOPF_Pos (5U)
  7867. #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
  7868. #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
  7869. #define I2C_ISR_TC_Pos (6U)
  7870. #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
  7871. #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
  7872. #define I2C_ISR_TCR_Pos (7U)
  7873. #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
  7874. #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
  7875. #define I2C_ISR_BERR_Pos (8U)
  7876. #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
  7877. #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
  7878. #define I2C_ISR_ARLO_Pos (9U)
  7879. #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
  7880. #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
  7881. #define I2C_ISR_OVR_Pos (10U)
  7882. #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
  7883. #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
  7884. #define I2C_ISR_PECERR_Pos (11U)
  7885. #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
  7886. #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
  7887. #define I2C_ISR_TIMEOUT_Pos (12U)
  7888. #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
  7889. #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
  7890. #define I2C_ISR_ALERT_Pos (13U)
  7891. #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
  7892. #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
  7893. #define I2C_ISR_BUSY_Pos (15U)
  7894. #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
  7895. #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
  7896. #define I2C_ISR_DIR_Pos (16U)
  7897. #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
  7898. #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
  7899. #define I2C_ISR_ADDCODE_Pos (17U)
  7900. #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
  7901. #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
  7902. /****************** Bit definition for I2C_ICR register *********************/
  7903. #define I2C_ICR_ADDRCF_Pos (3U)
  7904. #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
  7905. #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
  7906. #define I2C_ICR_NACKCF_Pos (4U)
  7907. #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
  7908. #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
  7909. #define I2C_ICR_STOPCF_Pos (5U)
  7910. #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
  7911. #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
  7912. #define I2C_ICR_BERRCF_Pos (8U)
  7913. #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
  7914. #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
  7915. #define I2C_ICR_ARLOCF_Pos (9U)
  7916. #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
  7917. #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
  7918. #define I2C_ICR_OVRCF_Pos (10U)
  7919. #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
  7920. #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
  7921. #define I2C_ICR_PECCF_Pos (11U)
  7922. #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
  7923. #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
  7924. #define I2C_ICR_TIMOUTCF_Pos (12U)
  7925. #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
  7926. #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
  7927. #define I2C_ICR_ALERTCF_Pos (13U)
  7928. #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
  7929. #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
  7930. /****************** Bit definition for I2C_PECR register *********************/
  7931. #define I2C_PECR_PEC_Pos (0U)
  7932. #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
  7933. #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
  7934. /****************** Bit definition for I2C_RXDR register *********************/
  7935. #define I2C_RXDR_RXDATA_Pos (0U)
  7936. #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
  7937. #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
  7938. /****************** Bit definition for I2C_TXDR register *********************/
  7939. #define I2C_TXDR_TXDATA_Pos (0U)
  7940. #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
  7941. #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
  7942. /******************************************************************************/
  7943. /* */
  7944. /* Independent WATCHDOG */
  7945. /* */
  7946. /******************************************************************************/
  7947. /******************* Bit definition for IWDG_KR register ********************/
  7948. #define IWDG_KR_KEY_Pos (0U)
  7949. #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
  7950. #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
  7951. /******************* Bit definition for IWDG_PR register ********************/
  7952. #define IWDG_PR_PR_Pos (0U)
  7953. #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
  7954. #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
  7955. #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
  7956. #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
  7957. #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
  7958. /******************* Bit definition for IWDG_RLR register *******************/
  7959. #define IWDG_RLR_RL_Pos (0U)
  7960. #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
  7961. #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
  7962. /******************* Bit definition for IWDG_SR register ********************/
  7963. #define IWDG_SR_PVU_Pos (0U)
  7964. #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
  7965. #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
  7966. #define IWDG_SR_RVU_Pos (1U)
  7967. #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
  7968. #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
  7969. #define IWDG_SR_WVU_Pos (2U)
  7970. #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
  7971. #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
  7972. /******************* Bit definition for IWDG_KR register ********************/
  7973. #define IWDG_WINR_WIN_Pos (0U)
  7974. #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
  7975. #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
  7976. /******************************************************************************/
  7977. /* */
  7978. /* Firewall */
  7979. /* */
  7980. /******************************************************************************/
  7981. /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
  7982. #define FW_CSSA_ADD_Pos (8U)
  7983. #define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
  7984. #define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
  7985. #define FW_CSL_LENG_Pos (8U)
  7986. #define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
  7987. #define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
  7988. #define FW_NVDSSA_ADD_Pos (8U)
  7989. #define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
  7990. #define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
  7991. #define FW_NVDSL_LENG_Pos (8U)
  7992. #define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
  7993. #define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
  7994. #define FW_VDSSA_ADD_Pos (6U)
  7995. #define FW_VDSSA_ADD_Msk (0x7FFU << FW_VDSSA_ADD_Pos) /*!< 0x0001FFC0 */
  7996. #define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
  7997. #define FW_VDSL_LENG_Pos (6U)
  7998. #define FW_VDSL_LENG_Msk (0x7FFU << FW_VDSL_LENG_Pos) /*!< 0x0001FFC0 */
  7999. #define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
  8000. /**************************Bit definition for CR register *********************/
  8001. #define FW_CR_FPA_Pos (0U)
  8002. #define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
  8003. #define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
  8004. #define FW_CR_VDS_Pos (1U)
  8005. #define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
  8006. #define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
  8007. #define FW_CR_VDE_Pos (2U)
  8008. #define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
  8009. #define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
  8010. /******************************************************************************/
  8011. /* */
  8012. /* Power Control */
  8013. /* */
  8014. /******************************************************************************/
  8015. /******************** Bit definition for PWR_CR1 register ********************/
  8016. #define PWR_CR1_LPR_Pos (14U)
  8017. #define PWR_CR1_LPR_Msk (0x1U << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
  8018. #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
  8019. #define PWR_CR1_VOS_Pos (9U)
  8020. #define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
  8021. #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
  8022. #define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
  8023. #define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
  8024. #define PWR_CR1_DBP_Pos (8U)
  8025. #define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
  8026. #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
  8027. #define PWR_CR1_LPMS_Pos (0U)
  8028. #define PWR_CR1_LPMS_Msk (0x7U << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
  8029. #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
  8030. #define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
  8031. #define PWR_CR1_LPMS_STOP1_Pos (0U)
  8032. #define PWR_CR1_LPMS_STOP1_Msk (0x1U << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
  8033. #define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
  8034. #define PWR_CR1_LPMS_STOP2_Pos (1U)
  8035. #define PWR_CR1_LPMS_STOP2_Msk (0x1U << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */
  8036. #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
  8037. #define PWR_CR1_LPMS_STANDBY_Pos (0U)
  8038. #define PWR_CR1_LPMS_STANDBY_Msk (0x3U << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
  8039. #define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
  8040. #define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
  8041. #define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
  8042. #define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
  8043. /******************** Bit definition for PWR_CR2 register ********************/
  8044. #define PWR_CR2_USV_Pos (10U)
  8045. #define PWR_CR2_USV_Msk (0x1U << PWR_CR2_USV_Pos) /*!< 0x00000400 */
  8046. #define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */
  8047. /*!< PVME Peripheral Voltage Monitor Enable */
  8048. #define PWR_CR2_PVME_Pos (6U)
  8049. #define PWR_CR2_PVME_Msk (0x3U << PWR_CR2_PVME_Pos) /*!< 0x000000C0 */
  8050. #define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
  8051. #define PWR_CR2_PVME4_Pos (7U)
  8052. #define PWR_CR2_PVME4_Msk (0x1U << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
  8053. #define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
  8054. #define PWR_CR2_PVME3_Pos (6U)
  8055. #define PWR_CR2_PVME3_Msk (0x1U << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
  8056. #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
  8057. /*!< PVD level configuration */
  8058. #define PWR_CR2_PLS_Pos (1U)
  8059. #define PWR_CR2_PLS_Msk (0x7U << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
  8060. #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
  8061. #define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
  8062. #define PWR_CR2_PLS_LEV1_Pos (1U)
  8063. #define PWR_CR2_PLS_LEV1_Msk (0x1U << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
  8064. #define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
  8065. #define PWR_CR2_PLS_LEV2_Pos (2U)
  8066. #define PWR_CR2_PLS_LEV2_Msk (0x1U << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
  8067. #define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
  8068. #define PWR_CR2_PLS_LEV3_Pos (1U)
  8069. #define PWR_CR2_PLS_LEV3_Msk (0x3U << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
  8070. #define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
  8071. #define PWR_CR2_PLS_LEV4_Pos (3U)
  8072. #define PWR_CR2_PLS_LEV4_Msk (0x1U << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
  8073. #define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
  8074. #define PWR_CR2_PLS_LEV5_Pos (1U)
  8075. #define PWR_CR2_PLS_LEV5_Msk (0x5U << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
  8076. #define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
  8077. #define PWR_CR2_PLS_LEV6_Pos (2U)
  8078. #define PWR_CR2_PLS_LEV6_Msk (0x3U << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
  8079. #define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
  8080. #define PWR_CR2_PLS_LEV7_Pos (1U)
  8081. #define PWR_CR2_PLS_LEV7_Msk (0x7U << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
  8082. #define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
  8083. #define PWR_CR2_PVDE_Pos (0U)
  8084. #define PWR_CR2_PVDE_Msk (0x1U << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
  8085. #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
  8086. /******************** Bit definition for PWR_CR3 register ********************/
  8087. #define PWR_CR3_EIWUL_Pos (15U)
  8088. #define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
  8089. #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
  8090. #define PWR_CR3_APC_Pos (10U)
  8091. #define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
  8092. #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
  8093. #define PWR_CR3_RRS_Pos (8U)
  8094. #define PWR_CR3_RRS_Msk (0x1U << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
  8095. #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
  8096. #define PWR_CR3_EWUP5_Pos (4U)
  8097. #define PWR_CR3_EWUP5_Msk (0x1U << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
  8098. #define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
  8099. #define PWR_CR3_EWUP4_Pos (3U)
  8100. #define PWR_CR3_EWUP4_Msk (0x1U << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
  8101. #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
  8102. #define PWR_CR3_EWUP3_Pos (2U)
  8103. #define PWR_CR3_EWUP3_Msk (0x1U << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
  8104. #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
  8105. #define PWR_CR3_EWUP2_Pos (1U)
  8106. #define PWR_CR3_EWUP2_Msk (0x1U << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
  8107. #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
  8108. #define PWR_CR3_EWUP1_Pos (0U)
  8109. #define PWR_CR3_EWUP1_Msk (0x1U << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
  8110. #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
  8111. #define PWR_CR3_EWUP_Pos (0U)
  8112. #define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
  8113. #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
  8114. /* Legacy defines */
  8115. #define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
  8116. #define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
  8117. #define PWR_CR3_EIWF PWR_CR3_EIWUL
  8118. /******************** Bit definition for PWR_CR4 register ********************/
  8119. #define PWR_CR4_VBRS_Pos (9U)
  8120. #define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
  8121. #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
  8122. #define PWR_CR4_VBE_Pos (8U)
  8123. #define PWR_CR4_VBE_Msk (0x1U << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
  8124. #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
  8125. #define PWR_CR4_WP5_Pos (4U)
  8126. #define PWR_CR4_WP5_Msk (0x1U << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
  8127. #define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
  8128. #define PWR_CR4_WP4_Pos (3U)
  8129. #define PWR_CR4_WP4_Msk (0x1U << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
  8130. #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
  8131. #define PWR_CR4_WP3_Pos (2U)
  8132. #define PWR_CR4_WP3_Msk (0x1U << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
  8133. #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
  8134. #define PWR_CR4_WP2_Pos (1U)
  8135. #define PWR_CR4_WP2_Msk (0x1U << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
  8136. #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
  8137. #define PWR_CR4_WP1_Pos (0U)
  8138. #define PWR_CR4_WP1_Msk (0x1U << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
  8139. #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
  8140. /******************** Bit definition for PWR_SR1 register ********************/
  8141. #define PWR_SR1_WUFI_Pos (15U)
  8142. #define PWR_SR1_WUFI_Msk (0x1U << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
  8143. #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
  8144. #define PWR_SR1_SBF_Pos (8U)
  8145. #define PWR_SR1_SBF_Msk (0x1U << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
  8146. #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
  8147. #define PWR_SR1_WUF_Pos (0U)
  8148. #define PWR_SR1_WUF_Msk (0x1FU << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
  8149. #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
  8150. #define PWR_SR1_WUF5_Pos (4U)
  8151. #define PWR_SR1_WUF5_Msk (0x1U << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
  8152. #define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
  8153. #define PWR_SR1_WUF4_Pos (3U)
  8154. #define PWR_SR1_WUF4_Msk (0x1U << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
  8155. #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
  8156. #define PWR_SR1_WUF3_Pos (2U)
  8157. #define PWR_SR1_WUF3_Msk (0x1U << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
  8158. #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
  8159. #define PWR_SR1_WUF2_Pos (1U)
  8160. #define PWR_SR1_WUF2_Msk (0x1U << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
  8161. #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
  8162. #define PWR_SR1_WUF1_Pos (0U)
  8163. #define PWR_SR1_WUF1_Msk (0x1U << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
  8164. #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
  8165. /******************** Bit definition for PWR_SR2 register ********************/
  8166. #define PWR_SR2_PVMO4_Pos (15U)
  8167. #define PWR_SR2_PVMO4_Msk (0x1U << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
  8168. #define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
  8169. #define PWR_SR2_PVMO3_Pos (14U)
  8170. #define PWR_SR2_PVMO3_Msk (0x1U << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
  8171. #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
  8172. #define PWR_SR2_PVDO_Pos (11U)
  8173. #define PWR_SR2_PVDO_Msk (0x1U << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
  8174. #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
  8175. #define PWR_SR2_VOSF_Pos (10U)
  8176. #define PWR_SR2_VOSF_Msk (0x1U << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
  8177. #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
  8178. #define PWR_SR2_REGLPF_Pos (9U)
  8179. #define PWR_SR2_REGLPF_Msk (0x1U << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
  8180. #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
  8181. #define PWR_SR2_REGLPS_Pos (8U)
  8182. #define PWR_SR2_REGLPS_Msk (0x1U << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
  8183. #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
  8184. /******************** Bit definition for PWR_SCR register ********************/
  8185. #define PWR_SCR_CSBF_Pos (8U)
  8186. #define PWR_SCR_CSBF_Msk (0x1U << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
  8187. #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
  8188. #define PWR_SCR_CWUF_Pos (0U)
  8189. #define PWR_SCR_CWUF_Msk (0x1FU << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
  8190. #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
  8191. #define PWR_SCR_CWUF5_Pos (4U)
  8192. #define PWR_SCR_CWUF5_Msk (0x1U << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
  8193. #define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
  8194. #define PWR_SCR_CWUF4_Pos (3U)
  8195. #define PWR_SCR_CWUF4_Msk (0x1U << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
  8196. #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
  8197. #define PWR_SCR_CWUF3_Pos (2U)
  8198. #define PWR_SCR_CWUF3_Msk (0x1U << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
  8199. #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
  8200. #define PWR_SCR_CWUF2_Pos (1U)
  8201. #define PWR_SCR_CWUF2_Msk (0x1U << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
  8202. #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
  8203. #define PWR_SCR_CWUF1_Pos (0U)
  8204. #define PWR_SCR_CWUF1_Msk (0x1U << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
  8205. #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
  8206. /******************** Bit definition for PWR_PUCRA register ********************/
  8207. #define PWR_PUCRA_PA15_Pos (15U)
  8208. #define PWR_PUCRA_PA15_Msk (0x1U << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
  8209. #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
  8210. #define PWR_PUCRA_PA13_Pos (13U)
  8211. #define PWR_PUCRA_PA13_Msk (0x1U << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
  8212. #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
  8213. #define PWR_PUCRA_PA12_Pos (12U)
  8214. #define PWR_PUCRA_PA12_Msk (0x1U << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
  8215. #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
  8216. #define PWR_PUCRA_PA11_Pos (11U)
  8217. #define PWR_PUCRA_PA11_Msk (0x1U << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
  8218. #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
  8219. #define PWR_PUCRA_PA10_Pos (10U)
  8220. #define PWR_PUCRA_PA10_Msk (0x1U << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
  8221. #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
  8222. #define PWR_PUCRA_PA9_Pos (9U)
  8223. #define PWR_PUCRA_PA9_Msk (0x1U << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
  8224. #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
  8225. #define PWR_PUCRA_PA8_Pos (8U)
  8226. #define PWR_PUCRA_PA8_Msk (0x1U << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
  8227. #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
  8228. #define PWR_PUCRA_PA7_Pos (7U)
  8229. #define PWR_PUCRA_PA7_Msk (0x1U << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
  8230. #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
  8231. #define PWR_PUCRA_PA6_Pos (6U)
  8232. #define PWR_PUCRA_PA6_Msk (0x1U << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
  8233. #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
  8234. #define PWR_PUCRA_PA5_Pos (5U)
  8235. #define PWR_PUCRA_PA5_Msk (0x1U << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
  8236. #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
  8237. #define PWR_PUCRA_PA4_Pos (4U)
  8238. #define PWR_PUCRA_PA4_Msk (0x1U << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
  8239. #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
  8240. #define PWR_PUCRA_PA3_Pos (3U)
  8241. #define PWR_PUCRA_PA3_Msk (0x1U << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
  8242. #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
  8243. #define PWR_PUCRA_PA2_Pos (2U)
  8244. #define PWR_PUCRA_PA2_Msk (0x1U << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
  8245. #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
  8246. #define PWR_PUCRA_PA1_Pos (1U)
  8247. #define PWR_PUCRA_PA1_Msk (0x1U << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
  8248. #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
  8249. #define PWR_PUCRA_PA0_Pos (0U)
  8250. #define PWR_PUCRA_PA0_Msk (0x1U << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
  8251. #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
  8252. /******************** Bit definition for PWR_PDCRA register ********************/
  8253. #define PWR_PDCRA_PA14_Pos (14U)
  8254. #define PWR_PDCRA_PA14_Msk (0x1U << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
  8255. #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
  8256. #define PWR_PDCRA_PA12_Pos (12U)
  8257. #define PWR_PDCRA_PA12_Msk (0x1U << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
  8258. #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
  8259. #define PWR_PDCRA_PA11_Pos (11U)
  8260. #define PWR_PDCRA_PA11_Msk (0x1U << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
  8261. #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
  8262. #define PWR_PDCRA_PA10_Pos (10U)
  8263. #define PWR_PDCRA_PA10_Msk (0x1U << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
  8264. #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
  8265. #define PWR_PDCRA_PA9_Pos (9U)
  8266. #define PWR_PDCRA_PA9_Msk (0x1U << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
  8267. #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
  8268. #define PWR_PDCRA_PA8_Pos (8U)
  8269. #define PWR_PDCRA_PA8_Msk (0x1U << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
  8270. #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
  8271. #define PWR_PDCRA_PA7_Pos (7U)
  8272. #define PWR_PDCRA_PA7_Msk (0x1U << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
  8273. #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
  8274. #define PWR_PDCRA_PA6_Pos (6U)
  8275. #define PWR_PDCRA_PA6_Msk (0x1U << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
  8276. #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
  8277. #define PWR_PDCRA_PA5_Pos (5U)
  8278. #define PWR_PDCRA_PA5_Msk (0x1U << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
  8279. #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
  8280. #define PWR_PDCRA_PA4_Pos (4U)
  8281. #define PWR_PDCRA_PA4_Msk (0x1U << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
  8282. #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
  8283. #define PWR_PDCRA_PA3_Pos (3U)
  8284. #define PWR_PDCRA_PA3_Msk (0x1U << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
  8285. #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
  8286. #define PWR_PDCRA_PA2_Pos (2U)
  8287. #define PWR_PDCRA_PA2_Msk (0x1U << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
  8288. #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
  8289. #define PWR_PDCRA_PA1_Pos (1U)
  8290. #define PWR_PDCRA_PA1_Msk (0x1U << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
  8291. #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
  8292. #define PWR_PDCRA_PA0_Pos (0U)
  8293. #define PWR_PDCRA_PA0_Msk (0x1U << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
  8294. #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
  8295. /******************** Bit definition for PWR_PUCRB register ********************/
  8296. #define PWR_PUCRB_PB7_Pos (7U)
  8297. #define PWR_PUCRB_PB7_Msk (0x1U << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
  8298. #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
  8299. #define PWR_PUCRB_PB6_Pos (6U)
  8300. #define PWR_PUCRB_PB6_Msk (0x1U << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
  8301. #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
  8302. #define PWR_PUCRB_PB5_Pos (5U)
  8303. #define PWR_PUCRB_PB5_Msk (0x1U << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
  8304. #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
  8305. #define PWR_PUCRB_PB4_Pos (4U)
  8306. #define PWR_PUCRB_PB4_Msk (0x1U << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
  8307. #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
  8308. #define PWR_PUCRB_PB3_Pos (3U)
  8309. #define PWR_PUCRB_PB3_Msk (0x1U << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
  8310. #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
  8311. #define PWR_PUCRB_PB1_Pos (1U)
  8312. #define PWR_PUCRB_PB1_Msk (0x1U << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
  8313. #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
  8314. #define PWR_PUCRB_PB0_Pos (0U)
  8315. #define PWR_PUCRB_PB0_Msk (0x1U << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
  8316. #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
  8317. /******************** Bit definition for PWR_PDCRB register ********************/
  8318. #define PWR_PDCRB_PB7_Pos (7U)
  8319. #define PWR_PDCRB_PB7_Msk (0x1U << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
  8320. #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
  8321. #define PWR_PDCRB_PB6_Pos (6U)
  8322. #define PWR_PDCRB_PB6_Msk (0x1U << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
  8323. #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
  8324. #define PWR_PDCRB_PB5_Pos (5U)
  8325. #define PWR_PDCRB_PB5_Msk (0x1U << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
  8326. #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
  8327. #define PWR_PDCRB_PB3_Pos (3U)
  8328. #define PWR_PDCRB_PB3_Msk (0x1U << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
  8329. #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
  8330. #define PWR_PDCRB_PB1_Pos (1U)
  8331. #define PWR_PDCRB_PB1_Msk (0x1U << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
  8332. #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
  8333. #define PWR_PDCRB_PB0_Pos (0U)
  8334. #define PWR_PDCRB_PB0_Msk (0x1U << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
  8335. #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
  8336. /******************** Bit definition for PWR_PUCRC register ********************/
  8337. #define PWR_PUCRC_PC15_Pos (15U)
  8338. #define PWR_PUCRC_PC15_Msk (0x1U << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
  8339. #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
  8340. #define PWR_PUCRC_PC14_Pos (14U)
  8341. #define PWR_PUCRC_PC14_Msk (0x1U << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
  8342. #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
  8343. /******************** Bit definition for PWR_PDCRC register ********************/
  8344. #define PWR_PDCRC_PC15_Pos (15U)
  8345. #define PWR_PDCRC_PC15_Msk (0x1U << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
  8346. #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
  8347. #define PWR_PDCRC_PC14_Pos (14U)
  8348. #define PWR_PDCRC_PC14_Msk (0x1U << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
  8349. #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
  8350. /******************** Bit definition for PWR_PUCRH register ********************/
  8351. #define PWR_PUCRH_PH3_Pos (3U)
  8352. #define PWR_PUCRH_PH3_Msk (0x1U << PWR_PUCRH_PH3_Pos) /*!< 0x00000008 */
  8353. #define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Port PH3 Pull-Up set */
  8354. /******************** Bit definition for PWR_PDCRH register ********************/
  8355. #define PWR_PDCRH_PH3_Pos (3U)
  8356. #define PWR_PDCRH_PH3_Msk (0x1U << PWR_PDCRH_PH3_Pos) /*!< 0x00000008 */
  8357. #define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Port PH3 Pull-Down set */
  8358. /******************************************************************************/
  8359. /* */
  8360. /* Reset and Clock Control */
  8361. /* */
  8362. /******************************************************************************/
  8363. /*
  8364. * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
  8365. */
  8366. #define RCC_HSI48_SUPPORT
  8367. #define RCC_PLLP_DIV_2_31_SUPPORT
  8368. #define RCC_PLLSAI1P_DIV_2_31_SUPPORT
  8369. /******************** Bit definition for RCC_CR register ********************/
  8370. #define RCC_CR_MSION_Pos (0U)
  8371. #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000001 */
  8372. #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */
  8373. #define RCC_CR_MSIRDY_Pos (1U)
  8374. #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */
  8375. #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
  8376. #define RCC_CR_MSIPLLEN_Pos (2U)
  8377. #define RCC_CR_MSIPLLEN_Msk (0x1U << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */
  8378. #define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */
  8379. #define RCC_CR_MSIRGSEL_Pos (3U)
  8380. #define RCC_CR_MSIRGSEL_Msk (0x1U << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */
  8381. #define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */
  8382. /*!< MSIRANGE configuration : 12 frequency ranges available */
  8383. #define RCC_CR_MSIRANGE_Pos (4U)
  8384. #define RCC_CR_MSIRANGE_Msk (0xFU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */
  8385. #define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */
  8386. #define RCC_CR_MSIRANGE_0 (0x0U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */
  8387. #define RCC_CR_MSIRANGE_1 (0x1U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */
  8388. #define RCC_CR_MSIRANGE_2 (0x2U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */
  8389. #define RCC_CR_MSIRANGE_3 (0x3U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */
  8390. #define RCC_CR_MSIRANGE_4 (0x4U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */
  8391. #define RCC_CR_MSIRANGE_5 (0x5U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */
  8392. #define RCC_CR_MSIRANGE_6 (0x6U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */
  8393. #define RCC_CR_MSIRANGE_7 (0x7U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */
  8394. #define RCC_CR_MSIRANGE_8 (0x8U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */
  8395. #define RCC_CR_MSIRANGE_9 (0x9U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */
  8396. #define RCC_CR_MSIRANGE_10 (0xAU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */
  8397. #define RCC_CR_MSIRANGE_11 (0xBU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */
  8398. #define RCC_CR_HSION_Pos (8U)
  8399. #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000100 */
  8400. #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
  8401. #define RCC_CR_HSIKERON_Pos (9U)
  8402. #define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
  8403. #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
  8404. #define RCC_CR_HSIRDY_Pos (10U)
  8405. #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
  8406. #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
  8407. #define RCC_CR_HSIASFS_Pos (11U)
  8408. #define RCC_CR_HSIASFS_Msk (0x1U << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */
  8409. #define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */
  8410. #define RCC_CR_HSEON_Pos (16U)
  8411. #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
  8412. #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
  8413. #define RCC_CR_HSERDY_Pos (17U)
  8414. #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
  8415. #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
  8416. #define RCC_CR_HSEBYP_Pos (18U)
  8417. #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
  8418. #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
  8419. #define RCC_CR_CSSON_Pos (19U)
  8420. #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
  8421. #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
  8422. #define RCC_CR_PLLON_Pos (24U)
  8423. #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
  8424. #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
  8425. #define RCC_CR_PLLRDY_Pos (25U)
  8426. #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
  8427. #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
  8428. #define RCC_CR_PLLSAI1ON_Pos (26U)
  8429. #define RCC_CR_PLLSAI1ON_Msk (0x1U << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
  8430. #define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
  8431. #define RCC_CR_PLLSAI1RDY_Pos (27U)
  8432. #define RCC_CR_PLLSAI1RDY_Msk (0x1U << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */
  8433. #define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */
  8434. /******************** Bit definition for RCC_ICSCR register ***************/
  8435. /*!< MSICAL configuration */
  8436. #define RCC_ICSCR_MSICAL_Pos (0U)
  8437. #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */
  8438. #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */
  8439. #define RCC_ICSCR_MSICAL_0 (0x01U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */
  8440. #define RCC_ICSCR_MSICAL_1 (0x02U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */
  8441. #define RCC_ICSCR_MSICAL_2 (0x04U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */
  8442. #define RCC_ICSCR_MSICAL_3 (0x08U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */
  8443. #define RCC_ICSCR_MSICAL_4 (0x10U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */
  8444. #define RCC_ICSCR_MSICAL_5 (0x20U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */
  8445. #define RCC_ICSCR_MSICAL_6 (0x40U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */
  8446. #define RCC_ICSCR_MSICAL_7 (0x80U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */
  8447. /*!< MSITRIM configuration */
  8448. #define RCC_ICSCR_MSITRIM_Pos (8U)
  8449. #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
  8450. #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */
  8451. #define RCC_ICSCR_MSITRIM_0 (0x01U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
  8452. #define RCC_ICSCR_MSITRIM_1 (0x02U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
  8453. #define RCC_ICSCR_MSITRIM_2 (0x04U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
  8454. #define RCC_ICSCR_MSITRIM_3 (0x08U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
  8455. #define RCC_ICSCR_MSITRIM_4 (0x10U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
  8456. #define RCC_ICSCR_MSITRIM_5 (0x20U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
  8457. #define RCC_ICSCR_MSITRIM_6 (0x40U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
  8458. #define RCC_ICSCR_MSITRIM_7 (0x80U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
  8459. /*!< HSICAL configuration */
  8460. #define RCC_ICSCR_HSICAL_Pos (16U)
  8461. #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
  8462. #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
  8463. #define RCC_ICSCR_HSICAL_0 (0x01U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
  8464. #define RCC_ICSCR_HSICAL_1 (0x02U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
  8465. #define RCC_ICSCR_HSICAL_2 (0x04U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
  8466. #define RCC_ICSCR_HSICAL_3 (0x08U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
  8467. #define RCC_ICSCR_HSICAL_4 (0x10U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
  8468. #define RCC_ICSCR_HSICAL_5 (0x20U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
  8469. #define RCC_ICSCR_HSICAL_6 (0x40U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
  8470. #define RCC_ICSCR_HSICAL_7 (0x80U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
  8471. /*!< HSITRIM configuration */
  8472. #define RCC_ICSCR_HSITRIM_Pos (24U)
  8473. #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
  8474. #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
  8475. #define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
  8476. #define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
  8477. #define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
  8478. #define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
  8479. #define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
  8480. /******************** Bit definition for RCC_CFGR register ******************/
  8481. /*!< SW configuration */
  8482. #define RCC_CFGR_SW_Pos (0U)
  8483. #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
  8484. #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
  8485. #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
  8486. #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
  8487. #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI oscillator selection as system clock */
  8488. #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
  8489. #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
  8490. #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
  8491. /*!< SWS configuration */
  8492. #define RCC_CFGR_SWS_Pos (2U)
  8493. #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
  8494. #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
  8495. #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
  8496. #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
  8497. #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
  8498. #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
  8499. #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
  8500. #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
  8501. /*!< HPRE configuration */
  8502. #define RCC_CFGR_HPRE_Pos (4U)
  8503. #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
  8504. #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
  8505. #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
  8506. #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
  8507. #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
  8508. #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
  8509. #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
  8510. #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
  8511. #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
  8512. #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
  8513. #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
  8514. #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
  8515. #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
  8516. #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
  8517. #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
  8518. /*!< PPRE1 configuration */
  8519. #define RCC_CFGR_PPRE1_Pos (8U)
  8520. #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
  8521. #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
  8522. #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
  8523. #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
  8524. #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
  8525. #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
  8526. #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
  8527. #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
  8528. #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
  8529. #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
  8530. /*!< PPRE2 configuration */
  8531. #define RCC_CFGR_PPRE2_Pos (11U)
  8532. #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
  8533. #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
  8534. #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
  8535. #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
  8536. #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
  8537. #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
  8538. #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
  8539. #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
  8540. #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
  8541. #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
  8542. #define RCC_CFGR_STOPWUCK_Pos (15U)
  8543. #define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
  8544. #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
  8545. /*!< MCOSEL configuration */
  8546. #define RCC_CFGR_MCOSEL_Pos (24U)
  8547. #define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
  8548. #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
  8549. #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
  8550. #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
  8551. #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
  8552. #define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
  8553. #define RCC_CFGR_MCOPRE_Pos (28U)
  8554. #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
  8555. #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
  8556. #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
  8557. #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
  8558. #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
  8559. #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
  8560. #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
  8561. #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
  8562. #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
  8563. #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
  8564. /* Legacy aliases */
  8565. #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
  8566. #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
  8567. #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
  8568. #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
  8569. #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
  8570. #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
  8571. /******************** Bit definition for RCC_PLLCFGR register ***************/
  8572. #define RCC_PLLCFGR_PLLSRC_Pos (0U)
  8573. #define RCC_PLLCFGR_PLLSRC_Msk (0x3U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
  8574. #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
  8575. #define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
  8576. #define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
  8577. #define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */
  8578. #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
  8579. #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
  8580. #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
  8581. #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
  8582. #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
  8583. #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
  8584. #define RCC_PLLCFGR_PLLM_Pos (4U)
  8585. #define RCC_PLLCFGR_PLLM_Msk (0x7U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
  8586. #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
  8587. #define RCC_PLLCFGR_PLLM_0 (0x1U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
  8588. #define RCC_PLLCFGR_PLLM_1 (0x2U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
  8589. #define RCC_PLLCFGR_PLLM_2 (0x4U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
  8590. #define RCC_PLLCFGR_PLLN_Pos (8U)
  8591. #define RCC_PLLCFGR_PLLN_Msk (0x7FU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
  8592. #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
  8593. #define RCC_PLLCFGR_PLLN_0 (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
  8594. #define RCC_PLLCFGR_PLLN_1 (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
  8595. #define RCC_PLLCFGR_PLLN_2 (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
  8596. #define RCC_PLLCFGR_PLLN_3 (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
  8597. #define RCC_PLLCFGR_PLLN_4 (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
  8598. #define RCC_PLLCFGR_PLLN_5 (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
  8599. #define RCC_PLLCFGR_PLLN_6 (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
  8600. #define RCC_PLLCFGR_PLLPEN_Pos (16U)
  8601. #define RCC_PLLCFGR_PLLPEN_Msk (0x1U << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
  8602. #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
  8603. #define RCC_PLLCFGR_PLLP_Pos (17U)
  8604. #define RCC_PLLCFGR_PLLP_Msk (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
  8605. #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
  8606. #define RCC_PLLCFGR_PLLQEN_Pos (20U)
  8607. #define RCC_PLLCFGR_PLLQEN_Msk (0x1U << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
  8608. #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
  8609. #define RCC_PLLCFGR_PLLQ_Pos (21U)
  8610. #define RCC_PLLCFGR_PLLQ_Msk (0x3U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
  8611. #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
  8612. #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
  8613. #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
  8614. #define RCC_PLLCFGR_PLLREN_Pos (24U)
  8615. #define RCC_PLLCFGR_PLLREN_Msk (0x1U << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
  8616. #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
  8617. #define RCC_PLLCFGR_PLLR_Pos (25U)
  8618. #define RCC_PLLCFGR_PLLR_Msk (0x3U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
  8619. #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
  8620. #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
  8621. #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
  8622. #define RCC_PLLCFGR_PLLPDIV_Pos (27U)
  8623. #define RCC_PLLCFGR_PLLPDIV_Msk (0x1FU << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */
  8624. #define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
  8625. #define RCC_PLLCFGR_PLLPDIV_0 (0x01U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */
  8626. #define RCC_PLLCFGR_PLLPDIV_1 (0x02U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */
  8627. #define RCC_PLLCFGR_PLLPDIV_2 (0x04U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */
  8628. #define RCC_PLLCFGR_PLLPDIV_3 (0x08U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */
  8629. #define RCC_PLLCFGR_PLLPDIV_4 (0x10U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */
  8630. /******************** Bit definition for RCC_PLLSAI1CFGR register ************/
  8631. #define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
  8632. #define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
  8633. #define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
  8634. #define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
  8635. #define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
  8636. #define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
  8637. #define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
  8638. #define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
  8639. #define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
  8640. #define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
  8641. #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
  8642. #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
  8643. #define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
  8644. #define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
  8645. #define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
  8646. #define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
  8647. #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
  8648. #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
  8649. #define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
  8650. #define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
  8651. #define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
  8652. #define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
  8653. #define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
  8654. #define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
  8655. #define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
  8656. #define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
  8657. #define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
  8658. #define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
  8659. #define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
  8660. #define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
  8661. #define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
  8662. #define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
  8663. #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos (27U)
  8664. #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk (0x1FU << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */
  8665. #define RCC_PLLSAI1CFGR_PLLSAI1PDIV RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk
  8666. #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */
  8667. #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */
  8668. #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */
  8669. #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */
  8670. #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */
  8671. /******************** Bit definition for RCC_CIER register ******************/
  8672. #define RCC_CIER_LSIRDYIE_Pos (0U)
  8673. #define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
  8674. #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
  8675. #define RCC_CIER_LSERDYIE_Pos (1U)
  8676. #define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
  8677. #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
  8678. #define RCC_CIER_MSIRDYIE_Pos (2U)
  8679. #define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */
  8680. #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
  8681. #define RCC_CIER_HSIRDYIE_Pos (3U)
  8682. #define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
  8683. #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
  8684. #define RCC_CIER_HSERDYIE_Pos (4U)
  8685. #define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
  8686. #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
  8687. #define RCC_CIER_PLLRDYIE_Pos (5U)
  8688. #define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
  8689. #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
  8690. #define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
  8691. #define RCC_CIER_PLLSAI1RDYIE_Msk (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
  8692. #define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
  8693. #define RCC_CIER_LSECSSIE_Pos (9U)
  8694. #define RCC_CIER_LSECSSIE_Msk (0x1U << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
  8695. #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
  8696. #define RCC_CIER_HSI48RDYIE_Pos (10U)
  8697. #define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */
  8698. #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
  8699. /******************** Bit definition for RCC_CIFR register ******************/
  8700. #define RCC_CIFR_LSIRDYF_Pos (0U)
  8701. #define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
  8702. #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
  8703. #define RCC_CIFR_LSERDYF_Pos (1U)
  8704. #define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
  8705. #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
  8706. #define RCC_CIFR_MSIRDYF_Pos (2U)
  8707. #define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */
  8708. #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
  8709. #define RCC_CIFR_HSIRDYF_Pos (3U)
  8710. #define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
  8711. #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
  8712. #define RCC_CIFR_HSERDYF_Pos (4U)
  8713. #define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
  8714. #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
  8715. #define RCC_CIFR_PLLRDYF_Pos (5U)
  8716. #define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
  8717. #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
  8718. #define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
  8719. #define RCC_CIFR_PLLSAI1RDYF_Msk (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
  8720. #define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
  8721. #define RCC_CIFR_CSSF_Pos (8U)
  8722. #define RCC_CIFR_CSSF_Msk (0x1U << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
  8723. #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
  8724. #define RCC_CIFR_LSECSSF_Pos (9U)
  8725. #define RCC_CIFR_LSECSSF_Msk (0x1U << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
  8726. #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
  8727. #define RCC_CIFR_HSI48RDYF_Pos (10U)
  8728. #define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
  8729. #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
  8730. /******************** Bit definition for RCC_CICR register ******************/
  8731. #define RCC_CICR_LSIRDYC_Pos (0U)
  8732. #define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
  8733. #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
  8734. #define RCC_CICR_LSERDYC_Pos (1U)
  8735. #define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
  8736. #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
  8737. #define RCC_CICR_MSIRDYC_Pos (2U)
  8738. #define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */
  8739. #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
  8740. #define RCC_CICR_HSIRDYC_Pos (3U)
  8741. #define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
  8742. #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
  8743. #define RCC_CICR_HSERDYC_Pos (4U)
  8744. #define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
  8745. #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
  8746. #define RCC_CICR_PLLRDYC_Pos (5U)
  8747. #define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
  8748. #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
  8749. #define RCC_CICR_PLLSAI1RDYC_Pos (6U)
  8750. #define RCC_CICR_PLLSAI1RDYC_Msk (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
  8751. #define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
  8752. #define RCC_CICR_CSSC_Pos (8U)
  8753. #define RCC_CICR_CSSC_Msk (0x1U << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
  8754. #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
  8755. #define RCC_CICR_LSECSSC_Pos (9U)
  8756. #define RCC_CICR_LSECSSC_Msk (0x1U << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
  8757. #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
  8758. #define RCC_CICR_HSI48RDYC_Pos (10U)
  8759. #define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
  8760. #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
  8761. /******************** Bit definition for RCC_AHB1RSTR register **************/
  8762. #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
  8763. #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
  8764. #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
  8765. #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
  8766. #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
  8767. #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
  8768. #define RCC_AHB1RSTR_FLASHRST_Pos (8U)
  8769. #define RCC_AHB1RSTR_FLASHRST_Msk (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
  8770. #define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
  8771. #define RCC_AHB1RSTR_CRCRST_Pos (12U)
  8772. #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
  8773. #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
  8774. #define RCC_AHB1RSTR_TSCRST_Pos (16U)
  8775. #define RCC_AHB1RSTR_TSCRST_Msk (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
  8776. #define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
  8777. /******************** Bit definition for RCC_AHB2RSTR register **************/
  8778. #define RCC_AHB2RSTR_GPIOARST_Pos (0U)
  8779. #define RCC_AHB2RSTR_GPIOARST_Msk (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
  8780. #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
  8781. #define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
  8782. #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
  8783. #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
  8784. #define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
  8785. #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
  8786. #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
  8787. #define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
  8788. #define RCC_AHB2RSTR_GPIOHRST_Msk (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
  8789. #define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
  8790. #define RCC_AHB2RSTR_ADCRST_Pos (13U)
  8791. #define RCC_AHB2RSTR_ADCRST_Msk (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
  8792. #define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
  8793. #define RCC_AHB2RSTR_RNGRST_Pos (18U)
  8794. #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
  8795. #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
  8796. /******************** Bit definition for RCC_AHB3RSTR register **************/
  8797. #define RCC_AHB3RSTR_QSPIRST_Pos (8U)
  8798. #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
  8799. #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
  8800. /******************** Bit definition for RCC_APB1RSTR1 register **************/
  8801. #define RCC_APB1RSTR1_TIM2RST_Pos (0U)
  8802. #define RCC_APB1RSTR1_TIM2RST_Msk (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
  8803. #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
  8804. #define RCC_APB1RSTR1_TIM6RST_Pos (4U)
  8805. #define RCC_APB1RSTR1_TIM6RST_Msk (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
  8806. #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
  8807. #define RCC_APB1RSTR1_TIM7RST_Pos (5U)
  8808. #define RCC_APB1RSTR1_TIM7RST_Msk (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
  8809. #define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
  8810. #define RCC_APB1RSTR1_SPI3RST_Pos (15U)
  8811. #define RCC_APB1RSTR1_SPI3RST_Msk (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
  8812. #define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
  8813. #define RCC_APB1RSTR1_USART2RST_Pos (17U)
  8814. #define RCC_APB1RSTR1_USART2RST_Msk (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
  8815. #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
  8816. #define RCC_APB1RSTR1_I2C1RST_Pos (21U)
  8817. #define RCC_APB1RSTR1_I2C1RST_Msk (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
  8818. #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
  8819. #define RCC_APB1RSTR1_I2C3RST_Pos (23U)
  8820. #define RCC_APB1RSTR1_I2C3RST_Msk (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
  8821. #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
  8822. #define RCC_APB1RSTR1_CRSRST_Pos (24U)
  8823. #define RCC_APB1RSTR1_CRSRST_Msk (0x1U << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */
  8824. #define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
  8825. #define RCC_APB1RSTR1_CAN1RST_Pos (25U)
  8826. #define RCC_APB1RSTR1_CAN1RST_Msk (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
  8827. #define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
  8828. #define RCC_APB1RSTR1_USBFSRST_Pos (26U)
  8829. #define RCC_APB1RSTR1_USBFSRST_Msk (0x1U << RCC_APB1RSTR1_USBFSRST_Pos) /*!< 0x04000000 */
  8830. #define RCC_APB1RSTR1_USBFSRST RCC_APB1RSTR1_USBFSRST_Msk
  8831. #define RCC_APB1RSTR1_PWRRST_Pos (28U)
  8832. #define RCC_APB1RSTR1_PWRRST_Msk (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
  8833. #define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
  8834. #define RCC_APB1RSTR1_DAC1RST_Pos (29U)
  8835. #define RCC_APB1RSTR1_DAC1RST_Msk (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
  8836. #define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
  8837. #define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
  8838. #define RCC_APB1RSTR1_OPAMPRST_Msk (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
  8839. #define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
  8840. #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
  8841. #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
  8842. #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
  8843. /******************** Bit definition for RCC_APB1RSTR2 register **************/
  8844. #define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
  8845. #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
  8846. #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
  8847. #define RCC_APB1RSTR2_SWPMI1RST_Pos (2U)
  8848. #define RCC_APB1RSTR2_SWPMI1RST_Msk (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
  8849. #define RCC_APB1RSTR2_SWPMI1RST RCC_APB1RSTR2_SWPMI1RST_Msk
  8850. #define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
  8851. #define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
  8852. #define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
  8853. /******************** Bit definition for RCC_APB2RSTR register **************/
  8854. #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
  8855. #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
  8856. #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
  8857. #define RCC_APB2RSTR_TIM1RST_Pos (11U)
  8858. #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
  8859. #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
  8860. #define RCC_APB2RSTR_SPI1RST_Pos (12U)
  8861. #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
  8862. #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
  8863. #define RCC_APB2RSTR_USART1RST_Pos (14U)
  8864. #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
  8865. #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
  8866. #define RCC_APB2RSTR_TIM15RST_Pos (16U)
  8867. #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
  8868. #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
  8869. #define RCC_APB2RSTR_TIM16RST_Pos (17U)
  8870. #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
  8871. #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
  8872. #define RCC_APB2RSTR_SAI1RST_Pos (21U)
  8873. #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
  8874. #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
  8875. /******************** Bit definition for RCC_AHB1ENR register ***************/
  8876. #define RCC_AHB1ENR_DMA1EN_Pos (0U)
  8877. #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
  8878. #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
  8879. #define RCC_AHB1ENR_DMA2EN_Pos (1U)
  8880. #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
  8881. #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
  8882. #define RCC_AHB1ENR_FLASHEN_Pos (8U)
  8883. #define RCC_AHB1ENR_FLASHEN_Msk (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
  8884. #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
  8885. #define RCC_AHB1ENR_CRCEN_Pos (12U)
  8886. #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
  8887. #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
  8888. #define RCC_AHB1ENR_TSCEN_Pos (16U)
  8889. #define RCC_AHB1ENR_TSCEN_Msk (0x1U << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
  8890. #define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
  8891. /******************** Bit definition for RCC_AHB2ENR register ***************/
  8892. #define RCC_AHB2ENR_GPIOAEN_Pos (0U)
  8893. #define RCC_AHB2ENR_GPIOAEN_Msk (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
  8894. #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
  8895. #define RCC_AHB2ENR_GPIOBEN_Pos (1U)
  8896. #define RCC_AHB2ENR_GPIOBEN_Msk (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
  8897. #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
  8898. #define RCC_AHB2ENR_GPIOCEN_Pos (2U)
  8899. #define RCC_AHB2ENR_GPIOCEN_Msk (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
  8900. #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
  8901. #define RCC_AHB2ENR_GPIOHEN_Pos (7U)
  8902. #define RCC_AHB2ENR_GPIOHEN_Msk (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
  8903. #define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
  8904. #define RCC_AHB2ENR_ADCEN_Pos (13U)
  8905. #define RCC_AHB2ENR_ADCEN_Msk (0x1U << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */
  8906. #define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
  8907. #define RCC_AHB2ENR_RNGEN_Pos (18U)
  8908. #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
  8909. #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
  8910. /******************** Bit definition for RCC_AHB3ENR register ***************/
  8911. #define RCC_AHB3ENR_QSPIEN_Pos (8U)
  8912. #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
  8913. #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
  8914. /******************** Bit definition for RCC_APB1ENR1 register ***************/
  8915. #define RCC_APB1ENR1_TIM2EN_Pos (0U)
  8916. #define RCC_APB1ENR1_TIM2EN_Msk (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
  8917. #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
  8918. #define RCC_APB1ENR1_TIM6EN_Pos (4U)
  8919. #define RCC_APB1ENR1_TIM6EN_Msk (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
  8920. #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
  8921. #define RCC_APB1ENR1_TIM7EN_Pos (5U)
  8922. #define RCC_APB1ENR1_TIM7EN_Msk (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
  8923. #define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
  8924. #define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
  8925. #define RCC_APB1ENR1_RTCAPBEN_Msk (0x1U << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
  8926. #define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
  8927. #define RCC_APB1ENR1_WWDGEN_Pos (11U)
  8928. #define RCC_APB1ENR1_WWDGEN_Msk (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
  8929. #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
  8930. #define RCC_APB1ENR1_SPI3EN_Pos (15U)
  8931. #define RCC_APB1ENR1_SPI3EN_Msk (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
  8932. #define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
  8933. #define RCC_APB1ENR1_USART2EN_Pos (17U)
  8934. #define RCC_APB1ENR1_USART2EN_Msk (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
  8935. #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
  8936. #define RCC_APB1ENR1_I2C1EN_Pos (21U)
  8937. #define RCC_APB1ENR1_I2C1EN_Msk (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
  8938. #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
  8939. #define RCC_APB1ENR1_I2C3EN_Pos (23U)
  8940. #define RCC_APB1ENR1_I2C3EN_Msk (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
  8941. #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
  8942. #define RCC_APB1ENR1_CRSEN_Pos (24U)
  8943. #define RCC_APB1ENR1_CRSEN_Msk (0x1U << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x01000000 */
  8944. #define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
  8945. #define RCC_APB1ENR1_CAN1EN_Pos (25U)
  8946. #define RCC_APB1ENR1_CAN1EN_Msk (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
  8947. #define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
  8948. #define RCC_APB1ENR1_USBFSEN_Pos (26U)
  8949. #define RCC_APB1ENR1_USBFSEN_Msk (0x1U << RCC_APB1ENR1_USBFSEN_Pos) /*!< 0x04000000 */
  8950. #define RCC_APB1ENR1_USBFSEN RCC_APB1ENR1_USBFSEN_Msk
  8951. #define RCC_APB1ENR1_PWREN_Pos (28U)
  8952. #define RCC_APB1ENR1_PWREN_Msk (0x1U << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
  8953. #define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
  8954. #define RCC_APB1ENR1_DAC1EN_Pos (29U)
  8955. #define RCC_APB1ENR1_DAC1EN_Msk (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
  8956. #define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
  8957. #define RCC_APB1ENR1_OPAMPEN_Pos (30U)
  8958. #define RCC_APB1ENR1_OPAMPEN_Msk (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
  8959. #define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
  8960. #define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
  8961. #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
  8962. #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
  8963. /******************** Bit definition for RCC_APB1RSTR2 register **************/
  8964. #define RCC_APB1ENR2_LPUART1EN_Pos (0U)
  8965. #define RCC_APB1ENR2_LPUART1EN_Msk (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
  8966. #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
  8967. #define RCC_APB1ENR2_SWPMI1EN_Pos (2U)
  8968. #define RCC_APB1ENR2_SWPMI1EN_Msk (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
  8969. #define RCC_APB1ENR2_SWPMI1EN RCC_APB1ENR2_SWPMI1EN_Msk
  8970. #define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
  8971. #define RCC_APB1ENR2_LPTIM2EN_Msk (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
  8972. #define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
  8973. /******************** Bit definition for RCC_APB2ENR register ***************/
  8974. #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
  8975. #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
  8976. #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
  8977. #define RCC_APB2ENR_FWEN_Pos (7U)
  8978. #define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
  8979. #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
  8980. #define RCC_APB2ENR_TIM1EN_Pos (11U)
  8981. #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
  8982. #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
  8983. #define RCC_APB2ENR_SPI1EN_Pos (12U)
  8984. #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
  8985. #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
  8986. #define RCC_APB2ENR_USART1EN_Pos (14U)
  8987. #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
  8988. #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
  8989. #define RCC_APB2ENR_TIM15EN_Pos (16U)
  8990. #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
  8991. #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
  8992. #define RCC_APB2ENR_TIM16EN_Pos (17U)
  8993. #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
  8994. #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
  8995. #define RCC_APB2ENR_SAI1EN_Pos (21U)
  8996. #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
  8997. #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
  8998. /******************** Bit definition for RCC_AHB1SMENR register ***************/
  8999. #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
  9000. #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
  9001. #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
  9002. #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
  9003. #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
  9004. #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
  9005. #define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
  9006. #define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
  9007. #define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
  9008. #define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
  9009. #define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
  9010. #define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
  9011. #define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
  9012. #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
  9013. #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
  9014. #define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
  9015. #define RCC_AHB1SMENR_TSCSMEN_Msk (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
  9016. #define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
  9017. /******************** Bit definition for RCC_AHB2SMENR register *************/
  9018. #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
  9019. #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
  9020. #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
  9021. #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
  9022. #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
  9023. #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
  9024. #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
  9025. #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
  9026. #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
  9027. #define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
  9028. #define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
  9029. #define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
  9030. #define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
  9031. #define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
  9032. #define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
  9033. #define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
  9034. #define RCC_AHB2SMENR_ADCSMEN_Msk (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
  9035. #define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
  9036. #define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
  9037. #define RCC_AHB2SMENR_RNGSMEN_Msk (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
  9038. #define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
  9039. /******************** Bit definition for RCC_AHB3SMENR register *************/
  9040. #define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
  9041. #define RCC_AHB3SMENR_QSPISMEN_Msk (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
  9042. #define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
  9043. /******************** Bit definition for RCC_APB1SMENR1 register *************/
  9044. #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
  9045. #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
  9046. #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
  9047. #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
  9048. #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
  9049. #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
  9050. #define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
  9051. #define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
  9052. #define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
  9053. #define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
  9054. #define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1U << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
  9055. #define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
  9056. #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
  9057. #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
  9058. #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
  9059. #define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
  9060. #define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
  9061. #define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
  9062. #define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
  9063. #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
  9064. #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
  9065. #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
  9066. #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
  9067. #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
  9068. #define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
  9069. #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
  9070. #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
  9071. #define RCC_APB1SMENR1_CRSSMEN_Pos (24U)
  9072. #define RCC_APB1SMENR1_CRSSMEN_Msk (0x1U << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
  9073. #define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
  9074. #define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
  9075. #define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
  9076. #define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
  9077. #define RCC_APB1SMENR1_USBFSSMEN_Pos (26U)
  9078. #define RCC_APB1SMENR1_USBFSSMEN_Msk (0x1U << RCC_APB1SMENR1_USBFSSMEN_Pos) /*!< 0x04000000 */
  9079. #define RCC_APB1SMENR1_USBFSSMEN RCC_APB1SMENR1_USBFSSMEN_Msk
  9080. #define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
  9081. #define RCC_APB1SMENR1_PWRSMEN_Msk (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
  9082. #define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
  9083. #define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
  9084. #define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
  9085. #define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
  9086. #define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
  9087. #define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
  9088. #define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
  9089. #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
  9090. #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
  9091. #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
  9092. /******************** Bit definition for RCC_APB1SMENR2 register *************/
  9093. #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
  9094. #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
  9095. #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
  9096. #define RCC_APB1SMENR2_SWPMI1SMEN_Pos (2U)
  9097. #define RCC_APB1SMENR2_SWPMI1SMEN_Msk (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
  9098. #define RCC_APB1SMENR2_SWPMI1SMEN RCC_APB1SMENR2_SWPMI1SMEN_Msk
  9099. #define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
  9100. #define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
  9101. #define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
  9102. /******************** Bit definition for RCC_APB2SMENR register *************/
  9103. #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
  9104. #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
  9105. #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
  9106. #define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
  9107. #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
  9108. #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
  9109. #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
  9110. #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
  9111. #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
  9112. #define RCC_APB2SMENR_USART1SMEN_Pos (14U)
  9113. #define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
  9114. #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
  9115. #define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
  9116. #define RCC_APB2SMENR_TIM15SMEN_Msk (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
  9117. #define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
  9118. #define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
  9119. #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
  9120. #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
  9121. #define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
  9122. #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
  9123. #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
  9124. /******************** Bit definition for RCC_CCIPR register ******************/
  9125. #define RCC_CCIPR_USART1SEL_Pos (0U)
  9126. #define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
  9127. #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
  9128. #define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
  9129. #define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
  9130. #define RCC_CCIPR_USART2SEL_Pos (2U)
  9131. #define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
  9132. #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
  9133. #define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
  9134. #define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
  9135. #define RCC_CCIPR_LPUART1SEL_Pos (10U)
  9136. #define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
  9137. #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
  9138. #define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
  9139. #define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
  9140. #define RCC_CCIPR_I2C1SEL_Pos (12U)
  9141. #define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
  9142. #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
  9143. #define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
  9144. #define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
  9145. #define RCC_CCIPR_I2C3SEL_Pos (16U)
  9146. #define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
  9147. #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
  9148. #define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
  9149. #define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
  9150. #define RCC_CCIPR_LPTIM1SEL_Pos (18U)
  9151. #define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
  9152. #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
  9153. #define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
  9154. #define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
  9155. #define RCC_CCIPR_LPTIM2SEL_Pos (20U)
  9156. #define RCC_CCIPR_LPTIM2SEL_Msk (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
  9157. #define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
  9158. #define RCC_CCIPR_LPTIM2SEL_0 (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
  9159. #define RCC_CCIPR_LPTIM2SEL_1 (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
  9160. #define RCC_CCIPR_SAI1SEL_Pos (22U)
  9161. #define RCC_CCIPR_SAI1SEL_Msk (0x3U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00C00000 */
  9162. #define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
  9163. #define RCC_CCIPR_SAI1SEL_0 (0x1U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00400000 */
  9164. #define RCC_CCIPR_SAI1SEL_1 (0x2U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00800000 */
  9165. #define RCC_CCIPR_CLK48SEL_Pos (26U)
  9166. #define RCC_CCIPR_CLK48SEL_Msk (0x3U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
  9167. #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
  9168. #define RCC_CCIPR_CLK48SEL_0 (0x1U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
  9169. #define RCC_CCIPR_CLK48SEL_1 (0x2U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
  9170. #define RCC_CCIPR_ADCSEL_Pos (28U)
  9171. #define RCC_CCIPR_ADCSEL_Msk (0x3U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */
  9172. #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
  9173. #define RCC_CCIPR_ADCSEL_0 (0x1U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */
  9174. #define RCC_CCIPR_ADCSEL_1 (0x2U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */
  9175. #define RCC_CCIPR_SWPMI1SEL_Pos (30U)
  9176. #define RCC_CCIPR_SWPMI1SEL_Msk (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
  9177. #define RCC_CCIPR_SWPMI1SEL RCC_CCIPR_SWPMI1SEL_Msk
  9178. /******************** Bit definition for RCC_BDCR register ******************/
  9179. #define RCC_BDCR_LSEON_Pos (0U)
  9180. #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
  9181. #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
  9182. #define RCC_BDCR_LSERDY_Pos (1U)
  9183. #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
  9184. #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
  9185. #define RCC_BDCR_LSEBYP_Pos (2U)
  9186. #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
  9187. #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
  9188. #define RCC_BDCR_LSEDRV_Pos (3U)
  9189. #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
  9190. #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
  9191. #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
  9192. #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
  9193. #define RCC_BDCR_LSECSSON_Pos (5U)
  9194. #define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
  9195. #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
  9196. #define RCC_BDCR_LSECSSD_Pos (6U)
  9197. #define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
  9198. #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
  9199. #define RCC_BDCR_RTCSEL_Pos (8U)
  9200. #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
  9201. #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
  9202. #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
  9203. #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
  9204. #define RCC_BDCR_RTCEN_Pos (15U)
  9205. #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
  9206. #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
  9207. #define RCC_BDCR_BDRST_Pos (16U)
  9208. #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
  9209. #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
  9210. #define RCC_BDCR_LSCOEN_Pos (24U)
  9211. #define RCC_BDCR_LSCOEN_Msk (0x1U << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
  9212. #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
  9213. #define RCC_BDCR_LSCOSEL_Pos (25U)
  9214. #define RCC_BDCR_LSCOSEL_Msk (0x1U << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
  9215. #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
  9216. /******************** Bit definition for RCC_CSR register *******************/
  9217. #define RCC_CSR_LSION_Pos (0U)
  9218. #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
  9219. #define RCC_CSR_LSION RCC_CSR_LSION_Msk
  9220. #define RCC_CSR_LSIRDY_Pos (1U)
  9221. #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
  9222. #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
  9223. #define RCC_CSR_MSISRANGE_Pos (8U)
  9224. #define RCC_CSR_MSISRANGE_Msk (0xFU << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */
  9225. #define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
  9226. #define RCC_CSR_MSISRANGE_1 (0x4U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */
  9227. #define RCC_CSR_MSISRANGE_2 (0x5U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */
  9228. #define RCC_CSR_MSISRANGE_4 (0x6U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */
  9229. #define RCC_CSR_MSISRANGE_8 (0x7U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */
  9230. #define RCC_CSR_RMVF_Pos (23U)
  9231. #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
  9232. #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
  9233. #define RCC_CSR_FWRSTF_Pos (24U)
  9234. #define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
  9235. #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
  9236. #define RCC_CSR_OBLRSTF_Pos (25U)
  9237. #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
  9238. #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
  9239. #define RCC_CSR_PINRSTF_Pos (26U)
  9240. #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
  9241. #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
  9242. #define RCC_CSR_BORRSTF_Pos (27U)
  9243. #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
  9244. #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
  9245. #define RCC_CSR_SFTRSTF_Pos (28U)
  9246. #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
  9247. #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
  9248. #define RCC_CSR_IWDGRSTF_Pos (29U)
  9249. #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
  9250. #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
  9251. #define RCC_CSR_WWDGRSTF_Pos (30U)
  9252. #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
  9253. #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
  9254. #define RCC_CSR_LPWRRSTF_Pos (31U)
  9255. #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
  9256. #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
  9257. /******************** Bit definition for RCC_CRRCR register *****************/
  9258. #define RCC_CRRCR_HSI48ON_Pos (0U)
  9259. #define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
  9260. #define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
  9261. #define RCC_CRRCR_HSI48RDY_Pos (1U)
  9262. #define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
  9263. #define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
  9264. /*!< HSI48CAL configuration */
  9265. #define RCC_CRRCR_HSI48CAL_Pos (7U)
  9266. #define RCC_CRRCR_HSI48CAL_Msk (0x1FFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */
  9267. #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
  9268. #define RCC_CRRCR_HSI48CAL_0 (0x001U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
  9269. #define RCC_CRRCR_HSI48CAL_1 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
  9270. #define RCC_CRRCR_HSI48CAL_2 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
  9271. #define RCC_CRRCR_HSI48CAL_3 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */
  9272. #define RCC_CRRCR_HSI48CAL_4 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */
  9273. #define RCC_CRRCR_HSI48CAL_5 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */
  9274. #define RCC_CRRCR_HSI48CAL_6 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */
  9275. #define RCC_CRRCR_HSI48CAL_7 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */
  9276. #define RCC_CRRCR_HSI48CAL_8 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */
  9277. /******************************************************************************/
  9278. /* */
  9279. /* RNG */
  9280. /* */
  9281. /******************************************************************************/
  9282. /******************** Bits definition for RNG_CR register *******************/
  9283. #define RNG_CR_RNGEN_Pos (2U)
  9284. #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
  9285. #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
  9286. #define RNG_CR_IE_Pos (3U)
  9287. #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
  9288. #define RNG_CR_IE RNG_CR_IE_Msk
  9289. /******************** Bits definition for RNG_SR register *******************/
  9290. #define RNG_SR_DRDY_Pos (0U)
  9291. #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
  9292. #define RNG_SR_DRDY RNG_SR_DRDY_Msk
  9293. #define RNG_SR_CECS_Pos (1U)
  9294. #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
  9295. #define RNG_SR_CECS RNG_SR_CECS_Msk
  9296. #define RNG_SR_SECS_Pos (2U)
  9297. #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
  9298. #define RNG_SR_SECS RNG_SR_SECS_Msk
  9299. #define RNG_SR_CEIS_Pos (5U)
  9300. #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
  9301. #define RNG_SR_CEIS RNG_SR_CEIS_Msk
  9302. #define RNG_SR_SEIS_Pos (6U)
  9303. #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
  9304. #define RNG_SR_SEIS RNG_SR_SEIS_Msk
  9305. /******************************************************************************/
  9306. /* */
  9307. /* Real-Time Clock (RTC) */
  9308. /* */
  9309. /******************************************************************************/
  9310. /*
  9311. * @brief Specific device feature definitions
  9312. */
  9313. #define RTC_TAMPER2_SUPPORT
  9314. #define RTC_WAKEUP_SUPPORT
  9315. #define RTC_BACKUP_SUPPORT
  9316. /******************** Bits definition for RTC_TR register *******************/
  9317. #define RTC_TR_PM_Pos (22U)
  9318. #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
  9319. #define RTC_TR_PM RTC_TR_PM_Msk
  9320. #define RTC_TR_HT_Pos (20U)
  9321. #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
  9322. #define RTC_TR_HT RTC_TR_HT_Msk
  9323. #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
  9324. #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
  9325. #define RTC_TR_HU_Pos (16U)
  9326. #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
  9327. #define RTC_TR_HU RTC_TR_HU_Msk
  9328. #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
  9329. #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
  9330. #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
  9331. #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
  9332. #define RTC_TR_MNT_Pos (12U)
  9333. #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
  9334. #define RTC_TR_MNT RTC_TR_MNT_Msk
  9335. #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
  9336. #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
  9337. #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
  9338. #define RTC_TR_MNU_Pos (8U)
  9339. #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
  9340. #define RTC_TR_MNU RTC_TR_MNU_Msk
  9341. #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
  9342. #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
  9343. #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
  9344. #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
  9345. #define RTC_TR_ST_Pos (4U)
  9346. #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
  9347. #define RTC_TR_ST RTC_TR_ST_Msk
  9348. #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
  9349. #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
  9350. #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
  9351. #define RTC_TR_SU_Pos (0U)
  9352. #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
  9353. #define RTC_TR_SU RTC_TR_SU_Msk
  9354. #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
  9355. #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
  9356. #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
  9357. #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
  9358. /******************** Bits definition for RTC_DR register *******************/
  9359. #define RTC_DR_YT_Pos (20U)
  9360. #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
  9361. #define RTC_DR_YT RTC_DR_YT_Msk
  9362. #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
  9363. #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
  9364. #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
  9365. #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
  9366. #define RTC_DR_YU_Pos (16U)
  9367. #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
  9368. #define RTC_DR_YU RTC_DR_YU_Msk
  9369. #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
  9370. #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
  9371. #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
  9372. #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
  9373. #define RTC_DR_WDU_Pos (13U)
  9374. #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
  9375. #define RTC_DR_WDU RTC_DR_WDU_Msk
  9376. #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
  9377. #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
  9378. #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
  9379. #define RTC_DR_MT_Pos (12U)
  9380. #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
  9381. #define RTC_DR_MT RTC_DR_MT_Msk
  9382. #define RTC_DR_MU_Pos (8U)
  9383. #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
  9384. #define RTC_DR_MU RTC_DR_MU_Msk
  9385. #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
  9386. #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
  9387. #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
  9388. #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
  9389. #define RTC_DR_DT_Pos (4U)
  9390. #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
  9391. #define RTC_DR_DT RTC_DR_DT_Msk
  9392. #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
  9393. #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
  9394. #define RTC_DR_DU_Pos (0U)
  9395. #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
  9396. #define RTC_DR_DU RTC_DR_DU_Msk
  9397. #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
  9398. #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
  9399. #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
  9400. #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
  9401. /******************** Bits definition for RTC_CR register *******************/
  9402. #define RTC_CR_ITSE_Pos (24U)
  9403. #define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
  9404. #define RTC_CR_ITSE RTC_CR_ITSE_Msk
  9405. #define RTC_CR_COE_Pos (23U)
  9406. #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
  9407. #define RTC_CR_COE RTC_CR_COE_Msk
  9408. #define RTC_CR_OSEL_Pos (21U)
  9409. #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
  9410. #define RTC_CR_OSEL RTC_CR_OSEL_Msk
  9411. #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
  9412. #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
  9413. #define RTC_CR_POL_Pos (20U)
  9414. #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
  9415. #define RTC_CR_POL RTC_CR_POL_Msk
  9416. #define RTC_CR_COSEL_Pos (19U)
  9417. #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
  9418. #define RTC_CR_COSEL RTC_CR_COSEL_Msk
  9419. #define RTC_CR_BKP_Pos (18U)
  9420. #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
  9421. #define RTC_CR_BKP RTC_CR_BKP_Msk
  9422. #define RTC_CR_SUB1H_Pos (17U)
  9423. #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
  9424. #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
  9425. #define RTC_CR_ADD1H_Pos (16U)
  9426. #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
  9427. #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
  9428. #define RTC_CR_TSIE_Pos (15U)
  9429. #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
  9430. #define RTC_CR_TSIE RTC_CR_TSIE_Msk
  9431. #define RTC_CR_WUTIE_Pos (14U)
  9432. #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
  9433. #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
  9434. #define RTC_CR_ALRBIE_Pos (13U)
  9435. #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
  9436. #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
  9437. #define RTC_CR_ALRAIE_Pos (12U)
  9438. #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
  9439. #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
  9440. #define RTC_CR_TSE_Pos (11U)
  9441. #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
  9442. #define RTC_CR_TSE RTC_CR_TSE_Msk
  9443. #define RTC_CR_WUTE_Pos (10U)
  9444. #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
  9445. #define RTC_CR_WUTE RTC_CR_WUTE_Msk
  9446. #define RTC_CR_ALRBE_Pos (9U)
  9447. #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
  9448. #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
  9449. #define RTC_CR_ALRAE_Pos (8U)
  9450. #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
  9451. #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
  9452. #define RTC_CR_FMT_Pos (6U)
  9453. #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
  9454. #define RTC_CR_FMT RTC_CR_FMT_Msk
  9455. #define RTC_CR_BYPSHAD_Pos (5U)
  9456. #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
  9457. #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
  9458. #define RTC_CR_REFCKON_Pos (4U)
  9459. #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
  9460. #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
  9461. #define RTC_CR_TSEDGE_Pos (3U)
  9462. #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
  9463. #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
  9464. #define RTC_CR_WUCKSEL_Pos (0U)
  9465. #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
  9466. #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
  9467. #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
  9468. #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
  9469. #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
  9470. /* Legacy defines */
  9471. #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
  9472. #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
  9473. #define RTC_CR_BCK RTC_CR_BKP
  9474. /******************** Bits definition for RTC_ISR register ******************/
  9475. #define RTC_ISR_ITSF_Pos (17U)
  9476. #define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
  9477. #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
  9478. #define RTC_ISR_RECALPF_Pos (16U)
  9479. #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
  9480. #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
  9481. #define RTC_ISR_TAMP2F_Pos (14U)
  9482. #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
  9483. #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
  9484. #define RTC_ISR_TSOVF_Pos (12U)
  9485. #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
  9486. #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
  9487. #define RTC_ISR_TSF_Pos (11U)
  9488. #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
  9489. #define RTC_ISR_TSF RTC_ISR_TSF_Msk
  9490. #define RTC_ISR_WUTF_Pos (10U)
  9491. #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
  9492. #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
  9493. #define RTC_ISR_ALRBF_Pos (9U)
  9494. #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
  9495. #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
  9496. #define RTC_ISR_ALRAF_Pos (8U)
  9497. #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
  9498. #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
  9499. #define RTC_ISR_INIT_Pos (7U)
  9500. #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
  9501. #define RTC_ISR_INIT RTC_ISR_INIT_Msk
  9502. #define RTC_ISR_INITF_Pos (6U)
  9503. #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
  9504. #define RTC_ISR_INITF RTC_ISR_INITF_Msk
  9505. #define RTC_ISR_RSF_Pos (5U)
  9506. #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
  9507. #define RTC_ISR_RSF RTC_ISR_RSF_Msk
  9508. #define RTC_ISR_INITS_Pos (4U)
  9509. #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
  9510. #define RTC_ISR_INITS RTC_ISR_INITS_Msk
  9511. #define RTC_ISR_SHPF_Pos (3U)
  9512. #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
  9513. #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
  9514. #define RTC_ISR_WUTWF_Pos (2U)
  9515. #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
  9516. #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
  9517. #define RTC_ISR_ALRBWF_Pos (1U)
  9518. #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
  9519. #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
  9520. #define RTC_ISR_ALRAWF_Pos (0U)
  9521. #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
  9522. #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
  9523. /******************** Bits definition for RTC_PRER register *****************/
  9524. #define RTC_PRER_PREDIV_A_Pos (16U)
  9525. #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
  9526. #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
  9527. #define RTC_PRER_PREDIV_S_Pos (0U)
  9528. #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
  9529. #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
  9530. /******************** Bits definition for RTC_WUTR register *****************/
  9531. #define RTC_WUTR_WUT_Pos (0U)
  9532. #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
  9533. #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
  9534. /******************** Bits definition for RTC_ALRMAR register ***************/
  9535. #define RTC_ALRMAR_MSK4_Pos (31U)
  9536. #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
  9537. #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
  9538. #define RTC_ALRMAR_WDSEL_Pos (30U)
  9539. #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
  9540. #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
  9541. #define RTC_ALRMAR_DT_Pos (28U)
  9542. #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
  9543. #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
  9544. #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
  9545. #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
  9546. #define RTC_ALRMAR_DU_Pos (24U)
  9547. #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
  9548. #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
  9549. #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
  9550. #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
  9551. #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
  9552. #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
  9553. #define RTC_ALRMAR_MSK3_Pos (23U)
  9554. #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
  9555. #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
  9556. #define RTC_ALRMAR_PM_Pos (22U)
  9557. #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
  9558. #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
  9559. #define RTC_ALRMAR_HT_Pos (20U)
  9560. #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
  9561. #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
  9562. #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
  9563. #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
  9564. #define RTC_ALRMAR_HU_Pos (16U)
  9565. #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
  9566. #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
  9567. #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
  9568. #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
  9569. #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
  9570. #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
  9571. #define RTC_ALRMAR_MSK2_Pos (15U)
  9572. #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
  9573. #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
  9574. #define RTC_ALRMAR_MNT_Pos (12U)
  9575. #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
  9576. #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
  9577. #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
  9578. #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
  9579. #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
  9580. #define RTC_ALRMAR_MNU_Pos (8U)
  9581. #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
  9582. #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
  9583. #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
  9584. #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
  9585. #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
  9586. #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
  9587. #define RTC_ALRMAR_MSK1_Pos (7U)
  9588. #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
  9589. #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
  9590. #define RTC_ALRMAR_ST_Pos (4U)
  9591. #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
  9592. #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
  9593. #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
  9594. #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
  9595. #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
  9596. #define RTC_ALRMAR_SU_Pos (0U)
  9597. #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
  9598. #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
  9599. #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
  9600. #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
  9601. #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
  9602. #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
  9603. /******************** Bits definition for RTC_ALRMBR register ***************/
  9604. #define RTC_ALRMBR_MSK4_Pos (31U)
  9605. #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
  9606. #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
  9607. #define RTC_ALRMBR_WDSEL_Pos (30U)
  9608. #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
  9609. #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
  9610. #define RTC_ALRMBR_DT_Pos (28U)
  9611. #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
  9612. #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
  9613. #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
  9614. #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
  9615. #define RTC_ALRMBR_DU_Pos (24U)
  9616. #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
  9617. #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
  9618. #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
  9619. #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
  9620. #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
  9621. #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
  9622. #define RTC_ALRMBR_MSK3_Pos (23U)
  9623. #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
  9624. #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
  9625. #define RTC_ALRMBR_PM_Pos (22U)
  9626. #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
  9627. #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
  9628. #define RTC_ALRMBR_HT_Pos (20U)
  9629. #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
  9630. #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
  9631. #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
  9632. #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
  9633. #define RTC_ALRMBR_HU_Pos (16U)
  9634. #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
  9635. #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
  9636. #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
  9637. #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
  9638. #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
  9639. #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
  9640. #define RTC_ALRMBR_MSK2_Pos (15U)
  9641. #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
  9642. #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
  9643. #define RTC_ALRMBR_MNT_Pos (12U)
  9644. #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
  9645. #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
  9646. #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
  9647. #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
  9648. #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
  9649. #define RTC_ALRMBR_MNU_Pos (8U)
  9650. #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
  9651. #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
  9652. #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
  9653. #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
  9654. #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
  9655. #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
  9656. #define RTC_ALRMBR_MSK1_Pos (7U)
  9657. #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
  9658. #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
  9659. #define RTC_ALRMBR_ST_Pos (4U)
  9660. #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
  9661. #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
  9662. #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
  9663. #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
  9664. #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
  9665. #define RTC_ALRMBR_SU_Pos (0U)
  9666. #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
  9667. #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
  9668. #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
  9669. #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
  9670. #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
  9671. #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
  9672. /******************** Bits definition for RTC_WPR register ******************/
  9673. #define RTC_WPR_KEY_Pos (0U)
  9674. #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
  9675. #define RTC_WPR_KEY RTC_WPR_KEY_Msk
  9676. /******************** Bits definition for RTC_SSR register ******************/
  9677. #define RTC_SSR_SS_Pos (0U)
  9678. #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
  9679. #define RTC_SSR_SS RTC_SSR_SS_Msk
  9680. /******************** Bits definition for RTC_SHIFTR register ***************/
  9681. #define RTC_SHIFTR_SUBFS_Pos (0U)
  9682. #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
  9683. #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
  9684. #define RTC_SHIFTR_ADD1S_Pos (31U)
  9685. #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
  9686. #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
  9687. /******************** Bits definition for RTC_TSTR register *****************/
  9688. #define RTC_TSTR_PM_Pos (22U)
  9689. #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
  9690. #define RTC_TSTR_PM RTC_TSTR_PM_Msk
  9691. #define RTC_TSTR_HT_Pos (20U)
  9692. #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
  9693. #define RTC_TSTR_HT RTC_TSTR_HT_Msk
  9694. #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
  9695. #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
  9696. #define RTC_TSTR_HU_Pos (16U)
  9697. #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
  9698. #define RTC_TSTR_HU RTC_TSTR_HU_Msk
  9699. #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
  9700. #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
  9701. #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
  9702. #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
  9703. #define RTC_TSTR_MNT_Pos (12U)
  9704. #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
  9705. #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
  9706. #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
  9707. #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
  9708. #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
  9709. #define RTC_TSTR_MNU_Pos (8U)
  9710. #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
  9711. #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
  9712. #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
  9713. #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
  9714. #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
  9715. #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
  9716. #define RTC_TSTR_ST_Pos (4U)
  9717. #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
  9718. #define RTC_TSTR_ST RTC_TSTR_ST_Msk
  9719. #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
  9720. #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
  9721. #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
  9722. #define RTC_TSTR_SU_Pos (0U)
  9723. #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
  9724. #define RTC_TSTR_SU RTC_TSTR_SU_Msk
  9725. #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
  9726. #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
  9727. #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
  9728. #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
  9729. /******************** Bits definition for RTC_TSDR register *****************/
  9730. #define RTC_TSDR_WDU_Pos (13U)
  9731. #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
  9732. #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
  9733. #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
  9734. #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
  9735. #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
  9736. #define RTC_TSDR_MT_Pos (12U)
  9737. #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
  9738. #define RTC_TSDR_MT RTC_TSDR_MT_Msk
  9739. #define RTC_TSDR_MU_Pos (8U)
  9740. #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
  9741. #define RTC_TSDR_MU RTC_TSDR_MU_Msk
  9742. #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
  9743. #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
  9744. #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
  9745. #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
  9746. #define RTC_TSDR_DT_Pos (4U)
  9747. #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
  9748. #define RTC_TSDR_DT RTC_TSDR_DT_Msk
  9749. #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
  9750. #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
  9751. #define RTC_TSDR_DU_Pos (0U)
  9752. #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
  9753. #define RTC_TSDR_DU RTC_TSDR_DU_Msk
  9754. #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
  9755. #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
  9756. #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
  9757. #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
  9758. /******************** Bits definition for RTC_TSSSR register ****************/
  9759. #define RTC_TSSSR_SS_Pos (0U)
  9760. #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
  9761. #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
  9762. /******************** Bits definition for RTC_CAL register *****************/
  9763. #define RTC_CALR_CALP_Pos (15U)
  9764. #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
  9765. #define RTC_CALR_CALP RTC_CALR_CALP_Msk
  9766. #define RTC_CALR_CALW8_Pos (14U)
  9767. #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
  9768. #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
  9769. #define RTC_CALR_CALW16_Pos (13U)
  9770. #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
  9771. #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
  9772. #define RTC_CALR_CALM_Pos (0U)
  9773. #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
  9774. #define RTC_CALR_CALM RTC_CALR_CALM_Msk
  9775. #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
  9776. #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
  9777. #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
  9778. #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
  9779. #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
  9780. #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
  9781. #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
  9782. #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
  9783. #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
  9784. /******************** Bits definition for RTC_TAMPCR register ***************/
  9785. #define RTC_TAMPCR_TAMP2MF_Pos (21U)
  9786. #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
  9787. #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
  9788. #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
  9789. #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
  9790. #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
  9791. #define RTC_TAMPCR_TAMP2IE_Pos (19U)
  9792. #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
  9793. #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
  9794. #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
  9795. #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
  9796. #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
  9797. #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
  9798. #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
  9799. #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
  9800. #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
  9801. #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
  9802. #define RTC_TAMPCR_TAMPFLT_Pos (11U)
  9803. #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
  9804. #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
  9805. #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
  9806. #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
  9807. #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
  9808. #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
  9809. #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
  9810. #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
  9811. #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
  9812. #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
  9813. #define RTC_TAMPCR_TAMPTS_Pos (7U)
  9814. #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
  9815. #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
  9816. #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
  9817. #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
  9818. #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
  9819. #define RTC_TAMPCR_TAMP2E_Pos (3U)
  9820. #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
  9821. #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
  9822. #define RTC_TAMPCR_TAMPIE_Pos (2U)
  9823. #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
  9824. #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
  9825. /******************** Bits definition for RTC_ALRMASSR register *************/
  9826. #define RTC_ALRMASSR_MASKSS_Pos (24U)
  9827. #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
  9828. #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
  9829. #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
  9830. #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
  9831. #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
  9832. #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
  9833. #define RTC_ALRMASSR_SS_Pos (0U)
  9834. #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
  9835. #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
  9836. /******************** Bits definition for RTC_ALRMBSSR register *************/
  9837. #define RTC_ALRMBSSR_MASKSS_Pos (24U)
  9838. #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
  9839. #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
  9840. #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
  9841. #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
  9842. #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
  9843. #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
  9844. #define RTC_ALRMBSSR_SS_Pos (0U)
  9845. #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
  9846. #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
  9847. /******************** Bits definition for RTC_0R register *******************/
  9848. #define RTC_OR_OUT_RMP_Pos (1U)
  9849. #define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
  9850. #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
  9851. #define RTC_OR_ALARMOUTTYPE_Pos (0U)
  9852. #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
  9853. #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
  9854. /******************** Bits definition for RTC_BKP0R register ****************/
  9855. #define RTC_BKP0R_Pos (0U)
  9856. #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
  9857. #define RTC_BKP0R RTC_BKP0R_Msk
  9858. /******************** Bits definition for RTC_BKP1R register ****************/
  9859. #define RTC_BKP1R_Pos (0U)
  9860. #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
  9861. #define RTC_BKP1R RTC_BKP1R_Msk
  9862. /******************** Bits definition for RTC_BKP2R register ****************/
  9863. #define RTC_BKP2R_Pos (0U)
  9864. #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
  9865. #define RTC_BKP2R RTC_BKP2R_Msk
  9866. /******************** Bits definition for RTC_BKP3R register ****************/
  9867. #define RTC_BKP3R_Pos (0U)
  9868. #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
  9869. #define RTC_BKP3R RTC_BKP3R_Msk
  9870. /******************** Bits definition for RTC_BKP4R register ****************/
  9871. #define RTC_BKP4R_Pos (0U)
  9872. #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
  9873. #define RTC_BKP4R RTC_BKP4R_Msk
  9874. /******************** Bits definition for RTC_BKP5R register ****************/
  9875. #define RTC_BKP5R_Pos (0U)
  9876. #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
  9877. #define RTC_BKP5R RTC_BKP5R_Msk
  9878. /******************** Bits definition for RTC_BKP6R register ****************/
  9879. #define RTC_BKP6R_Pos (0U)
  9880. #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
  9881. #define RTC_BKP6R RTC_BKP6R_Msk
  9882. /******************** Bits definition for RTC_BKP7R register ****************/
  9883. #define RTC_BKP7R_Pos (0U)
  9884. #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
  9885. #define RTC_BKP7R RTC_BKP7R_Msk
  9886. /******************** Bits definition for RTC_BKP8R register ****************/
  9887. #define RTC_BKP8R_Pos (0U)
  9888. #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
  9889. #define RTC_BKP8R RTC_BKP8R_Msk
  9890. /******************** Bits definition for RTC_BKP9R register ****************/
  9891. #define RTC_BKP9R_Pos (0U)
  9892. #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
  9893. #define RTC_BKP9R RTC_BKP9R_Msk
  9894. /******************** Bits definition for RTC_BKP10R register ***************/
  9895. #define RTC_BKP10R_Pos (0U)
  9896. #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
  9897. #define RTC_BKP10R RTC_BKP10R_Msk
  9898. /******************** Bits definition for RTC_BKP11R register ***************/
  9899. #define RTC_BKP11R_Pos (0U)
  9900. #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
  9901. #define RTC_BKP11R RTC_BKP11R_Msk
  9902. /******************** Bits definition for RTC_BKP12R register ***************/
  9903. #define RTC_BKP12R_Pos (0U)
  9904. #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
  9905. #define RTC_BKP12R RTC_BKP12R_Msk
  9906. /******************** Bits definition for RTC_BKP13R register ***************/
  9907. #define RTC_BKP13R_Pos (0U)
  9908. #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
  9909. #define RTC_BKP13R RTC_BKP13R_Msk
  9910. /******************** Bits definition for RTC_BKP14R register ***************/
  9911. #define RTC_BKP14R_Pos (0U)
  9912. #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
  9913. #define RTC_BKP14R RTC_BKP14R_Msk
  9914. /******************** Bits definition for RTC_BKP15R register ***************/
  9915. #define RTC_BKP15R_Pos (0U)
  9916. #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
  9917. #define RTC_BKP15R RTC_BKP15R_Msk
  9918. /******************** Bits definition for RTC_BKP16R register ***************/
  9919. #define RTC_BKP16R_Pos (0U)
  9920. #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
  9921. #define RTC_BKP16R RTC_BKP16R_Msk
  9922. /******************** Bits definition for RTC_BKP17R register ***************/
  9923. #define RTC_BKP17R_Pos (0U)
  9924. #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
  9925. #define RTC_BKP17R RTC_BKP17R_Msk
  9926. /******************** Bits definition for RTC_BKP18R register ***************/
  9927. #define RTC_BKP18R_Pos (0U)
  9928. #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
  9929. #define RTC_BKP18R RTC_BKP18R_Msk
  9930. /******************** Bits definition for RTC_BKP19R register ***************/
  9931. #define RTC_BKP19R_Pos (0U)
  9932. #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
  9933. #define RTC_BKP19R RTC_BKP19R_Msk
  9934. /******************** Bits definition for RTC_BKP20R register ***************/
  9935. #define RTC_BKP20R_Pos (0U)
  9936. #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
  9937. #define RTC_BKP20R RTC_BKP20R_Msk
  9938. /******************** Bits definition for RTC_BKP21R register ***************/
  9939. #define RTC_BKP21R_Pos (0U)
  9940. #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
  9941. #define RTC_BKP21R RTC_BKP21R_Msk
  9942. /******************** Bits definition for RTC_BKP22R register ***************/
  9943. #define RTC_BKP22R_Pos (0U)
  9944. #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
  9945. #define RTC_BKP22R RTC_BKP22R_Msk
  9946. /******************** Bits definition for RTC_BKP23R register ***************/
  9947. #define RTC_BKP23R_Pos (0U)
  9948. #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
  9949. #define RTC_BKP23R RTC_BKP23R_Msk
  9950. /******************** Bits definition for RTC_BKP24R register ***************/
  9951. #define RTC_BKP24R_Pos (0U)
  9952. #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
  9953. #define RTC_BKP24R RTC_BKP24R_Msk
  9954. /******************** Bits definition for RTC_BKP25R register ***************/
  9955. #define RTC_BKP25R_Pos (0U)
  9956. #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
  9957. #define RTC_BKP25R RTC_BKP25R_Msk
  9958. /******************** Bits definition for RTC_BKP26R register ***************/
  9959. #define RTC_BKP26R_Pos (0U)
  9960. #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
  9961. #define RTC_BKP26R RTC_BKP26R_Msk
  9962. /******************** Bits definition for RTC_BKP27R register ***************/
  9963. #define RTC_BKP27R_Pos (0U)
  9964. #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
  9965. #define RTC_BKP27R RTC_BKP27R_Msk
  9966. /******************** Bits definition for RTC_BKP28R register ***************/
  9967. #define RTC_BKP28R_Pos (0U)
  9968. #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
  9969. #define RTC_BKP28R RTC_BKP28R_Msk
  9970. /******************** Bits definition for RTC_BKP29R register ***************/
  9971. #define RTC_BKP29R_Pos (0U)
  9972. #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
  9973. #define RTC_BKP29R RTC_BKP29R_Msk
  9974. /******************** Bits definition for RTC_BKP30R register ***************/
  9975. #define RTC_BKP30R_Pos (0U)
  9976. #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
  9977. #define RTC_BKP30R RTC_BKP30R_Msk
  9978. /******************** Bits definition for RTC_BKP31R register ***************/
  9979. #define RTC_BKP31R_Pos (0U)
  9980. #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
  9981. #define RTC_BKP31R RTC_BKP31R_Msk
  9982. /******************** Number of backup registers ******************************/
  9983. #define RTC_BKP_NUMBER 32U
  9984. /******************************************************************************/
  9985. /* */
  9986. /* Serial Audio Interface */
  9987. /* */
  9988. /******************************************************************************/
  9989. /******************** Bit definition for SAI_GCR register *******************/
  9990. #define SAI_GCR_SYNCIN_Pos (0U)
  9991. #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
  9992. #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
  9993. #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
  9994. #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
  9995. #define SAI_GCR_SYNCOUT_Pos (4U)
  9996. #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
  9997. #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
  9998. #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
  9999. #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
  10000. /******************* Bit definition for SAI_xCR1 register *******************/
  10001. #define SAI_xCR1_MODE_Pos (0U)
  10002. #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
  10003. #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
  10004. #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
  10005. #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
  10006. #define SAI_xCR1_PRTCFG_Pos (2U)
  10007. #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
  10008. #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
  10009. #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
  10010. #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
  10011. #define SAI_xCR1_DS_Pos (5U)
  10012. #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
  10013. #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
  10014. #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
  10015. #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
  10016. #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
  10017. #define SAI_xCR1_LSBFIRST_Pos (8U)
  10018. #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
  10019. #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
  10020. #define SAI_xCR1_CKSTR_Pos (9U)
  10021. #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
  10022. #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
  10023. #define SAI_xCR1_SYNCEN_Pos (10U)
  10024. #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
  10025. #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
  10026. #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
  10027. #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
  10028. #define SAI_xCR1_MONO_Pos (12U)
  10029. #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
  10030. #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
  10031. #define SAI_xCR1_OUTDRIV_Pos (13U)
  10032. #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
  10033. #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
  10034. #define SAI_xCR1_SAIEN_Pos (16U)
  10035. #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
  10036. #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
  10037. #define SAI_xCR1_DMAEN_Pos (17U)
  10038. #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
  10039. #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
  10040. #define SAI_xCR1_NODIV_Pos (19U)
  10041. #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
  10042. #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
  10043. #define SAI_xCR1_MCKDIV_Pos (20U)
  10044. #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
  10045. #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
  10046. #define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
  10047. #define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
  10048. #define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
  10049. #define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
  10050. /******************* Bit definition for SAI_xCR2 register *******************/
  10051. #define SAI_xCR2_FTH_Pos (0U)
  10052. #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
  10053. #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
  10054. #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
  10055. #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
  10056. #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
  10057. #define SAI_xCR2_FFLUSH_Pos (3U)
  10058. #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
  10059. #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
  10060. #define SAI_xCR2_TRIS_Pos (4U)
  10061. #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
  10062. #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
  10063. #define SAI_xCR2_MUTE_Pos (5U)
  10064. #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
  10065. #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
  10066. #define SAI_xCR2_MUTEVAL_Pos (6U)
  10067. #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
  10068. #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
  10069. #define SAI_xCR2_MUTECNT_Pos (7U)
  10070. #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
  10071. #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
  10072. #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
  10073. #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
  10074. #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
  10075. #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
  10076. #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
  10077. #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
  10078. #define SAI_xCR2_CPL_Pos (13U)
  10079. #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
  10080. #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
  10081. #define SAI_xCR2_COMP_Pos (14U)
  10082. #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
  10083. #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
  10084. #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
  10085. #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
  10086. /****************** Bit definition for SAI_xFRCR register *******************/
  10087. #define SAI_xFRCR_FRL_Pos (0U)
  10088. #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
  10089. #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
  10090. #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
  10091. #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
  10092. #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
  10093. #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
  10094. #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
  10095. #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
  10096. #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
  10097. #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
  10098. #define SAI_xFRCR_FSALL_Pos (8U)
  10099. #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
  10100. #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
  10101. #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
  10102. #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
  10103. #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
  10104. #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
  10105. #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
  10106. #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
  10107. #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
  10108. #define SAI_xFRCR_FSDEF_Pos (16U)
  10109. #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
  10110. #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
  10111. #define SAI_xFRCR_FSPOL_Pos (17U)
  10112. #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
  10113. #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
  10114. #define SAI_xFRCR_FSOFF_Pos (18U)
  10115. #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
  10116. #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
  10117. /****************** Bit definition for SAI_xSLOTR register *******************/
  10118. #define SAI_xSLOTR_FBOFF_Pos (0U)
  10119. #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
  10120. #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
  10121. #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
  10122. #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
  10123. #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
  10124. #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
  10125. #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
  10126. #define SAI_xSLOTR_SLOTSZ_Pos (6U)
  10127. #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
  10128. #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
  10129. #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
  10130. #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
  10131. #define SAI_xSLOTR_NBSLOT_Pos (8U)
  10132. #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
  10133. #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
  10134. #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
  10135. #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
  10136. #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
  10137. #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
  10138. #define SAI_xSLOTR_SLOTEN_Pos (16U)
  10139. #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
  10140. #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
  10141. /******************* Bit definition for SAI_xIMR register *******************/
  10142. #define SAI_xIMR_OVRUDRIE_Pos (0U)
  10143. #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
  10144. #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
  10145. #define SAI_xIMR_MUTEDETIE_Pos (1U)
  10146. #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
  10147. #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
  10148. #define SAI_xIMR_WCKCFGIE_Pos (2U)
  10149. #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
  10150. #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
  10151. #define SAI_xIMR_FREQIE_Pos (3U)
  10152. #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
  10153. #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
  10154. #define SAI_xIMR_CNRDYIE_Pos (4U)
  10155. #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
  10156. #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
  10157. #define SAI_xIMR_AFSDETIE_Pos (5U)
  10158. #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
  10159. #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
  10160. #define SAI_xIMR_LFSDETIE_Pos (6U)
  10161. #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
  10162. #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
  10163. /******************** Bit definition for SAI_xSR register *******************/
  10164. #define SAI_xSR_OVRUDR_Pos (0U)
  10165. #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
  10166. #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
  10167. #define SAI_xSR_MUTEDET_Pos (1U)
  10168. #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
  10169. #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
  10170. #define SAI_xSR_WCKCFG_Pos (2U)
  10171. #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
  10172. #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
  10173. #define SAI_xSR_FREQ_Pos (3U)
  10174. #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
  10175. #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
  10176. #define SAI_xSR_CNRDY_Pos (4U)
  10177. #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
  10178. #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
  10179. #define SAI_xSR_AFSDET_Pos (5U)
  10180. #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
  10181. #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
  10182. #define SAI_xSR_LFSDET_Pos (6U)
  10183. #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
  10184. #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
  10185. #define SAI_xSR_FLVL_Pos (16U)
  10186. #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
  10187. #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
  10188. #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
  10189. #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
  10190. #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
  10191. /****************** Bit definition for SAI_xCLRFR register ******************/
  10192. #define SAI_xCLRFR_COVRUDR_Pos (0U)
  10193. #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
  10194. #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
  10195. #define SAI_xCLRFR_CMUTEDET_Pos (1U)
  10196. #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
  10197. #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
  10198. #define SAI_xCLRFR_CWCKCFG_Pos (2U)
  10199. #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
  10200. #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
  10201. #define SAI_xCLRFR_CFREQ_Pos (3U)
  10202. #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
  10203. #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
  10204. #define SAI_xCLRFR_CCNRDY_Pos (4U)
  10205. #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
  10206. #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
  10207. #define SAI_xCLRFR_CAFSDET_Pos (5U)
  10208. #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
  10209. #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
  10210. #define SAI_xCLRFR_CLFSDET_Pos (6U)
  10211. #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
  10212. #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
  10213. /****************** Bit definition for SAI_xDR register ******************/
  10214. #define SAI_xDR_DATA_Pos (0U)
  10215. #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
  10216. #define SAI_xDR_DATA SAI_xDR_DATA_Msk
  10217. /******************************************************************************/
  10218. /* */
  10219. /* Serial Peripheral Interface (SPI) */
  10220. /* */
  10221. /******************************************************************************/
  10222. /******************* Bit definition for SPI_CR1 register ********************/
  10223. #define SPI_CR1_CPHA_Pos (0U)
  10224. #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
  10225. #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
  10226. #define SPI_CR1_CPOL_Pos (1U)
  10227. #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
  10228. #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
  10229. #define SPI_CR1_MSTR_Pos (2U)
  10230. #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
  10231. #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
  10232. #define SPI_CR1_BR_Pos (3U)
  10233. #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
  10234. #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
  10235. #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
  10236. #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
  10237. #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
  10238. #define SPI_CR1_SPE_Pos (6U)
  10239. #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
  10240. #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
  10241. #define SPI_CR1_LSBFIRST_Pos (7U)
  10242. #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
  10243. #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
  10244. #define SPI_CR1_SSI_Pos (8U)
  10245. #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
  10246. #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
  10247. #define SPI_CR1_SSM_Pos (9U)
  10248. #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
  10249. #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
  10250. #define SPI_CR1_RXONLY_Pos (10U)
  10251. #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
  10252. #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
  10253. #define SPI_CR1_CRCL_Pos (11U)
  10254. #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
  10255. #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
  10256. #define SPI_CR1_CRCNEXT_Pos (12U)
  10257. #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
  10258. #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
  10259. #define SPI_CR1_CRCEN_Pos (13U)
  10260. #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
  10261. #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
  10262. #define SPI_CR1_BIDIOE_Pos (14U)
  10263. #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
  10264. #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
  10265. #define SPI_CR1_BIDIMODE_Pos (15U)
  10266. #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
  10267. #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
  10268. /******************* Bit definition for SPI_CR2 register ********************/
  10269. #define SPI_CR2_RXDMAEN_Pos (0U)
  10270. #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
  10271. #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
  10272. #define SPI_CR2_TXDMAEN_Pos (1U)
  10273. #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
  10274. #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
  10275. #define SPI_CR2_SSOE_Pos (2U)
  10276. #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
  10277. #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
  10278. #define SPI_CR2_NSSP_Pos (3U)
  10279. #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
  10280. #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
  10281. #define SPI_CR2_FRF_Pos (4U)
  10282. #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
  10283. #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
  10284. #define SPI_CR2_ERRIE_Pos (5U)
  10285. #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
  10286. #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
  10287. #define SPI_CR2_RXNEIE_Pos (6U)
  10288. #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
  10289. #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
  10290. #define SPI_CR2_TXEIE_Pos (7U)
  10291. #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
  10292. #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
  10293. #define SPI_CR2_DS_Pos (8U)
  10294. #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
  10295. #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
  10296. #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
  10297. #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
  10298. #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
  10299. #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
  10300. #define SPI_CR2_FRXTH_Pos (12U)
  10301. #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
  10302. #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
  10303. #define SPI_CR2_LDMARX_Pos (13U)
  10304. #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
  10305. #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
  10306. #define SPI_CR2_LDMATX_Pos (14U)
  10307. #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
  10308. #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
  10309. /******************** Bit definition for SPI_SR register ********************/
  10310. #define SPI_SR_RXNE_Pos (0U)
  10311. #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
  10312. #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
  10313. #define SPI_SR_TXE_Pos (1U)
  10314. #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
  10315. #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
  10316. #define SPI_SR_CHSIDE_Pos (2U)
  10317. #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
  10318. #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
  10319. #define SPI_SR_UDR_Pos (3U)
  10320. #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
  10321. #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
  10322. #define SPI_SR_CRCERR_Pos (4U)
  10323. #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
  10324. #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
  10325. #define SPI_SR_MODF_Pos (5U)
  10326. #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
  10327. #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
  10328. #define SPI_SR_OVR_Pos (6U)
  10329. #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
  10330. #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
  10331. #define SPI_SR_BSY_Pos (7U)
  10332. #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
  10333. #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
  10334. #define SPI_SR_FRE_Pos (8U)
  10335. #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
  10336. #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
  10337. #define SPI_SR_FRLVL_Pos (9U)
  10338. #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
  10339. #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
  10340. #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
  10341. #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
  10342. #define SPI_SR_FTLVL_Pos (11U)
  10343. #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
  10344. #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
  10345. #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
  10346. #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
  10347. /******************** Bit definition for SPI_DR register ********************/
  10348. #define SPI_DR_DR_Pos (0U)
  10349. #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
  10350. #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
  10351. /******************* Bit definition for SPI_CRCPR register ******************/
  10352. #define SPI_CRCPR_CRCPOLY_Pos (0U)
  10353. #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
  10354. #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
  10355. /****************** Bit definition for SPI_RXCRCR register ******************/
  10356. #define SPI_RXCRCR_RXCRC_Pos (0U)
  10357. #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
  10358. #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
  10359. /****************** Bit definition for SPI_TXCRCR register ******************/
  10360. #define SPI_TXCRCR_TXCRC_Pos (0U)
  10361. #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
  10362. #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
  10363. /******************************************************************************/
  10364. /* */
  10365. /* QUADSPI */
  10366. /* */
  10367. /******************************************************************************/
  10368. /***************** Bit definition for QUADSPI_CR register *******************/
  10369. #define QUADSPI_CR_EN_Pos (0U)
  10370. #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
  10371. #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
  10372. #define QUADSPI_CR_ABORT_Pos (1U)
  10373. #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
  10374. #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
  10375. #define QUADSPI_CR_DMAEN_Pos (2U)
  10376. #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
  10377. #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
  10378. #define QUADSPI_CR_TCEN_Pos (3U)
  10379. #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
  10380. #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
  10381. #define QUADSPI_CR_SSHIFT_Pos (4U)
  10382. #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
  10383. #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
  10384. #define QUADSPI_CR_DFM_Pos (6U)
  10385. #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
  10386. #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */
  10387. #define QUADSPI_CR_FSEL_Pos (7U)
  10388. #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
  10389. #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */
  10390. #define QUADSPI_CR_FTHRES_Pos (8U)
  10391. #define QUADSPI_CR_FTHRES_Msk (0xFU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
  10392. #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
  10393. #define QUADSPI_CR_TEIE_Pos (16U)
  10394. #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
  10395. #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
  10396. #define QUADSPI_CR_TCIE_Pos (17U)
  10397. #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
  10398. #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
  10399. #define QUADSPI_CR_FTIE_Pos (18U)
  10400. #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
  10401. #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
  10402. #define QUADSPI_CR_SMIE_Pos (19U)
  10403. #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
  10404. #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
  10405. #define QUADSPI_CR_TOIE_Pos (20U)
  10406. #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
  10407. #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
  10408. #define QUADSPI_CR_APMS_Pos (22U)
  10409. #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
  10410. #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
  10411. #define QUADSPI_CR_PMM_Pos (23U)
  10412. #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
  10413. #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
  10414. #define QUADSPI_CR_PRESCALER_Pos (24U)
  10415. #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
  10416. #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
  10417. /***************** Bit definition for QUADSPI_DCR register ******************/
  10418. #define QUADSPI_DCR_CKMODE_Pos (0U)
  10419. #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
  10420. #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
  10421. #define QUADSPI_DCR_CSHT_Pos (8U)
  10422. #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
  10423. #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
  10424. #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
  10425. #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
  10426. #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
  10427. #define QUADSPI_DCR_FSIZE_Pos (16U)
  10428. #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
  10429. #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
  10430. /****************** Bit definition for QUADSPI_SR register *******************/
  10431. #define QUADSPI_SR_TEF_Pos (0U)
  10432. #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
  10433. #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
  10434. #define QUADSPI_SR_TCF_Pos (1U)
  10435. #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
  10436. #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
  10437. #define QUADSPI_SR_FTF_Pos (2U)
  10438. #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
  10439. #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
  10440. #define QUADSPI_SR_SMF_Pos (3U)
  10441. #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
  10442. #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
  10443. #define QUADSPI_SR_TOF_Pos (4U)
  10444. #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
  10445. #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
  10446. #define QUADSPI_SR_BUSY_Pos (5U)
  10447. #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
  10448. #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
  10449. #define QUADSPI_SR_FLEVEL_Pos (8U)
  10450. #define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
  10451. #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
  10452. /****************** Bit definition for QUADSPI_FCR register ******************/
  10453. #define QUADSPI_FCR_CTEF_Pos (0U)
  10454. #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
  10455. #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
  10456. #define QUADSPI_FCR_CTCF_Pos (1U)
  10457. #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
  10458. #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
  10459. #define QUADSPI_FCR_CSMF_Pos (3U)
  10460. #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
  10461. #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
  10462. #define QUADSPI_FCR_CTOF_Pos (4U)
  10463. #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
  10464. #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
  10465. /****************** Bit definition for QUADSPI_DLR register ******************/
  10466. #define QUADSPI_DLR_DL_Pos (0U)
  10467. #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
  10468. #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
  10469. /****************** Bit definition for QUADSPI_CCR register ******************/
  10470. #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
  10471. #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
  10472. #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
  10473. #define QUADSPI_CCR_IMODE_Pos (8U)
  10474. #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
  10475. #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
  10476. #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
  10477. #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
  10478. #define QUADSPI_CCR_ADMODE_Pos (10U)
  10479. #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
  10480. #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
  10481. #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
  10482. #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
  10483. #define QUADSPI_CCR_ADSIZE_Pos (12U)
  10484. #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
  10485. #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
  10486. #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
  10487. #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
  10488. #define QUADSPI_CCR_ABMODE_Pos (14U)
  10489. #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
  10490. #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
  10491. #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
  10492. #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
  10493. #define QUADSPI_CCR_ABSIZE_Pos (16U)
  10494. #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
  10495. #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
  10496. #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
  10497. #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
  10498. #define QUADSPI_CCR_DCYC_Pos (18U)
  10499. #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
  10500. #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
  10501. #define QUADSPI_CCR_DMODE_Pos (24U)
  10502. #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
  10503. #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
  10504. #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
  10505. #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
  10506. #define QUADSPI_CCR_FMODE_Pos (26U)
  10507. #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
  10508. #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
  10509. #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
  10510. #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
  10511. #define QUADSPI_CCR_SIOO_Pos (28U)
  10512. #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
  10513. #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
  10514. #define QUADSPI_CCR_DHHC_Pos (30U)
  10515. #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
  10516. #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */
  10517. #define QUADSPI_CCR_DDRM_Pos (31U)
  10518. #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
  10519. #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
  10520. /****************** Bit definition for QUADSPI_AR register *******************/
  10521. #define QUADSPI_AR_ADDRESS_Pos (0U)
  10522. #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
  10523. #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
  10524. /****************** Bit definition for QUADSPI_ABR register ******************/
  10525. #define QUADSPI_ABR_ALTERNATE_Pos (0U)
  10526. #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
  10527. #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
  10528. /****************** Bit definition for QUADSPI_DR register *******************/
  10529. #define QUADSPI_DR_DATA_Pos (0U)
  10530. #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
  10531. #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
  10532. /****************** Bit definition for QUADSPI_PSMKR register ****************/
  10533. #define QUADSPI_PSMKR_MASK_Pos (0U)
  10534. #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
  10535. #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
  10536. /****************** Bit definition for QUADSPI_PSMAR register ****************/
  10537. #define QUADSPI_PSMAR_MATCH_Pos (0U)
  10538. #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
  10539. #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
  10540. /****************** Bit definition for QUADSPI_PIR register *****************/
  10541. #define QUADSPI_PIR_INTERVAL_Pos (0U)
  10542. #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
  10543. #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
  10544. /****************** Bit definition for QUADSPI_LPTR register *****************/
  10545. #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
  10546. #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
  10547. #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
  10548. /******************************************************************************/
  10549. /* */
  10550. /* SYSCFG */
  10551. /* */
  10552. /******************************************************************************/
  10553. /****************** Bit definition for SYSCFG_MEMRMP register ***************/
  10554. #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
  10555. #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
  10556. #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
  10557. #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
  10558. #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
  10559. #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
  10560. /****************** Bit definition for SYSCFG_CFGR1 register ******************/
  10561. #define SYSCFG_CFGR1_FWDIS_Pos (0U)
  10562. #define SYSCFG_CFGR1_FWDIS_Msk (0x1U << SYSCFG_CFGR1_FWDIS_Pos) /*!< 0x00000001 */
  10563. #define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk /*!< FIREWALL access enable*/
  10564. #define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
  10565. #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
  10566. #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
  10567. #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
  10568. #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
  10569. #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
  10570. #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
  10571. #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
  10572. #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
  10573. #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
  10574. #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
  10575. #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
  10576. #define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
  10577. #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
  10578. #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
  10579. #define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
  10580. #define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
  10581. #define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
  10582. #define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
  10583. #define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
  10584. #define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
  10585. /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
  10586. #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
  10587. #define SYSCFG_EXTICR1_EXTI0_Msk (0x7U << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
  10588. #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
  10589. #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
  10590. #define SYSCFG_EXTICR1_EXTI1_Msk (0x7U << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x00000070 */
  10591. #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
  10592. #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
  10593. #define SYSCFG_EXTICR1_EXTI2_Msk (0x7U << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000700 */
  10594. #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
  10595. #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
  10596. #define SYSCFG_EXTICR1_EXTI3_Msk (0x7U << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x00007000 */
  10597. #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
  10598. /**
  10599. * @brief EXTI0 configuration
  10600. */
  10601. #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
  10602. #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
  10603. #define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
  10604. /**
  10605. * @brief EXTI1 configuration
  10606. */
  10607. #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
  10608. #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
  10609. #define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
  10610. /**
  10611. * @brief EXTI2 configuration
  10612. */
  10613. #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
  10614. /**
  10615. * @brief EXTI3 configuration
  10616. */
  10617. #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
  10618. #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
  10619. #define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
  10620. /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
  10621. #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
  10622. #define SYSCFG_EXTICR2_EXTI4_Msk (0x7U << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
  10623. #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
  10624. #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
  10625. #define SYSCFG_EXTICR2_EXTI5_Msk (0x7U << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x00000070 */
  10626. #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
  10627. #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
  10628. #define SYSCFG_EXTICR2_EXTI6_Msk (0x7U << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000700 */
  10629. #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
  10630. #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
  10631. #define SYSCFG_EXTICR2_EXTI7_Msk (0x7U << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x00007000 */
  10632. #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
  10633. /**
  10634. * @brief EXTI4 configuration
  10635. */
  10636. #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
  10637. #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
  10638. /**
  10639. * @brief EXTI5 configuration
  10640. */
  10641. #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
  10642. #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
  10643. /**
  10644. * @brief EXTI6 configuration
  10645. */
  10646. #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
  10647. #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
  10648. /**
  10649. * @brief EXTI7 configuration
  10650. */
  10651. #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
  10652. #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
  10653. /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
  10654. #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
  10655. #define SYSCFG_EXTICR3_EXTI8_Msk (0x7U << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
  10656. #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
  10657. #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
  10658. #define SYSCFG_EXTICR3_EXTI9_Msk (0x7U << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x00000070 */
  10659. #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
  10660. #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
  10661. #define SYSCFG_EXTICR3_EXTI10_Msk (0x7U << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000700 */
  10662. #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
  10663. #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
  10664. #define SYSCFG_EXTICR3_EXTI11_Msk (0x7U << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x00007000 */
  10665. #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
  10666. /**
  10667. * @brief EXTI8 configuration
  10668. */
  10669. #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
  10670. /**
  10671. * @brief EXTI9 configuration
  10672. */
  10673. #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
  10674. /**
  10675. * @brief EXTI10 configuration
  10676. */
  10677. #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
  10678. /**
  10679. * @brief EXTI11 configuration
  10680. */
  10681. #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
  10682. /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
  10683. #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
  10684. #define SYSCFG_EXTICR4_EXTI12_Msk (0x7U << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
  10685. #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
  10686. #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
  10687. #define SYSCFG_EXTICR4_EXTI13_Msk (0x7U << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
  10688. #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
  10689. #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
  10690. #define SYSCFG_EXTICR4_EXTI14_Msk (0x7U << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
  10691. #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
  10692. #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
  10693. #define SYSCFG_EXTICR4_EXTI15_Msk (0x7U << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
  10694. #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
  10695. /**
  10696. * @brief EXTI12 configuration
  10697. */
  10698. #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
  10699. /**
  10700. * @brief EXTI13 configuration
  10701. */
  10702. #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
  10703. /**
  10704. * @brief EXTI14 configuration
  10705. */
  10706. #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
  10707. #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
  10708. /**
  10709. * @brief EXTI15 configuration
  10710. */
  10711. #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
  10712. #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
  10713. /****************** Bit definition for SYSCFG_SCSR register ****************/
  10714. #define SYSCFG_SCSR_SRAM2ER_Pos (0U)
  10715. #define SYSCFG_SCSR_SRAM2ER_Msk (0x1U << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */
  10716. #define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */
  10717. #define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
  10718. #define SYSCFG_SCSR_SRAM2BSY_Msk (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */
  10719. #define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */
  10720. /****************** Bit definition for SYSCFG_CFGR2 register ****************/
  10721. #define SYSCFG_CFGR2_CLL_Pos (0U)
  10722. #define SYSCFG_CFGR2_CLL_Msk (0x1U << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
  10723. #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
  10724. #define SYSCFG_CFGR2_SPL_Pos (1U)
  10725. #define SYSCFG_CFGR2_SPL_Msk (0x1U << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
  10726. #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
  10727. #define SYSCFG_CFGR2_PVDL_Pos (2U)
  10728. #define SYSCFG_CFGR2_PVDL_Msk (0x1U << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
  10729. #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
  10730. #define SYSCFG_CFGR2_ECCL_Pos (3U)
  10731. #define SYSCFG_CFGR2_ECCL_Msk (0x1U << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
  10732. #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
  10733. #define SYSCFG_CFGR2_SPF_Pos (8U)
  10734. #define SYSCFG_CFGR2_SPF_Msk (0x1U << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
  10735. #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
  10736. /****************** Bit definition for SYSCFG_SWPR register ****************/
  10737. #define SYSCFG_SWPR_PAGE0_Pos (0U)
  10738. #define SYSCFG_SWPR_PAGE0_Msk (0x1U << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
  10739. #define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 */
  10740. #define SYSCFG_SWPR_PAGE1_Pos (1U)
  10741. #define SYSCFG_SWPR_PAGE1_Msk (0x1U << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
  10742. #define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 */
  10743. #define SYSCFG_SWPR_PAGE2_Pos (2U)
  10744. #define SYSCFG_SWPR_PAGE2_Msk (0x1U << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
  10745. #define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 */
  10746. #define SYSCFG_SWPR_PAGE3_Pos (3U)
  10747. #define SYSCFG_SWPR_PAGE3_Msk (0x1U << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
  10748. #define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 */
  10749. #define SYSCFG_SWPR_PAGE4_Pos (4U)
  10750. #define SYSCFG_SWPR_PAGE4_Msk (0x1U << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
  10751. #define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 */
  10752. #define SYSCFG_SWPR_PAGE5_Pos (5U)
  10753. #define SYSCFG_SWPR_PAGE5_Msk (0x1U << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
  10754. #define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 */
  10755. #define SYSCFG_SWPR_PAGE6_Pos (6U)
  10756. #define SYSCFG_SWPR_PAGE6_Msk (0x1U << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
  10757. #define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 */
  10758. #define SYSCFG_SWPR_PAGE7_Pos (7U)
  10759. #define SYSCFG_SWPR_PAGE7_Msk (0x1U << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
  10760. #define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 */
  10761. #define SYSCFG_SWPR_PAGE8_Pos (8U)
  10762. #define SYSCFG_SWPR_PAGE8_Msk (0x1U << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
  10763. #define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 */
  10764. #define SYSCFG_SWPR_PAGE9_Pos (9U)
  10765. #define SYSCFG_SWPR_PAGE9_Msk (0x1U << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
  10766. #define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 */
  10767. #define SYSCFG_SWPR_PAGE10_Pos (10U)
  10768. #define SYSCFG_SWPR_PAGE10_Msk (0x1U << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
  10769. #define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10*/
  10770. #define SYSCFG_SWPR_PAGE11_Pos (11U)
  10771. #define SYSCFG_SWPR_PAGE11_Msk (0x1U << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
  10772. #define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11*/
  10773. #define SYSCFG_SWPR_PAGE12_Pos (12U)
  10774. #define SYSCFG_SWPR_PAGE12_Msk (0x1U << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
  10775. #define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12*/
  10776. #define SYSCFG_SWPR_PAGE13_Pos (13U)
  10777. #define SYSCFG_SWPR_PAGE13_Msk (0x1U << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
  10778. #define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13*/
  10779. #define SYSCFG_SWPR_PAGE14_Pos (14U)
  10780. #define SYSCFG_SWPR_PAGE14_Msk (0x1U << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
  10781. #define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14*/
  10782. #define SYSCFG_SWPR_PAGE15_Pos (15U)
  10783. #define SYSCFG_SWPR_PAGE15_Msk (0x1U << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
  10784. #define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15*/
  10785. /****************** Bit definition for SYSCFG_SKR register ****************/
  10786. #define SYSCFG_SKR_KEY_Pos (0U)
  10787. #define SYSCFG_SKR_KEY_Msk (0xFFU << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
  10788. #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */
  10789. /******************************************************************************/
  10790. /* */
  10791. /* TIM */
  10792. /* */
  10793. /******************************************************************************/
  10794. /******************* Bit definition for TIM_CR1 register ********************/
  10795. #define TIM_CR1_CEN_Pos (0U)
  10796. #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
  10797. #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
  10798. #define TIM_CR1_UDIS_Pos (1U)
  10799. #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
  10800. #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
  10801. #define TIM_CR1_URS_Pos (2U)
  10802. #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
  10803. #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
  10804. #define TIM_CR1_OPM_Pos (3U)
  10805. #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
  10806. #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
  10807. #define TIM_CR1_DIR_Pos (4U)
  10808. #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
  10809. #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
  10810. #define TIM_CR1_CMS_Pos (5U)
  10811. #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
  10812. #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
  10813. #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
  10814. #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
  10815. #define TIM_CR1_ARPE_Pos (7U)
  10816. #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
  10817. #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
  10818. #define TIM_CR1_CKD_Pos (8U)
  10819. #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
  10820. #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
  10821. #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
  10822. #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
  10823. #define TIM_CR1_UIFREMAP_Pos (11U)
  10824. #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
  10825. #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
  10826. /******************* Bit definition for TIM_CR2 register ********************/
  10827. #define TIM_CR2_CCPC_Pos (0U)
  10828. #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
  10829. #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
  10830. #define TIM_CR2_CCUS_Pos (2U)
  10831. #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
  10832. #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
  10833. #define TIM_CR2_CCDS_Pos (3U)
  10834. #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
  10835. #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
  10836. #define TIM_CR2_MMS_Pos (4U)
  10837. #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
  10838. #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
  10839. #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
  10840. #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
  10841. #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
  10842. #define TIM_CR2_TI1S_Pos (7U)
  10843. #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
  10844. #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
  10845. #define TIM_CR2_OIS1_Pos (8U)
  10846. #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
  10847. #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
  10848. #define TIM_CR2_OIS1N_Pos (9U)
  10849. #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
  10850. #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
  10851. #define TIM_CR2_OIS2_Pos (10U)
  10852. #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
  10853. #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
  10854. #define TIM_CR2_OIS2N_Pos (11U)
  10855. #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
  10856. #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
  10857. #define TIM_CR2_OIS3_Pos (12U)
  10858. #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
  10859. #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
  10860. #define TIM_CR2_OIS3N_Pos (13U)
  10861. #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
  10862. #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
  10863. #define TIM_CR2_OIS4_Pos (14U)
  10864. #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
  10865. #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
  10866. #define TIM_CR2_OIS5_Pos (16U)
  10867. #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
  10868. #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
  10869. #define TIM_CR2_OIS6_Pos (18U)
  10870. #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
  10871. #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
  10872. #define TIM_CR2_MMS2_Pos (20U)
  10873. #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
  10874. #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
  10875. #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
  10876. #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
  10877. #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
  10878. #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
  10879. /******************* Bit definition for TIM_SMCR register *******************/
  10880. #define TIM_SMCR_SMS_Pos (0U)
  10881. #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
  10882. #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
  10883. #define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
  10884. #define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
  10885. #define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
  10886. #define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
  10887. #define TIM_SMCR_OCCS_Pos (3U)
  10888. #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
  10889. #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
  10890. #define TIM_SMCR_TS_Pos (4U)
  10891. #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
  10892. #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
  10893. #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
  10894. #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
  10895. #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
  10896. #define TIM_SMCR_MSM_Pos (7U)
  10897. #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
  10898. #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
  10899. #define TIM_SMCR_ETF_Pos (8U)
  10900. #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
  10901. #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
  10902. #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
  10903. #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
  10904. #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
  10905. #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
  10906. #define TIM_SMCR_ETPS_Pos (12U)
  10907. #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
  10908. #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
  10909. #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
  10910. #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
  10911. #define TIM_SMCR_ECE_Pos (14U)
  10912. #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
  10913. #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
  10914. #define TIM_SMCR_ETP_Pos (15U)
  10915. #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
  10916. #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
  10917. /******************* Bit definition for TIM_DIER register *******************/
  10918. #define TIM_DIER_UIE_Pos (0U)
  10919. #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
  10920. #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
  10921. #define TIM_DIER_CC1IE_Pos (1U)
  10922. #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
  10923. #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
  10924. #define TIM_DIER_CC2IE_Pos (2U)
  10925. #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
  10926. #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
  10927. #define TIM_DIER_CC3IE_Pos (3U)
  10928. #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
  10929. #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
  10930. #define TIM_DIER_CC4IE_Pos (4U)
  10931. #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
  10932. #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
  10933. #define TIM_DIER_COMIE_Pos (5U)
  10934. #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
  10935. #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
  10936. #define TIM_DIER_TIE_Pos (6U)
  10937. #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
  10938. #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
  10939. #define TIM_DIER_BIE_Pos (7U)
  10940. #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
  10941. #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
  10942. #define TIM_DIER_UDE_Pos (8U)
  10943. #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
  10944. #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
  10945. #define TIM_DIER_CC1DE_Pos (9U)
  10946. #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
  10947. #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
  10948. #define TIM_DIER_CC2DE_Pos (10U)
  10949. #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
  10950. #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
  10951. #define TIM_DIER_CC3DE_Pos (11U)
  10952. #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
  10953. #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
  10954. #define TIM_DIER_CC4DE_Pos (12U)
  10955. #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
  10956. #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
  10957. #define TIM_DIER_COMDE_Pos (13U)
  10958. #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
  10959. #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
  10960. #define TIM_DIER_TDE_Pos (14U)
  10961. #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
  10962. #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
  10963. /******************** Bit definition for TIM_SR register ********************/
  10964. #define TIM_SR_UIF_Pos (0U)
  10965. #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
  10966. #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
  10967. #define TIM_SR_CC1IF_Pos (1U)
  10968. #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
  10969. #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
  10970. #define TIM_SR_CC2IF_Pos (2U)
  10971. #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
  10972. #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
  10973. #define TIM_SR_CC3IF_Pos (3U)
  10974. #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
  10975. #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
  10976. #define TIM_SR_CC4IF_Pos (4U)
  10977. #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
  10978. #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
  10979. #define TIM_SR_COMIF_Pos (5U)
  10980. #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
  10981. #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
  10982. #define TIM_SR_TIF_Pos (6U)
  10983. #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
  10984. #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
  10985. #define TIM_SR_BIF_Pos (7U)
  10986. #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
  10987. #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
  10988. #define TIM_SR_B2IF_Pos (8U)
  10989. #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
  10990. #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
  10991. #define TIM_SR_CC1OF_Pos (9U)
  10992. #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
  10993. #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
  10994. #define TIM_SR_CC2OF_Pos (10U)
  10995. #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
  10996. #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
  10997. #define TIM_SR_CC3OF_Pos (11U)
  10998. #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
  10999. #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
  11000. #define TIM_SR_CC4OF_Pos (12U)
  11001. #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
  11002. #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
  11003. #define TIM_SR_SBIF_Pos (13U)
  11004. #define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
  11005. #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
  11006. #define TIM_SR_CC5IF_Pos (16U)
  11007. #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
  11008. #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
  11009. #define TIM_SR_CC6IF_Pos (17U)
  11010. #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
  11011. #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
  11012. /******************* Bit definition for TIM_EGR register ********************/
  11013. #define TIM_EGR_UG_Pos (0U)
  11014. #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
  11015. #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
  11016. #define TIM_EGR_CC1G_Pos (1U)
  11017. #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
  11018. #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
  11019. #define TIM_EGR_CC2G_Pos (2U)
  11020. #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
  11021. #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
  11022. #define TIM_EGR_CC3G_Pos (3U)
  11023. #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
  11024. #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
  11025. #define TIM_EGR_CC4G_Pos (4U)
  11026. #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
  11027. #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
  11028. #define TIM_EGR_COMG_Pos (5U)
  11029. #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
  11030. #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
  11031. #define TIM_EGR_TG_Pos (6U)
  11032. #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
  11033. #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
  11034. #define TIM_EGR_BG_Pos (7U)
  11035. #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
  11036. #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
  11037. #define TIM_EGR_B2G_Pos (8U)
  11038. #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
  11039. #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
  11040. /****************** Bit definition for TIM_CCMR1 register *******************/
  11041. #define TIM_CCMR1_CC1S_Pos (0U)
  11042. #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
  11043. #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
  11044. #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
  11045. #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
  11046. #define TIM_CCMR1_OC1FE_Pos (2U)
  11047. #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
  11048. #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
  11049. #define TIM_CCMR1_OC1PE_Pos (3U)
  11050. #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
  11051. #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
  11052. #define TIM_CCMR1_OC1M_Pos (4U)
  11053. #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
  11054. #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
  11055. #define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
  11056. #define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
  11057. #define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
  11058. #define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
  11059. #define TIM_CCMR1_OC1CE_Pos (7U)
  11060. #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
  11061. #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
  11062. #define TIM_CCMR1_CC2S_Pos (8U)
  11063. #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
  11064. #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
  11065. #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
  11066. #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
  11067. #define TIM_CCMR1_OC2FE_Pos (10U)
  11068. #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
  11069. #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
  11070. #define TIM_CCMR1_OC2PE_Pos (11U)
  11071. #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
  11072. #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
  11073. #define TIM_CCMR1_OC2M_Pos (12U)
  11074. #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
  11075. #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
  11076. #define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
  11077. #define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
  11078. #define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
  11079. #define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
  11080. #define TIM_CCMR1_OC2CE_Pos (15U)
  11081. #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
  11082. #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
  11083. /*----------------------------------------------------------------------------*/
  11084. #define TIM_CCMR1_IC1PSC_Pos (2U)
  11085. #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
  11086. #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
  11087. #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
  11088. #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
  11089. #define TIM_CCMR1_IC1F_Pos (4U)
  11090. #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
  11091. #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
  11092. #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
  11093. #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
  11094. #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
  11095. #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
  11096. #define TIM_CCMR1_IC2PSC_Pos (10U)
  11097. #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
  11098. #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
  11099. #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
  11100. #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
  11101. #define TIM_CCMR1_IC2F_Pos (12U)
  11102. #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
  11103. #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
  11104. #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
  11105. #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
  11106. #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
  11107. #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
  11108. /****************** Bit definition for TIM_CCMR2 register *******************/
  11109. #define TIM_CCMR2_CC3S_Pos (0U)
  11110. #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
  11111. #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
  11112. #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
  11113. #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
  11114. #define TIM_CCMR2_OC3FE_Pos (2U)
  11115. #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
  11116. #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
  11117. #define TIM_CCMR2_OC3PE_Pos (3U)
  11118. #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
  11119. #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
  11120. #define TIM_CCMR2_OC3M_Pos (4U)
  11121. #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
  11122. #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
  11123. #define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
  11124. #define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
  11125. #define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
  11126. #define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
  11127. #define TIM_CCMR2_OC3CE_Pos (7U)
  11128. #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
  11129. #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
  11130. #define TIM_CCMR2_CC4S_Pos (8U)
  11131. #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
  11132. #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
  11133. #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
  11134. #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
  11135. #define TIM_CCMR2_OC4FE_Pos (10U)
  11136. #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
  11137. #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
  11138. #define TIM_CCMR2_OC4PE_Pos (11U)
  11139. #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
  11140. #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
  11141. #define TIM_CCMR2_OC4M_Pos (12U)
  11142. #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
  11143. #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
  11144. #define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
  11145. #define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
  11146. #define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
  11147. #define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
  11148. #define TIM_CCMR2_OC4CE_Pos (15U)
  11149. #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
  11150. #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
  11151. /*----------------------------------------------------------------------------*/
  11152. #define TIM_CCMR2_IC3PSC_Pos (2U)
  11153. #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
  11154. #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
  11155. #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
  11156. #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
  11157. #define TIM_CCMR2_IC3F_Pos (4U)
  11158. #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
  11159. #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
  11160. #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
  11161. #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
  11162. #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
  11163. #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
  11164. #define TIM_CCMR2_IC4PSC_Pos (10U)
  11165. #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
  11166. #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
  11167. #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
  11168. #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
  11169. #define TIM_CCMR2_IC4F_Pos (12U)
  11170. #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
  11171. #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
  11172. #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
  11173. #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
  11174. #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
  11175. #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
  11176. /****************** Bit definition for TIM_CCMR3 register *******************/
  11177. #define TIM_CCMR3_OC5FE_Pos (2U)
  11178. #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
  11179. #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
  11180. #define TIM_CCMR3_OC5PE_Pos (3U)
  11181. #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
  11182. #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
  11183. #define TIM_CCMR3_OC5M_Pos (4U)
  11184. #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
  11185. #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
  11186. #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
  11187. #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
  11188. #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
  11189. #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
  11190. #define TIM_CCMR3_OC5CE_Pos (7U)
  11191. #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
  11192. #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
  11193. #define TIM_CCMR3_OC6FE_Pos (10U)
  11194. #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
  11195. #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
  11196. #define TIM_CCMR3_OC6PE_Pos (11U)
  11197. #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
  11198. #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
  11199. #define TIM_CCMR3_OC6M_Pos (12U)
  11200. #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
  11201. #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
  11202. #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
  11203. #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
  11204. #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
  11205. #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
  11206. #define TIM_CCMR3_OC6CE_Pos (15U)
  11207. #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
  11208. #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
  11209. /******************* Bit definition for TIM_CCER register *******************/
  11210. #define TIM_CCER_CC1E_Pos (0U)
  11211. #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
  11212. #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
  11213. #define TIM_CCER_CC1P_Pos (1U)
  11214. #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
  11215. #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
  11216. #define TIM_CCER_CC1NE_Pos (2U)
  11217. #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
  11218. #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
  11219. #define TIM_CCER_CC1NP_Pos (3U)
  11220. #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
  11221. #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
  11222. #define TIM_CCER_CC2E_Pos (4U)
  11223. #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
  11224. #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
  11225. #define TIM_CCER_CC2P_Pos (5U)
  11226. #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
  11227. #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
  11228. #define TIM_CCER_CC2NE_Pos (6U)
  11229. #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
  11230. #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
  11231. #define TIM_CCER_CC2NP_Pos (7U)
  11232. #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
  11233. #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
  11234. #define TIM_CCER_CC3E_Pos (8U)
  11235. #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
  11236. #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
  11237. #define TIM_CCER_CC3P_Pos (9U)
  11238. #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
  11239. #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
  11240. #define TIM_CCER_CC3NE_Pos (10U)
  11241. #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
  11242. #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
  11243. #define TIM_CCER_CC3NP_Pos (11U)
  11244. #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
  11245. #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
  11246. #define TIM_CCER_CC4E_Pos (12U)
  11247. #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
  11248. #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
  11249. #define TIM_CCER_CC4P_Pos (13U)
  11250. #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
  11251. #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
  11252. #define TIM_CCER_CC4NP_Pos (15U)
  11253. #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
  11254. #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
  11255. #define TIM_CCER_CC5E_Pos (16U)
  11256. #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
  11257. #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
  11258. #define TIM_CCER_CC5P_Pos (17U)
  11259. #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
  11260. #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
  11261. #define TIM_CCER_CC6E_Pos (20U)
  11262. #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
  11263. #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
  11264. #define TIM_CCER_CC6P_Pos (21U)
  11265. #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
  11266. #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
  11267. /******************* Bit definition for TIM_CNT register ********************/
  11268. #define TIM_CNT_CNT_Pos (0U)
  11269. #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
  11270. #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
  11271. #define TIM_CNT_UIFCPY_Pos (31U)
  11272. #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
  11273. #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
  11274. /******************* Bit definition for TIM_PSC register ********************/
  11275. #define TIM_PSC_PSC_Pos (0U)
  11276. #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
  11277. #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
  11278. /******************* Bit definition for TIM_ARR register ********************/
  11279. #define TIM_ARR_ARR_Pos (0U)
  11280. #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
  11281. #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
  11282. /******************* Bit definition for TIM_RCR register ********************/
  11283. #define TIM_RCR_REP_Pos (0U)
  11284. #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
  11285. #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
  11286. /******************* Bit definition for TIM_CCR1 register *******************/
  11287. #define TIM_CCR1_CCR1_Pos (0U)
  11288. #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
  11289. #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
  11290. /******************* Bit definition for TIM_CCR2 register *******************/
  11291. #define TIM_CCR2_CCR2_Pos (0U)
  11292. #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
  11293. #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
  11294. /******************* Bit definition for TIM_CCR3 register *******************/
  11295. #define TIM_CCR3_CCR3_Pos (0U)
  11296. #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
  11297. #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
  11298. /******************* Bit definition for TIM_CCR4 register *******************/
  11299. #define TIM_CCR4_CCR4_Pos (0U)
  11300. #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
  11301. #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
  11302. /******************* Bit definition for TIM_CCR5 register *******************/
  11303. #define TIM_CCR5_CCR5_Pos (0U)
  11304. #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
  11305. #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
  11306. #define TIM_CCR5_GC5C1_Pos (29U)
  11307. #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
  11308. #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
  11309. #define TIM_CCR5_GC5C2_Pos (30U)
  11310. #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
  11311. #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
  11312. #define TIM_CCR5_GC5C3_Pos (31U)
  11313. #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
  11314. #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
  11315. /******************* Bit definition for TIM_CCR6 register *******************/
  11316. #define TIM_CCR6_CCR6_Pos (0U)
  11317. #define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
  11318. #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
  11319. /******************* Bit definition for TIM_BDTR register *******************/
  11320. #define TIM_BDTR_DTG_Pos (0U)
  11321. #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
  11322. #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
  11323. #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
  11324. #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
  11325. #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
  11326. #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
  11327. #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
  11328. #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
  11329. #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
  11330. #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
  11331. #define TIM_BDTR_LOCK_Pos (8U)
  11332. #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
  11333. #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
  11334. #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
  11335. #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
  11336. #define TIM_BDTR_OSSI_Pos (10U)
  11337. #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
  11338. #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
  11339. #define TIM_BDTR_OSSR_Pos (11U)
  11340. #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
  11341. #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
  11342. #define TIM_BDTR_BKE_Pos (12U)
  11343. #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
  11344. #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
  11345. #define TIM_BDTR_BKP_Pos (13U)
  11346. #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
  11347. #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
  11348. #define TIM_BDTR_AOE_Pos (14U)
  11349. #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
  11350. #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
  11351. #define TIM_BDTR_MOE_Pos (15U)
  11352. #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
  11353. #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
  11354. #define TIM_BDTR_BKF_Pos (16U)
  11355. #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
  11356. #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
  11357. #define TIM_BDTR_BK2F_Pos (20U)
  11358. #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
  11359. #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
  11360. #define TIM_BDTR_BK2E_Pos (24U)
  11361. #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
  11362. #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
  11363. #define TIM_BDTR_BK2P_Pos (25U)
  11364. #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
  11365. #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
  11366. /******************* Bit definition for TIM_DCR register ********************/
  11367. #define TIM_DCR_DBA_Pos (0U)
  11368. #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
  11369. #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
  11370. #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
  11371. #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
  11372. #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
  11373. #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
  11374. #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
  11375. #define TIM_DCR_DBL_Pos (8U)
  11376. #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
  11377. #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
  11378. #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
  11379. #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
  11380. #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
  11381. #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
  11382. #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
  11383. /******************* Bit definition for TIM_DMAR register *******************/
  11384. #define TIM_DMAR_DMAB_Pos (0U)
  11385. #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
  11386. #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
  11387. /******************* Bit definition for TIM1_OR1 register *******************/
  11388. #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
  11389. #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
  11390. #define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
  11391. #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
  11392. #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
  11393. #define TIM1_OR1_TI1_RMP_Pos (4U)
  11394. #define TIM1_OR1_TI1_RMP_Msk (0x1U << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
  11395. #define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */
  11396. /******************* Bit definition for TIM1_OR2 register *******************/
  11397. #define TIM1_OR2_BKINE_Pos (0U)
  11398. #define TIM1_OR2_BKINE_Msk (0x1U << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */
  11399. #define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */
  11400. #define TIM1_OR2_BKCMP1E_Pos (1U)
  11401. #define TIM1_OR2_BKCMP1E_Msk (0x1U << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
  11402. #define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
  11403. #define TIM1_OR2_BKCMP2E_Pos (2U)
  11404. #define TIM1_OR2_BKCMP2E_Msk (0x1U << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
  11405. #define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
  11406. #define TIM1_OR2_BKINP_Pos (9U)
  11407. #define TIM1_OR2_BKINP_Msk (0x1U << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */
  11408. #define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
  11409. #define TIM1_OR2_BKCMP1P_Pos (10U)
  11410. #define TIM1_OR2_BKCMP1P_Msk (0x1U << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
  11411. #define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
  11412. #define TIM1_OR2_BKCMP2P_Pos (11U)
  11413. #define TIM1_OR2_BKCMP2P_Msk (0x1U << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
  11414. #define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
  11415. #define TIM1_OR2_ETRSEL_Pos (14U)
  11416. #define TIM1_OR2_ETRSEL_Msk (0x7U << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
  11417. #define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
  11418. #define TIM1_OR2_ETRSEL_0 (0x1U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */
  11419. #define TIM1_OR2_ETRSEL_1 (0x2U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */
  11420. #define TIM1_OR2_ETRSEL_2 (0x4U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */
  11421. /******************* Bit definition for TIM1_OR3 register *******************/
  11422. #define TIM1_OR3_BK2INE_Pos (0U)
  11423. #define TIM1_OR3_BK2INE_Msk (0x1U << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */
  11424. #define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
  11425. #define TIM1_OR3_BK2CMP1E_Pos (1U)
  11426. #define TIM1_OR3_BK2CMP1E_Msk (0x1U << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
  11427. #define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
  11428. #define TIM1_OR3_BK2CMP2E_Pos (2U)
  11429. #define TIM1_OR3_BK2CMP2E_Msk (0x1U << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
  11430. #define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
  11431. #define TIM1_OR3_BK2INP_Pos (9U)
  11432. #define TIM1_OR3_BK2INP_Msk (0x1U << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */
  11433. #define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
  11434. #define TIM1_OR3_BK2CMP1P_Pos (10U)
  11435. #define TIM1_OR3_BK2CMP1P_Msk (0x1U << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
  11436. #define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
  11437. #define TIM1_OR3_BK2CMP2P_Pos (11U)
  11438. #define TIM1_OR3_BK2CMP2P_Msk (0x1U << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
  11439. #define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
  11440. /******************* Bit definition for TIM2_OR1 register *******************/
  11441. #define TIM2_OR1_ITR1_RMP_Pos (0U)
  11442. #define TIM2_OR1_ITR1_RMP_Msk (0x1U << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */
  11443. #define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
  11444. #define TIM2_OR1_ETR1_RMP_Pos (1U)
  11445. #define TIM2_OR1_ETR1_RMP_Msk (0x1U << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */
  11446. #define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */
  11447. #define TIM2_OR1_TI4_RMP_Pos (2U)
  11448. #define TIM2_OR1_TI4_RMP_Msk (0x3U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */
  11449. #define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
  11450. #define TIM2_OR1_TI4_RMP_0 (0x1U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */
  11451. #define TIM2_OR1_TI4_RMP_1 (0x2U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */
  11452. /******************* Bit definition for TIM2_OR2 register *******************/
  11453. #define TIM2_OR2_ETRSEL_Pos (14U)
  11454. #define TIM2_OR2_ETRSEL_Msk (0x7U << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
  11455. #define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
  11456. #define TIM2_OR2_ETRSEL_0 (0x1U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */
  11457. #define TIM2_OR2_ETRSEL_1 (0x2U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */
  11458. #define TIM2_OR2_ETRSEL_2 (0x4U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */
  11459. /******************* Bit definition for TIM15_OR1 register ******************/
  11460. #define TIM15_OR1_TI1_RMP_Pos (0U)
  11461. #define TIM15_OR1_TI1_RMP_Msk (0x1U << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
  11462. #define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */
  11463. #define TIM15_OR1_ENCODER_MODE_Pos (1U)
  11464. #define TIM15_OR1_ENCODER_MODE_Msk (0x3U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */
  11465. #define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
  11466. #define TIM15_OR1_ENCODER_MODE_0 (0x1U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */
  11467. #define TIM15_OR1_ENCODER_MODE_1 (0x2U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */
  11468. /******************* Bit definition for TIM15_OR2 register ******************/
  11469. #define TIM15_OR2_BKINE_Pos (0U)
  11470. #define TIM15_OR2_BKINE_Msk (0x1U << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */
  11471. #define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */
  11472. #define TIM15_OR2_BKCMP1E_Pos (1U)
  11473. #define TIM15_OR2_BKCMP1E_Msk (0x1U << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
  11474. #define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
  11475. #define TIM15_OR2_BKCMP2E_Pos (2U)
  11476. #define TIM15_OR2_BKCMP2E_Msk (0x1U << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
  11477. #define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
  11478. #define TIM15_OR2_BKINP_Pos (9U)
  11479. #define TIM15_OR2_BKINP_Msk (0x1U << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */
  11480. #define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
  11481. #define TIM15_OR2_BKCMP1P_Pos (10U)
  11482. #define TIM15_OR2_BKCMP1P_Msk (0x1U << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
  11483. #define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
  11484. #define TIM15_OR2_BKCMP2P_Pos (11U)
  11485. #define TIM15_OR2_BKCMP2P_Msk (0x1U << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
  11486. #define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
  11487. /******************* Bit definition for TIM16_OR1 register ******************/
  11488. #define TIM16_OR1_TI1_RMP_Pos (0U)
  11489. #define TIM16_OR1_TI1_RMP_Msk (0x7U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
  11490. #define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM16 Input Capture 1 remap) */
  11491. #define TIM16_OR1_TI1_RMP_0 (0x1U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
  11492. #define TIM16_OR1_TI1_RMP_1 (0x2U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
  11493. #define TIM16_OR1_TI1_RMP_2 (0x4U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
  11494. /******************* Bit definition for TIM16_OR2 register ******************/
  11495. #define TIM16_OR2_BKINE_Pos (0U)
  11496. #define TIM16_OR2_BKINE_Msk (0x1U << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */
  11497. #define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */
  11498. #define TIM16_OR2_BKCMP1E_Pos (1U)
  11499. #define TIM16_OR2_BKCMP1E_Msk (0x1U << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
  11500. #define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
  11501. #define TIM16_OR2_BKCMP2E_Pos (2U)
  11502. #define TIM16_OR2_BKCMP2E_Msk (0x1U << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
  11503. #define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
  11504. #define TIM16_OR2_BKINP_Pos (9U)
  11505. #define TIM16_OR2_BKINP_Msk (0x1U << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */
  11506. #define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
  11507. #define TIM16_OR2_BKCMP1P_Pos (10U)
  11508. #define TIM16_OR2_BKCMP1P_Msk (0x1U << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
  11509. #define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
  11510. #define TIM16_OR2_BKCMP2P_Pos (11U)
  11511. #define TIM16_OR2_BKCMP2P_Msk (0x1U << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
  11512. #define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
  11513. /******************************************************************************/
  11514. /* */
  11515. /* Low Power Timer (LPTTIM) */
  11516. /* */
  11517. /******************************************************************************/
  11518. /****************** Bit definition for LPTIM_ISR register *******************/
  11519. #define LPTIM_ISR_CMPM_Pos (0U)
  11520. #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
  11521. #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
  11522. #define LPTIM_ISR_ARRM_Pos (1U)
  11523. #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
  11524. #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
  11525. #define LPTIM_ISR_EXTTRIG_Pos (2U)
  11526. #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
  11527. #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
  11528. #define LPTIM_ISR_CMPOK_Pos (3U)
  11529. #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
  11530. #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
  11531. #define LPTIM_ISR_ARROK_Pos (4U)
  11532. #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
  11533. #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
  11534. #define LPTIM_ISR_UP_Pos (5U)
  11535. #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
  11536. #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
  11537. #define LPTIM_ISR_DOWN_Pos (6U)
  11538. #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
  11539. #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
  11540. /****************** Bit definition for LPTIM_ICR register *******************/
  11541. #define LPTIM_ICR_CMPMCF_Pos (0U)
  11542. #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
  11543. #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
  11544. #define LPTIM_ICR_ARRMCF_Pos (1U)
  11545. #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
  11546. #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
  11547. #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
  11548. #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
  11549. #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
  11550. #define LPTIM_ICR_CMPOKCF_Pos (3U)
  11551. #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
  11552. #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
  11553. #define LPTIM_ICR_ARROKCF_Pos (4U)
  11554. #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
  11555. #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
  11556. #define LPTIM_ICR_UPCF_Pos (5U)
  11557. #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
  11558. #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
  11559. #define LPTIM_ICR_DOWNCF_Pos (6U)
  11560. #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
  11561. #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
  11562. /****************** Bit definition for LPTIM_IER register ********************/
  11563. #define LPTIM_IER_CMPMIE_Pos (0U)
  11564. #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
  11565. #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
  11566. #define LPTIM_IER_ARRMIE_Pos (1U)
  11567. #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
  11568. #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
  11569. #define LPTIM_IER_EXTTRIGIE_Pos (2U)
  11570. #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
  11571. #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
  11572. #define LPTIM_IER_CMPOKIE_Pos (3U)
  11573. #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
  11574. #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
  11575. #define LPTIM_IER_ARROKIE_Pos (4U)
  11576. #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
  11577. #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
  11578. #define LPTIM_IER_UPIE_Pos (5U)
  11579. #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
  11580. #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
  11581. #define LPTIM_IER_DOWNIE_Pos (6U)
  11582. #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
  11583. #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
  11584. /****************** Bit definition for LPTIM_CFGR register *******************/
  11585. #define LPTIM_CFGR_CKSEL_Pos (0U)
  11586. #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
  11587. #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
  11588. #define LPTIM_CFGR_CKPOL_Pos (1U)
  11589. #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
  11590. #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
  11591. #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
  11592. #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
  11593. #define LPTIM_CFGR_CKFLT_Pos (3U)
  11594. #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
  11595. #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
  11596. #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
  11597. #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
  11598. #define LPTIM_CFGR_TRGFLT_Pos (6U)
  11599. #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
  11600. #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
  11601. #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
  11602. #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
  11603. #define LPTIM_CFGR_PRESC_Pos (9U)
  11604. #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
  11605. #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
  11606. #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
  11607. #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
  11608. #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
  11609. #define LPTIM_CFGR_TRIGSEL_Pos (13U)
  11610. #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
  11611. #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
  11612. #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
  11613. #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
  11614. #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
  11615. #define LPTIM_CFGR_TRIGEN_Pos (17U)
  11616. #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
  11617. #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
  11618. #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
  11619. #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
  11620. #define LPTIM_CFGR_TIMOUT_Pos (19U)
  11621. #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
  11622. #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
  11623. #define LPTIM_CFGR_WAVE_Pos (20U)
  11624. #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
  11625. #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
  11626. #define LPTIM_CFGR_WAVPOL_Pos (21U)
  11627. #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
  11628. #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
  11629. #define LPTIM_CFGR_PRELOAD_Pos (22U)
  11630. #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
  11631. #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
  11632. #define LPTIM_CFGR_COUNTMODE_Pos (23U)
  11633. #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
  11634. #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
  11635. #define LPTIM_CFGR_ENC_Pos (24U)
  11636. #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
  11637. #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
  11638. /****************** Bit definition for LPTIM_CR register ********************/
  11639. #define LPTIM_CR_ENABLE_Pos (0U)
  11640. #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
  11641. #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
  11642. #define LPTIM_CR_SNGSTRT_Pos (1U)
  11643. #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
  11644. #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
  11645. #define LPTIM_CR_CNTSTRT_Pos (2U)
  11646. #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
  11647. #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
  11648. /****************** Bit definition for LPTIM_CMP register *******************/
  11649. #define LPTIM_CMP_CMP_Pos (0U)
  11650. #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
  11651. #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
  11652. /****************** Bit definition for LPTIM_ARR register *******************/
  11653. #define LPTIM_ARR_ARR_Pos (0U)
  11654. #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
  11655. #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
  11656. /****************** Bit definition for LPTIM_CNT register *******************/
  11657. #define LPTIM_CNT_CNT_Pos (0U)
  11658. #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
  11659. #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
  11660. /****************** Bit definition for LPTIM_OR register ********************/
  11661. #define LPTIM_OR_OR_Pos (0U)
  11662. #define LPTIM_OR_OR_Msk (0x3U << LPTIM_OR_OR_Pos) /*!< 0x00000003 */
  11663. #define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */
  11664. #define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */
  11665. #define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */
  11666. /******************************************************************************/
  11667. /* */
  11668. /* Analog Comparators (COMP) */
  11669. /* */
  11670. /******************************************************************************/
  11671. /********************** Bit definition for COMP_CSR register ****************/
  11672. #define COMP_CSR_EN_Pos (0U)
  11673. #define COMP_CSR_EN_Msk (0x1U << COMP_CSR_EN_Pos) /*!< 0x00000001 */
  11674. #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
  11675. #define COMP_CSR_PWRMODE_Pos (2U)
  11676. #define COMP_CSR_PWRMODE_Msk (0x3U << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */
  11677. #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
  11678. #define COMP_CSR_PWRMODE_0 (0x1U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */
  11679. #define COMP_CSR_PWRMODE_1 (0x2U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */
  11680. #define COMP_CSR_INMSEL_Pos (4U)
  11681. #define COMP_CSR_INMSEL_Msk (0x7U << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
  11682. #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
  11683. #define COMP_CSR_INMSEL_0 (0x1U << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
  11684. #define COMP_CSR_INMSEL_1 (0x2U << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
  11685. #define COMP_CSR_INMSEL_2 (0x4U << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
  11686. #define COMP_CSR_INPSEL_Pos (7U)
  11687. #define COMP_CSR_INPSEL_Msk (0x3U << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */
  11688. #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
  11689. #define COMP_CSR_INPSEL_0 (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
  11690. #define COMP_CSR_INPSEL_1 (0x2U << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
  11691. #define COMP_CSR_WINMODE_Pos (9U)
  11692. #define COMP_CSR_WINMODE_Msk (0x1U << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */
  11693. #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
  11694. #define COMP_CSR_POLARITY_Pos (15U)
  11695. #define COMP_CSR_POLARITY_Msk (0x1U << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
  11696. #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
  11697. #define COMP_CSR_HYST_Pos (16U)
  11698. #define COMP_CSR_HYST_Msk (0x3U << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
  11699. #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
  11700. #define COMP_CSR_HYST_0 (0x1U << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
  11701. #define COMP_CSR_HYST_1 (0x2U << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
  11702. #define COMP_CSR_BLANKING_Pos (18U)
  11703. #define COMP_CSR_BLANKING_Msk (0x7U << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
  11704. #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
  11705. #define COMP_CSR_BLANKING_0 (0x1U << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
  11706. #define COMP_CSR_BLANKING_1 (0x2U << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
  11707. #define COMP_CSR_BLANKING_2 (0x4U << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
  11708. #define COMP_CSR_BRGEN_Pos (22U)
  11709. #define COMP_CSR_BRGEN_Msk (0x1U << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
  11710. #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
  11711. #define COMP_CSR_SCALEN_Pos (23U)
  11712. #define COMP_CSR_SCALEN_Msk (0x1U << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
  11713. #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
  11714. #define COMP_CSR_INMESEL_Pos (25U)
  11715. #define COMP_CSR_INMESEL_Msk (0x3U << COMP_CSR_INMESEL_Pos) /*!< 0x06000000 */
  11716. #define COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk /*!< Comparator input minus extended selection */
  11717. #define COMP_CSR_INMESEL_0 (0x1U << COMP_CSR_INMESEL_Pos) /*!< 0x02000000 */
  11718. #define COMP_CSR_INMESEL_1 (0x2U << COMP_CSR_INMESEL_Pos) /*!< 0x04000000 */
  11719. #define COMP_CSR_VALUE_Pos (30U)
  11720. #define COMP_CSR_VALUE_Msk (0x1U << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
  11721. #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
  11722. #define COMP_CSR_LOCK_Pos (31U)
  11723. #define COMP_CSR_LOCK_Msk (0x1U << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
  11724. #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
  11725. /******************************************************************************/
  11726. /* */
  11727. /* Operational Amplifier (OPAMP) */
  11728. /* */
  11729. /******************************************************************************/
  11730. /********************* Bit definition for OPAMPx_CSR register ***************/
  11731. #define OPAMP_CSR_OPAMPxEN_Pos (0U)
  11732. #define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
  11733. #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
  11734. #define OPAMP_CSR_OPALPM_Pos (1U)
  11735. #define OPAMP_CSR_OPALPM_Msk (0x1U << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */
  11736. #define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */
  11737. #define OPAMP_CSR_OPAMODE_Pos (2U)
  11738. #define OPAMP_CSR_OPAMODE_Msk (0x3U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */
  11739. #define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */
  11740. #define OPAMP_CSR_OPAMODE_0 (0x1U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */
  11741. #define OPAMP_CSR_OPAMODE_1 (0x2U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */
  11742. #define OPAMP_CSR_PGGAIN_Pos (4U)
  11743. #define OPAMP_CSR_PGGAIN_Msk (0x3U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000030 */
  11744. #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
  11745. #define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000010 */
  11746. #define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000020 */
  11747. #define OPAMP_CSR_VMSEL_Pos (8U)
  11748. #define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000300 */
  11749. #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
  11750. #define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000100 */
  11751. #define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000200 */
  11752. #define OPAMP_CSR_VPSEL_Pos (10U)
  11753. #define OPAMP_CSR_VPSEL_Msk (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000400 */
  11754. #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
  11755. #define OPAMP_CSR_CALON_Pos (12U)
  11756. #define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */
  11757. #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
  11758. #define OPAMP_CSR_CALSEL_Pos (13U)
  11759. #define OPAMP_CSR_CALSEL_Msk (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
  11760. #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
  11761. #define OPAMP_CSR_USERTRIM_Pos (14U)
  11762. #define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */
  11763. #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
  11764. #define OPAMP_CSR_CALOUT_Pos (15U)
  11765. #define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */
  11766. #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
  11767. /********************* Bit definition for OPAMP1_CSR register ***************/
  11768. #define OPAMP1_CSR_OPAEN_Pos (0U)
  11769. #define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
  11770. #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
  11771. #define OPAMP1_CSR_OPALPM_Pos (1U)
  11772. #define OPAMP1_CSR_OPALPM_Msk (0x1U << OPAMP1_CSR_OPALPM_Pos) /*!< 0x00000002 */
  11773. #define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk /*!< Operational amplifier1 Low Power Mode */
  11774. #define OPAMP1_CSR_OPAMODE_Pos (2U)
  11775. #define OPAMP1_CSR_OPAMODE_Msk (0x3U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x0000000C */
  11776. #define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk /*!< Operational amplifier1 PGA mode */
  11777. #define OPAMP1_CSR_OPAMODE_0 (0x1U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000004 */
  11778. #define OPAMP1_CSR_OPAMODE_1 (0x2U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000008 */
  11779. #define OPAMP1_CSR_PGAGAIN_Pos (4U)
  11780. #define OPAMP1_CSR_PGAGAIN_Msk (0x3U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
  11781. #define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
  11782. #define OPAMP1_CSR_PGAGAIN_0 (0x1U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
  11783. #define OPAMP1_CSR_PGAGAIN_1 (0x2U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
  11784. #define OPAMP1_CSR_VMSEL_Pos (8U)
  11785. #define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000300 */
  11786. #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
  11787. #define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000100 */
  11788. #define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000200 */
  11789. #define OPAMP1_CSR_VPSEL_Pos (10U)
  11790. #define OPAMP1_CSR_VPSEL_Msk (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */
  11791. #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
  11792. #define OPAMP1_CSR_CALON_Pos (12U)
  11793. #define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00001000 */
  11794. #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
  11795. #define OPAMP1_CSR_CALSEL_Pos (13U)
  11796. #define OPAMP1_CSR_CALSEL_Msk (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
  11797. #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
  11798. #define OPAMP1_CSR_USERTRIM_Pos (14U)
  11799. #define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00004000 */
  11800. #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
  11801. #define OPAMP1_CSR_CALOUT_Pos (15U)
  11802. #define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x00008000 */
  11803. #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
  11804. #define OPAMP1_CSR_OPARANGE_Pos (31U)
  11805. #define OPAMP1_CSR_OPARANGE_Msk (0x1U << OPAMP1_CSR_OPARANGE_Pos) /*!< 0x80000000 */
  11806. #define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
  11807. /******************* Bit definition for OPAMP_OTR register ******************/
  11808. #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
  11809. #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
  11810. #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
  11811. #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
  11812. #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
  11813. #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
  11814. /******************* Bit definition for OPAMP1_OTR register ******************/
  11815. #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
  11816. #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
  11817. #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
  11818. #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
  11819. #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
  11820. #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
  11821. /******************* Bit definition for OPAMP_LPOTR register ****************/
  11822. #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
  11823. #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
  11824. #define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
  11825. #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
  11826. #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
  11827. #define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
  11828. /******************* Bit definition for OPAMP1_LPOTR register ****************/
  11829. #define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
  11830. #define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
  11831. #define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
  11832. #define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
  11833. #define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
  11834. #define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
  11835. /******************************************************************************/
  11836. /* */
  11837. /* Touch Sensing Controller (TSC) */
  11838. /* */
  11839. /******************************************************************************/
  11840. /******************* Bit definition for TSC_CR register *********************/
  11841. #define TSC_CR_TSCE_Pos (0U)
  11842. #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
  11843. #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
  11844. #define TSC_CR_START_Pos (1U)
  11845. #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
  11846. #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
  11847. #define TSC_CR_AM_Pos (2U)
  11848. #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
  11849. #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
  11850. #define TSC_CR_SYNCPOL_Pos (3U)
  11851. #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
  11852. #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
  11853. #define TSC_CR_IODEF_Pos (4U)
  11854. #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
  11855. #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
  11856. #define TSC_CR_MCV_Pos (5U)
  11857. #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
  11858. #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
  11859. #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
  11860. #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
  11861. #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
  11862. #define TSC_CR_PGPSC_Pos (12U)
  11863. #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
  11864. #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
  11865. #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
  11866. #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
  11867. #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
  11868. #define TSC_CR_SSPSC_Pos (15U)
  11869. #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
  11870. #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
  11871. #define TSC_CR_SSE_Pos (16U)
  11872. #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
  11873. #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
  11874. #define TSC_CR_SSD_Pos (17U)
  11875. #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
  11876. #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
  11877. #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
  11878. #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
  11879. #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
  11880. #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
  11881. #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
  11882. #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
  11883. #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
  11884. #define TSC_CR_CTPL_Pos (24U)
  11885. #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
  11886. #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
  11887. #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
  11888. #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
  11889. #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
  11890. #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
  11891. #define TSC_CR_CTPH_Pos (28U)
  11892. #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
  11893. #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
  11894. #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
  11895. #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
  11896. #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
  11897. #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
  11898. /******************* Bit definition for TSC_IER register ********************/
  11899. #define TSC_IER_EOAIE_Pos (0U)
  11900. #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
  11901. #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
  11902. #define TSC_IER_MCEIE_Pos (1U)
  11903. #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
  11904. #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
  11905. /******************* Bit definition for TSC_ICR register ********************/
  11906. #define TSC_ICR_EOAIC_Pos (0U)
  11907. #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
  11908. #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
  11909. #define TSC_ICR_MCEIC_Pos (1U)
  11910. #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
  11911. #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
  11912. /******************* Bit definition for TSC_ISR register ********************/
  11913. #define TSC_ISR_EOAF_Pos (0U)
  11914. #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
  11915. #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
  11916. #define TSC_ISR_MCEF_Pos (1U)
  11917. #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
  11918. #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
  11919. /******************* Bit definition for TSC_IOHCR register ******************/
  11920. #define TSC_IOHCR_G1_IO1_Pos (0U)
  11921. #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
  11922. #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
  11923. #define TSC_IOHCR_G1_IO2_Pos (1U)
  11924. #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
  11925. #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
  11926. #define TSC_IOHCR_G1_IO3_Pos (2U)
  11927. #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
  11928. #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
  11929. #define TSC_IOHCR_G1_IO4_Pos (3U)
  11930. #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
  11931. #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
  11932. #define TSC_IOHCR_G2_IO1_Pos (4U)
  11933. #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
  11934. #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
  11935. #define TSC_IOHCR_G2_IO2_Pos (5U)
  11936. #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
  11937. #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
  11938. #define TSC_IOHCR_G2_IO3_Pos (6U)
  11939. #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
  11940. #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
  11941. #define TSC_IOHCR_G2_IO4_Pos (7U)
  11942. #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
  11943. #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
  11944. #define TSC_IOHCR_G3_IO1_Pos (8U)
  11945. #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
  11946. #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
  11947. #define TSC_IOHCR_G3_IO2_Pos (9U)
  11948. #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
  11949. #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
  11950. #define TSC_IOHCR_G3_IO3_Pos (10U)
  11951. #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
  11952. #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
  11953. #define TSC_IOHCR_G3_IO4_Pos (11U)
  11954. #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
  11955. #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
  11956. #define TSC_IOHCR_G4_IO1_Pos (12U)
  11957. #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
  11958. #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
  11959. #define TSC_IOHCR_G4_IO2_Pos (13U)
  11960. #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
  11961. #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
  11962. #define TSC_IOHCR_G4_IO3_Pos (14U)
  11963. #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
  11964. #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
  11965. #define TSC_IOHCR_G4_IO4_Pos (15U)
  11966. #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
  11967. #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
  11968. #define TSC_IOHCR_G5_IO1_Pos (16U)
  11969. #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
  11970. #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
  11971. #define TSC_IOHCR_G5_IO2_Pos (17U)
  11972. #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
  11973. #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
  11974. #define TSC_IOHCR_G5_IO3_Pos (18U)
  11975. #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
  11976. #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
  11977. #define TSC_IOHCR_G5_IO4_Pos (19U)
  11978. #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
  11979. #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
  11980. #define TSC_IOHCR_G6_IO1_Pos (20U)
  11981. #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
  11982. #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
  11983. #define TSC_IOHCR_G6_IO2_Pos (21U)
  11984. #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
  11985. #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
  11986. #define TSC_IOHCR_G6_IO3_Pos (22U)
  11987. #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
  11988. #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
  11989. #define TSC_IOHCR_G6_IO4_Pos (23U)
  11990. #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
  11991. #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
  11992. #define TSC_IOHCR_G7_IO1_Pos (24U)
  11993. #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
  11994. #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
  11995. #define TSC_IOHCR_G7_IO2_Pos (25U)
  11996. #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
  11997. #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
  11998. #define TSC_IOHCR_G7_IO3_Pos (26U)
  11999. #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
  12000. #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
  12001. #define TSC_IOHCR_G7_IO4_Pos (27U)
  12002. #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
  12003. #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
  12004. /******************* Bit definition for TSC_IOASCR register *****************/
  12005. #define TSC_IOASCR_G1_IO1_Pos (0U)
  12006. #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
  12007. #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
  12008. #define TSC_IOASCR_G1_IO2_Pos (1U)
  12009. #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
  12010. #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
  12011. #define TSC_IOASCR_G1_IO3_Pos (2U)
  12012. #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
  12013. #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
  12014. #define TSC_IOASCR_G1_IO4_Pos (3U)
  12015. #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
  12016. #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
  12017. #define TSC_IOASCR_G2_IO1_Pos (4U)
  12018. #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
  12019. #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
  12020. #define TSC_IOASCR_G2_IO2_Pos (5U)
  12021. #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
  12022. #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
  12023. #define TSC_IOASCR_G2_IO3_Pos (6U)
  12024. #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
  12025. #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
  12026. #define TSC_IOASCR_G2_IO4_Pos (7U)
  12027. #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
  12028. #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
  12029. #define TSC_IOASCR_G3_IO1_Pos (8U)
  12030. #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
  12031. #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
  12032. #define TSC_IOASCR_G3_IO2_Pos (9U)
  12033. #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
  12034. #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
  12035. #define TSC_IOASCR_G3_IO3_Pos (10U)
  12036. #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
  12037. #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
  12038. #define TSC_IOASCR_G3_IO4_Pos (11U)
  12039. #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
  12040. #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
  12041. #define TSC_IOASCR_G4_IO1_Pos (12U)
  12042. #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
  12043. #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
  12044. #define TSC_IOASCR_G4_IO2_Pos (13U)
  12045. #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
  12046. #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
  12047. #define TSC_IOASCR_G4_IO3_Pos (14U)
  12048. #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
  12049. #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
  12050. #define TSC_IOASCR_G4_IO4_Pos (15U)
  12051. #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
  12052. #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
  12053. #define TSC_IOASCR_G5_IO1_Pos (16U)
  12054. #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
  12055. #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
  12056. #define TSC_IOASCR_G5_IO2_Pos (17U)
  12057. #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
  12058. #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
  12059. #define TSC_IOASCR_G5_IO3_Pos (18U)
  12060. #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
  12061. #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
  12062. #define TSC_IOASCR_G5_IO4_Pos (19U)
  12063. #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
  12064. #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
  12065. #define TSC_IOASCR_G6_IO1_Pos (20U)
  12066. #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
  12067. #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
  12068. #define TSC_IOASCR_G6_IO2_Pos (21U)
  12069. #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
  12070. #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
  12071. #define TSC_IOASCR_G6_IO3_Pos (22U)
  12072. #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
  12073. #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
  12074. #define TSC_IOASCR_G6_IO4_Pos (23U)
  12075. #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
  12076. #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
  12077. #define TSC_IOASCR_G7_IO1_Pos (24U)
  12078. #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
  12079. #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
  12080. #define TSC_IOASCR_G7_IO2_Pos (25U)
  12081. #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
  12082. #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
  12083. #define TSC_IOASCR_G7_IO3_Pos (26U)
  12084. #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
  12085. #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
  12086. #define TSC_IOASCR_G7_IO4_Pos (27U)
  12087. #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
  12088. #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
  12089. /******************* Bit definition for TSC_IOSCR register ******************/
  12090. #define TSC_IOSCR_G1_IO1_Pos (0U)
  12091. #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
  12092. #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
  12093. #define TSC_IOSCR_G1_IO2_Pos (1U)
  12094. #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
  12095. #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
  12096. #define TSC_IOSCR_G1_IO3_Pos (2U)
  12097. #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
  12098. #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
  12099. #define TSC_IOSCR_G1_IO4_Pos (3U)
  12100. #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
  12101. #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
  12102. #define TSC_IOSCR_G2_IO1_Pos (4U)
  12103. #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
  12104. #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
  12105. #define TSC_IOSCR_G2_IO2_Pos (5U)
  12106. #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
  12107. #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
  12108. #define TSC_IOSCR_G2_IO3_Pos (6U)
  12109. #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
  12110. #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
  12111. #define TSC_IOSCR_G2_IO4_Pos (7U)
  12112. #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
  12113. #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
  12114. #define TSC_IOSCR_G3_IO1_Pos (8U)
  12115. #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
  12116. #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
  12117. #define TSC_IOSCR_G3_IO2_Pos (9U)
  12118. #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
  12119. #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
  12120. #define TSC_IOSCR_G3_IO3_Pos (10U)
  12121. #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
  12122. #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
  12123. #define TSC_IOSCR_G3_IO4_Pos (11U)
  12124. #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
  12125. #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
  12126. #define TSC_IOSCR_G4_IO1_Pos (12U)
  12127. #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
  12128. #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
  12129. #define TSC_IOSCR_G4_IO2_Pos (13U)
  12130. #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
  12131. #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
  12132. #define TSC_IOSCR_G4_IO3_Pos (14U)
  12133. #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
  12134. #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
  12135. #define TSC_IOSCR_G4_IO4_Pos (15U)
  12136. #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
  12137. #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
  12138. #define TSC_IOSCR_G5_IO1_Pos (16U)
  12139. #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
  12140. #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
  12141. #define TSC_IOSCR_G5_IO2_Pos (17U)
  12142. #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
  12143. #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
  12144. #define TSC_IOSCR_G5_IO3_Pos (18U)
  12145. #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
  12146. #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
  12147. #define TSC_IOSCR_G5_IO4_Pos (19U)
  12148. #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
  12149. #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
  12150. #define TSC_IOSCR_G6_IO1_Pos (20U)
  12151. #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
  12152. #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
  12153. #define TSC_IOSCR_G6_IO2_Pos (21U)
  12154. #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
  12155. #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
  12156. #define TSC_IOSCR_G6_IO3_Pos (22U)
  12157. #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
  12158. #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
  12159. #define TSC_IOSCR_G6_IO4_Pos (23U)
  12160. #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
  12161. #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
  12162. #define TSC_IOSCR_G7_IO1_Pos (24U)
  12163. #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
  12164. #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
  12165. #define TSC_IOSCR_G7_IO2_Pos (25U)
  12166. #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
  12167. #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
  12168. #define TSC_IOSCR_G7_IO3_Pos (26U)
  12169. #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
  12170. #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
  12171. #define TSC_IOSCR_G7_IO4_Pos (27U)
  12172. #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
  12173. #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
  12174. /******************* Bit definition for TSC_IOCCR register ******************/
  12175. #define TSC_IOCCR_G1_IO1_Pos (0U)
  12176. #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
  12177. #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
  12178. #define TSC_IOCCR_G1_IO2_Pos (1U)
  12179. #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
  12180. #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
  12181. #define TSC_IOCCR_G1_IO3_Pos (2U)
  12182. #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
  12183. #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
  12184. #define TSC_IOCCR_G1_IO4_Pos (3U)
  12185. #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
  12186. #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
  12187. #define TSC_IOCCR_G2_IO1_Pos (4U)
  12188. #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
  12189. #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
  12190. #define TSC_IOCCR_G2_IO2_Pos (5U)
  12191. #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
  12192. #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
  12193. #define TSC_IOCCR_G2_IO3_Pos (6U)
  12194. #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
  12195. #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
  12196. #define TSC_IOCCR_G2_IO4_Pos (7U)
  12197. #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
  12198. #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
  12199. #define TSC_IOCCR_G3_IO1_Pos (8U)
  12200. #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
  12201. #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
  12202. #define TSC_IOCCR_G3_IO2_Pos (9U)
  12203. #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
  12204. #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
  12205. #define TSC_IOCCR_G3_IO3_Pos (10U)
  12206. #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
  12207. #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
  12208. #define TSC_IOCCR_G3_IO4_Pos (11U)
  12209. #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
  12210. #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
  12211. #define TSC_IOCCR_G4_IO1_Pos (12U)
  12212. #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
  12213. #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
  12214. #define TSC_IOCCR_G4_IO2_Pos (13U)
  12215. #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
  12216. #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
  12217. #define TSC_IOCCR_G4_IO3_Pos (14U)
  12218. #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
  12219. #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
  12220. #define TSC_IOCCR_G4_IO4_Pos (15U)
  12221. #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
  12222. #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
  12223. #define TSC_IOCCR_G5_IO1_Pos (16U)
  12224. #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
  12225. #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
  12226. #define TSC_IOCCR_G5_IO2_Pos (17U)
  12227. #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
  12228. #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
  12229. #define TSC_IOCCR_G5_IO3_Pos (18U)
  12230. #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
  12231. #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
  12232. #define TSC_IOCCR_G5_IO4_Pos (19U)
  12233. #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
  12234. #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
  12235. #define TSC_IOCCR_G6_IO1_Pos (20U)
  12236. #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
  12237. #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
  12238. #define TSC_IOCCR_G6_IO2_Pos (21U)
  12239. #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
  12240. #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
  12241. #define TSC_IOCCR_G6_IO3_Pos (22U)
  12242. #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
  12243. #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
  12244. #define TSC_IOCCR_G6_IO4_Pos (23U)
  12245. #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
  12246. #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
  12247. #define TSC_IOCCR_G7_IO1_Pos (24U)
  12248. #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
  12249. #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
  12250. #define TSC_IOCCR_G7_IO2_Pos (25U)
  12251. #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
  12252. #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
  12253. #define TSC_IOCCR_G7_IO3_Pos (26U)
  12254. #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
  12255. #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
  12256. #define TSC_IOCCR_G7_IO4_Pos (27U)
  12257. #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
  12258. #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
  12259. /******************* Bit definition for TSC_IOGCSR register *****************/
  12260. #define TSC_IOGCSR_G1E_Pos (0U)
  12261. #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
  12262. #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
  12263. #define TSC_IOGCSR_G2E_Pos (1U)
  12264. #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
  12265. #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
  12266. #define TSC_IOGCSR_G3E_Pos (2U)
  12267. #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
  12268. #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
  12269. #define TSC_IOGCSR_G4E_Pos (3U)
  12270. #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
  12271. #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
  12272. #define TSC_IOGCSR_G5E_Pos (4U)
  12273. #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
  12274. #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
  12275. #define TSC_IOGCSR_G6E_Pos (5U)
  12276. #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
  12277. #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
  12278. #define TSC_IOGCSR_G7E_Pos (6U)
  12279. #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
  12280. #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
  12281. #define TSC_IOGCSR_G1S_Pos (16U)
  12282. #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
  12283. #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
  12284. #define TSC_IOGCSR_G2S_Pos (17U)
  12285. #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
  12286. #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
  12287. #define TSC_IOGCSR_G3S_Pos (18U)
  12288. #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
  12289. #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
  12290. #define TSC_IOGCSR_G4S_Pos (19U)
  12291. #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
  12292. #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
  12293. #define TSC_IOGCSR_G5S_Pos (20U)
  12294. #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
  12295. #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
  12296. #define TSC_IOGCSR_G6S_Pos (21U)
  12297. #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
  12298. #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
  12299. #define TSC_IOGCSR_G7S_Pos (22U)
  12300. #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
  12301. #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
  12302. /******************* Bit definition for TSC_IOGXCR register *****************/
  12303. #define TSC_IOGXCR_CNT_Pos (0U)
  12304. #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
  12305. #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
  12306. /******************************************************************************/
  12307. /* */
  12308. /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
  12309. /* */
  12310. /******************************************************************************/
  12311. /*
  12312. * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
  12313. */
  12314. #define USART_TCBGT_SUPPORT
  12315. /****************** Bit definition for USART_CR1 register *******************/
  12316. #define USART_CR1_UE_Pos (0U)
  12317. #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
  12318. #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
  12319. #define USART_CR1_UESM_Pos (1U)
  12320. #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
  12321. #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
  12322. #define USART_CR1_RE_Pos (2U)
  12323. #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
  12324. #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
  12325. #define USART_CR1_TE_Pos (3U)
  12326. #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
  12327. #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
  12328. #define USART_CR1_IDLEIE_Pos (4U)
  12329. #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
  12330. #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
  12331. #define USART_CR1_RXNEIE_Pos (5U)
  12332. #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
  12333. #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
  12334. #define USART_CR1_TCIE_Pos (6U)
  12335. #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
  12336. #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
  12337. #define USART_CR1_TXEIE_Pos (7U)
  12338. #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
  12339. #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
  12340. #define USART_CR1_PEIE_Pos (8U)
  12341. #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
  12342. #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
  12343. #define USART_CR1_PS_Pos (9U)
  12344. #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
  12345. #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
  12346. #define USART_CR1_PCE_Pos (10U)
  12347. #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
  12348. #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
  12349. #define USART_CR1_WAKE_Pos (11U)
  12350. #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
  12351. #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
  12352. #define USART_CR1_M_Pos (12U)
  12353. #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
  12354. #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
  12355. #define USART_CR1_M0_Pos (12U)
  12356. #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
  12357. #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
  12358. #define USART_CR1_MME_Pos (13U)
  12359. #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
  12360. #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
  12361. #define USART_CR1_CMIE_Pos (14U)
  12362. #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
  12363. #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
  12364. #define USART_CR1_OVER8_Pos (15U)
  12365. #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
  12366. #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
  12367. #define USART_CR1_DEDT_Pos (16U)
  12368. #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
  12369. #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
  12370. #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
  12371. #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
  12372. #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
  12373. #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
  12374. #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
  12375. #define USART_CR1_DEAT_Pos (21U)
  12376. #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
  12377. #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
  12378. #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
  12379. #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
  12380. #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
  12381. #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
  12382. #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
  12383. #define USART_CR1_RTOIE_Pos (26U)
  12384. #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
  12385. #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
  12386. #define USART_CR1_EOBIE_Pos (27U)
  12387. #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
  12388. #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
  12389. #define USART_CR1_M1_Pos (28U)
  12390. #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
  12391. #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
  12392. /****************** Bit definition for USART_CR2 register *******************/
  12393. #define USART_CR2_ADDM7_Pos (4U)
  12394. #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
  12395. #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
  12396. #define USART_CR2_LBDL_Pos (5U)
  12397. #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
  12398. #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
  12399. #define USART_CR2_LBDIE_Pos (6U)
  12400. #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
  12401. #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
  12402. #define USART_CR2_LBCL_Pos (8U)
  12403. #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
  12404. #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
  12405. #define USART_CR2_CPHA_Pos (9U)
  12406. #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
  12407. #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
  12408. #define USART_CR2_CPOL_Pos (10U)
  12409. #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
  12410. #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
  12411. #define USART_CR2_CLKEN_Pos (11U)
  12412. #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
  12413. #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
  12414. #define USART_CR2_STOP_Pos (12U)
  12415. #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
  12416. #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
  12417. #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
  12418. #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
  12419. #define USART_CR2_LINEN_Pos (14U)
  12420. #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
  12421. #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
  12422. #define USART_CR2_SWAP_Pos (15U)
  12423. #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
  12424. #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
  12425. #define USART_CR2_RXINV_Pos (16U)
  12426. #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
  12427. #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
  12428. #define USART_CR2_TXINV_Pos (17U)
  12429. #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
  12430. #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
  12431. #define USART_CR2_DATAINV_Pos (18U)
  12432. #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
  12433. #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
  12434. #define USART_CR2_MSBFIRST_Pos (19U)
  12435. #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
  12436. #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
  12437. #define USART_CR2_ABREN_Pos (20U)
  12438. #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
  12439. #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
  12440. #define USART_CR2_ABRMODE_Pos (21U)
  12441. #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
  12442. #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
  12443. #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
  12444. #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
  12445. #define USART_CR2_RTOEN_Pos (23U)
  12446. #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
  12447. #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
  12448. #define USART_CR2_ADD_Pos (24U)
  12449. #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
  12450. #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
  12451. /****************** Bit definition for USART_CR3 register *******************/
  12452. #define USART_CR3_EIE_Pos (0U)
  12453. #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
  12454. #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
  12455. #define USART_CR3_IREN_Pos (1U)
  12456. #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
  12457. #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
  12458. #define USART_CR3_IRLP_Pos (2U)
  12459. #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
  12460. #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
  12461. #define USART_CR3_HDSEL_Pos (3U)
  12462. #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
  12463. #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
  12464. #define USART_CR3_NACK_Pos (4U)
  12465. #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
  12466. #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
  12467. #define USART_CR3_SCEN_Pos (5U)
  12468. #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
  12469. #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
  12470. #define USART_CR3_DMAR_Pos (6U)
  12471. #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
  12472. #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
  12473. #define USART_CR3_DMAT_Pos (7U)
  12474. #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
  12475. #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
  12476. #define USART_CR3_RTSE_Pos (8U)
  12477. #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
  12478. #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
  12479. #define USART_CR3_CTSE_Pos (9U)
  12480. #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
  12481. #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
  12482. #define USART_CR3_CTSIE_Pos (10U)
  12483. #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
  12484. #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
  12485. #define USART_CR3_ONEBIT_Pos (11U)
  12486. #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
  12487. #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
  12488. #define USART_CR3_OVRDIS_Pos (12U)
  12489. #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
  12490. #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
  12491. #define USART_CR3_DDRE_Pos (13U)
  12492. #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
  12493. #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
  12494. #define USART_CR3_DEM_Pos (14U)
  12495. #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
  12496. #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
  12497. #define USART_CR3_DEP_Pos (15U)
  12498. #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
  12499. #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
  12500. #define USART_CR3_SCARCNT_Pos (17U)
  12501. #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
  12502. #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
  12503. #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
  12504. #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
  12505. #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
  12506. #define USART_CR3_WUS_Pos (20U)
  12507. #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
  12508. #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
  12509. #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
  12510. #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
  12511. #define USART_CR3_WUFIE_Pos (22U)
  12512. #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
  12513. #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
  12514. #define USART_CR3_TCBGTIE_Pos (24U)
  12515. #define USART_CR3_TCBGTIE_Msk (0x1U << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
  12516. #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
  12517. /****************** Bit definition for USART_BRR register *******************/
  12518. #define USART_BRR_DIV_FRACTION_Pos (0U)
  12519. #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
  12520. #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
  12521. #define USART_BRR_DIV_MANTISSA_Pos (4U)
  12522. #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
  12523. #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
  12524. /****************** Bit definition for USART_GTPR register ******************/
  12525. #define USART_GTPR_PSC_Pos (0U)
  12526. #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
  12527. #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
  12528. #define USART_GTPR_GT_Pos (8U)
  12529. #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
  12530. #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
  12531. /******************* Bit definition for USART_RTOR register *****************/
  12532. #define USART_RTOR_RTO_Pos (0U)
  12533. #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
  12534. #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
  12535. #define USART_RTOR_BLEN_Pos (24U)
  12536. #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
  12537. #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
  12538. /******************* Bit definition for USART_RQR register ******************/
  12539. #define USART_RQR_ABRRQ_Pos (0U)
  12540. #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
  12541. #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
  12542. #define USART_RQR_SBKRQ_Pos (1U)
  12543. #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
  12544. #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
  12545. #define USART_RQR_MMRQ_Pos (2U)
  12546. #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
  12547. #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
  12548. #define USART_RQR_RXFRQ_Pos (3U)
  12549. #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
  12550. #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
  12551. #define USART_RQR_TXFRQ_Pos (4U)
  12552. #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
  12553. #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
  12554. /******************* Bit definition for USART_ISR register ******************/
  12555. #define USART_ISR_PE_Pos (0U)
  12556. #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
  12557. #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
  12558. #define USART_ISR_FE_Pos (1U)
  12559. #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
  12560. #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
  12561. #define USART_ISR_NE_Pos (2U)
  12562. #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
  12563. #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
  12564. #define USART_ISR_ORE_Pos (3U)
  12565. #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
  12566. #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
  12567. #define USART_ISR_IDLE_Pos (4U)
  12568. #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
  12569. #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
  12570. #define USART_ISR_RXNE_Pos (5U)
  12571. #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
  12572. #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
  12573. #define USART_ISR_TC_Pos (6U)
  12574. #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
  12575. #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
  12576. #define USART_ISR_TXE_Pos (7U)
  12577. #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
  12578. #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
  12579. #define USART_ISR_LBDF_Pos (8U)
  12580. #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
  12581. #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
  12582. #define USART_ISR_CTSIF_Pos (9U)
  12583. #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
  12584. #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
  12585. #define USART_ISR_CTS_Pos (10U)
  12586. #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
  12587. #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
  12588. #define USART_ISR_RTOF_Pos (11U)
  12589. #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
  12590. #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
  12591. #define USART_ISR_EOBF_Pos (12U)
  12592. #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
  12593. #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
  12594. #define USART_ISR_ABRE_Pos (14U)
  12595. #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
  12596. #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
  12597. #define USART_ISR_ABRF_Pos (15U)
  12598. #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
  12599. #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
  12600. #define USART_ISR_BUSY_Pos (16U)
  12601. #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
  12602. #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
  12603. #define USART_ISR_CMF_Pos (17U)
  12604. #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
  12605. #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
  12606. #define USART_ISR_SBKF_Pos (18U)
  12607. #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
  12608. #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
  12609. #define USART_ISR_RWU_Pos (19U)
  12610. #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
  12611. #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
  12612. #define USART_ISR_WUF_Pos (20U)
  12613. #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
  12614. #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
  12615. #define USART_ISR_TEACK_Pos (21U)
  12616. #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
  12617. #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
  12618. #define USART_ISR_REACK_Pos (22U)
  12619. #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
  12620. #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
  12621. #define USART_ISR_TCBGT_Pos (25U)
  12622. #define USART_ISR_TCBGT_Msk (0x1U << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
  12623. #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */
  12624. /******************* Bit definition for USART_ICR register ******************/
  12625. #define USART_ICR_PECF_Pos (0U)
  12626. #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
  12627. #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
  12628. #define USART_ICR_FECF_Pos (1U)
  12629. #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
  12630. #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
  12631. #define USART_ICR_NECF_Pos (2U)
  12632. #define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
  12633. #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
  12634. #define USART_ICR_ORECF_Pos (3U)
  12635. #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
  12636. #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
  12637. #define USART_ICR_IDLECF_Pos (4U)
  12638. #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
  12639. #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
  12640. #define USART_ICR_TCCF_Pos (6U)
  12641. #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
  12642. #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
  12643. #define USART_ICR_TCBGTCF_Pos (7U)
  12644. #define USART_ICR_TCBGTCF_Msk (0x1U << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
  12645. #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
  12646. #define USART_ICR_LBDCF_Pos (8U)
  12647. #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
  12648. #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
  12649. #define USART_ICR_CTSCF_Pos (9U)
  12650. #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
  12651. #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
  12652. #define USART_ICR_RTOCF_Pos (11U)
  12653. #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
  12654. #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
  12655. #define USART_ICR_EOBCF_Pos (12U)
  12656. #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
  12657. #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
  12658. #define USART_ICR_CMCF_Pos (17U)
  12659. #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
  12660. #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
  12661. #define USART_ICR_WUCF_Pos (20U)
  12662. #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
  12663. #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
  12664. /* Legacy defines */
  12665. #define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
  12666. #define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
  12667. #define USART_ICR_NCF USART_ICR_NECF
  12668. /******************* Bit definition for USART_RDR register ******************/
  12669. #define USART_RDR_RDR_Pos (0U)
  12670. #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
  12671. #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
  12672. /******************* Bit definition for USART_TDR register ******************/
  12673. #define USART_TDR_TDR_Pos (0U)
  12674. #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
  12675. #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
  12676. /******************************************************************************/
  12677. /* */
  12678. /* Single Wire Protocol Master Interface (SWPMI) */
  12679. /* */
  12680. /******************************************************************************/
  12681. /******************* Bit definition for SWPMI_CR register ********************/
  12682. #define SWPMI_CR_RXDMA_Pos (0U)
  12683. #define SWPMI_CR_RXDMA_Msk (0x1U << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
  12684. #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
  12685. #define SWPMI_CR_TXDMA_Pos (1U)
  12686. #define SWPMI_CR_TXDMA_Msk (0x1U << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
  12687. #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
  12688. #define SWPMI_CR_RXMODE_Pos (2U)
  12689. #define SWPMI_CR_RXMODE_Msk (0x1U << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
  12690. #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
  12691. #define SWPMI_CR_TXMODE_Pos (3U)
  12692. #define SWPMI_CR_TXMODE_Msk (0x1U << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
  12693. #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
  12694. #define SWPMI_CR_LPBK_Pos (4U)
  12695. #define SWPMI_CR_LPBK_Msk (0x1U << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
  12696. #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
  12697. #define SWPMI_CR_SWPACT_Pos (5U)
  12698. #define SWPMI_CR_SWPACT_Msk (0x1U << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
  12699. #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
  12700. #define SWPMI_CR_DEACT_Pos (10U)
  12701. #define SWPMI_CR_DEACT_Msk (0x1U << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
  12702. #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
  12703. /******************* Bit definition for SWPMI_BRR register ********************/
  12704. #define SWPMI_BRR_BR_Pos (0U)
  12705. #define SWPMI_BRR_BR_Msk (0x3FU << SWPMI_BRR_BR_Pos) /*!< 0x0000003F */
  12706. #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[5:0] bits (Bitrate prescaler) */
  12707. /******************* Bit definition for SWPMI_ISR register ********************/
  12708. #define SWPMI_ISR_RXBFF_Pos (0U)
  12709. #define SWPMI_ISR_RXBFF_Msk (0x1U << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
  12710. #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
  12711. #define SWPMI_ISR_TXBEF_Pos (1U)
  12712. #define SWPMI_ISR_TXBEF_Msk (0x1U << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
  12713. #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
  12714. #define SWPMI_ISR_RXBERF_Pos (2U)
  12715. #define SWPMI_ISR_RXBERF_Msk (0x1U << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
  12716. #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
  12717. #define SWPMI_ISR_RXOVRF_Pos (3U)
  12718. #define SWPMI_ISR_RXOVRF_Msk (0x1U << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
  12719. #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
  12720. #define SWPMI_ISR_TXUNRF_Pos (4U)
  12721. #define SWPMI_ISR_TXUNRF_Msk (0x1U << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
  12722. #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
  12723. #define SWPMI_ISR_RXNE_Pos (5U)
  12724. #define SWPMI_ISR_RXNE_Msk (0x1U << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
  12725. #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
  12726. #define SWPMI_ISR_TXE_Pos (6U)
  12727. #define SWPMI_ISR_TXE_Msk (0x1U << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
  12728. #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
  12729. #define SWPMI_ISR_TCF_Pos (7U)
  12730. #define SWPMI_ISR_TCF_Msk (0x1U << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
  12731. #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
  12732. #define SWPMI_ISR_SRF_Pos (8U)
  12733. #define SWPMI_ISR_SRF_Msk (0x1U << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
  12734. #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
  12735. #define SWPMI_ISR_SUSP_Pos (9U)
  12736. #define SWPMI_ISR_SUSP_Msk (0x1U << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
  12737. #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
  12738. #define SWPMI_ISR_DEACTF_Pos (10U)
  12739. #define SWPMI_ISR_DEACTF_Msk (0x1U << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
  12740. #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
  12741. /******************* Bit definition for SWPMI_ICR register ********************/
  12742. #define SWPMI_ICR_CRXBFF_Pos (0U)
  12743. #define SWPMI_ICR_CRXBFF_Msk (0x1U << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
  12744. #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
  12745. #define SWPMI_ICR_CTXBEF_Pos (1U)
  12746. #define SWPMI_ICR_CTXBEF_Msk (0x1U << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
  12747. #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
  12748. #define SWPMI_ICR_CRXBERF_Pos (2U)
  12749. #define SWPMI_ICR_CRXBERF_Msk (0x1U << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
  12750. #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
  12751. #define SWPMI_ICR_CRXOVRF_Pos (3U)
  12752. #define SWPMI_ICR_CRXOVRF_Msk (0x1U << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
  12753. #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
  12754. #define SWPMI_ICR_CTXUNRF_Pos (4U)
  12755. #define SWPMI_ICR_CTXUNRF_Msk (0x1U << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
  12756. #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
  12757. #define SWPMI_ICR_CTCF_Pos (7U)
  12758. #define SWPMI_ICR_CTCF_Msk (0x1U << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
  12759. #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
  12760. #define SWPMI_ICR_CSRF_Pos (8U)
  12761. #define SWPMI_ICR_CSRF_Msk (0x1U << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
  12762. #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
  12763. /******************* Bit definition for SWPMI_IER register ********************/
  12764. #define SWPMI_IER_SRIE_Pos (8U)
  12765. #define SWPMI_IER_SRIE_Msk (0x1U << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
  12766. #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
  12767. #define SWPMI_IER_TCIE_Pos (7U)
  12768. #define SWPMI_IER_TCIE_Msk (0x1U << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
  12769. #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
  12770. #define SWPMI_IER_TIE_Pos (6U)
  12771. #define SWPMI_IER_TIE_Msk (0x1U << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
  12772. #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
  12773. #define SWPMI_IER_RIE_Pos (5U)
  12774. #define SWPMI_IER_RIE_Msk (0x1U << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
  12775. #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
  12776. #define SWPMI_IER_TXUNRIE_Pos (4U)
  12777. #define SWPMI_IER_TXUNRIE_Msk (0x1U << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
  12778. #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
  12779. #define SWPMI_IER_RXOVRIE_Pos (3U)
  12780. #define SWPMI_IER_RXOVRIE_Msk (0x1U << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
  12781. #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
  12782. #define SWPMI_IER_RXBERIE_Pos (2U)
  12783. #define SWPMI_IER_RXBERIE_Msk (0x1U << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
  12784. #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
  12785. #define SWPMI_IER_TXBEIE_Pos (1U)
  12786. #define SWPMI_IER_TXBEIE_Msk (0x1U << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
  12787. #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
  12788. #define SWPMI_IER_RXBFIE_Pos (0U)
  12789. #define SWPMI_IER_RXBFIE_Msk (0x1U << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
  12790. #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
  12791. /******************* Bit definition for SWPMI_RFL register ********************/
  12792. #define SWPMI_RFL_RFL_Pos (0U)
  12793. #define SWPMI_RFL_RFL_Msk (0x1FU << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
  12794. #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
  12795. #define SWPMI_RFL_RFL_0_1_Pos (0U)
  12796. #define SWPMI_RFL_RFL_0_1_Msk (0x3U << SWPMI_RFL_RFL_0_1_Pos) /*!< 0x00000003 */
  12797. #define SWPMI_RFL_RFL_0_1 SWPMI_RFL_RFL_0_1_Msk /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
  12798. /******************* Bit definition for SWPMI_TDR register ********************/
  12799. #define SWPMI_TDR_TD_Pos (0U)
  12800. #define SWPMI_TDR_TD_Msk (0xFFFFFFFFU << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
  12801. #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
  12802. /******************* Bit definition for SWPMI_RDR register ********************/
  12803. #define SWPMI_RDR_RD_Pos (0U)
  12804. #define SWPMI_RDR_RD_Msk (0xFFFFFFFFU << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
  12805. #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
  12806. /******************* Bit definition for SWPMI_OR register ********************/
  12807. #define SWPMI_OR_TBYP_Pos (0U)
  12808. #define SWPMI_OR_TBYP_Msk (0x1U << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
  12809. #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
  12810. #define SWPMI_OR_CLASS_Pos (1U)
  12811. #define SWPMI_OR_CLASS_Msk (0x1U << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
  12812. #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP Voltage Class selection */
  12813. /******************************************************************************/
  12814. /* */
  12815. /* Window WATCHDOG */
  12816. /* */
  12817. /******************************************************************************/
  12818. /******************* Bit definition for WWDG_CR register ********************/
  12819. #define WWDG_CR_T_Pos (0U)
  12820. #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
  12821. #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
  12822. #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
  12823. #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
  12824. #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
  12825. #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
  12826. #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
  12827. #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
  12828. #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
  12829. #define WWDG_CR_WDGA_Pos (7U)
  12830. #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
  12831. #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
  12832. /******************* Bit definition for WWDG_CFR register *******************/
  12833. #define WWDG_CFR_W_Pos (0U)
  12834. #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
  12835. #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
  12836. #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
  12837. #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
  12838. #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
  12839. #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
  12840. #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
  12841. #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
  12842. #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
  12843. #define WWDG_CFR_WDGTB_Pos (7U)
  12844. #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
  12845. #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
  12846. #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
  12847. #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
  12848. #define WWDG_CFR_EWI_Pos (9U)
  12849. #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
  12850. #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
  12851. /******************* Bit definition for WWDG_SR register ********************/
  12852. #define WWDG_SR_EWIF_Pos (0U)
  12853. #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
  12854. #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
  12855. /******************************************************************************/
  12856. /* */
  12857. /* Debug MCU */
  12858. /* */
  12859. /******************************************************************************/
  12860. /******************** Bit definition for DBGMCU_IDCODE register *************/
  12861. #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
  12862. #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
  12863. #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
  12864. #define DBGMCU_IDCODE_REV_ID_Pos (16U)
  12865. #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
  12866. #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
  12867. /******************** Bit definition for DBGMCU_CR register *****************/
  12868. #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
  12869. #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
  12870. #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
  12871. #define DBGMCU_CR_DBG_STOP_Pos (1U)
  12872. #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
  12873. #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
  12874. #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
  12875. #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
  12876. #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
  12877. #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
  12878. #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
  12879. #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
  12880. #define DBGMCU_CR_TRACE_MODE_Pos (6U)
  12881. #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
  12882. #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
  12883. #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
  12884. #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
  12885. /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
  12886. #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
  12887. #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
  12888. #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
  12889. #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
  12890. #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
  12891. #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
  12892. #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
  12893. #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
  12894. #define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
  12895. #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
  12896. #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
  12897. #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
  12898. #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
  12899. #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
  12900. #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
  12901. #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
  12902. #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
  12903. #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
  12904. #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
  12905. #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
  12906. #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
  12907. #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
  12908. #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
  12909. #define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
  12910. #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
  12911. #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
  12912. #define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
  12913. #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
  12914. #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
  12915. #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
  12916. /******************** Bit definition for DBGMCU_APB1FZR2 register **********/
  12917. #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
  12918. #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
  12919. #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
  12920. /******************** Bit definition for DBGMCU_APB2FZ register ************/
  12921. #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
  12922. #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
  12923. #define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
  12924. #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
  12925. #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
  12926. #define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
  12927. #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
  12928. #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
  12929. #define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
  12930. /******************************************************************************/
  12931. /* */
  12932. /* USB Device FS Endpoint registers */
  12933. /* */
  12934. /******************************************************************************/
  12935. #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
  12936. #define USB_EP1R (USB_BASE + 0x00000004) /*!< endpoint 1 register address */
  12937. #define USB_EP2R (USB_BASE + 0x00000008) /*!< endpoint 2 register address */
  12938. #define USB_EP3R (USB_BASE + 0x0000000C) /*!< endpoint 3 register address */
  12939. #define USB_EP4R (USB_BASE + 0x00000010) /*!< endpoint 4 register address */
  12940. #define USB_EP5R (USB_BASE + 0x00000014) /*!< endpoint 5 register address */
  12941. #define USB_EP6R (USB_BASE + 0x00000018) /*!< endpoint 6 register address */
  12942. #define USB_EP7R (USB_BASE + 0x0000001C) /*!< endpoint 7 register address */
  12943. /* bit positions */
  12944. #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
  12945. #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
  12946. #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
  12947. #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
  12948. #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
  12949. #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
  12950. #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
  12951. #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
  12952. #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
  12953. #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
  12954. /* EndPoint REGister MASK (no toggle fields) */
  12955. #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
  12956. /*!< EP_TYPE[1:0] EndPoint TYPE */
  12957. #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
  12958. #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
  12959. #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
  12960. #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
  12961. #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
  12962. #define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
  12963. #define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
  12964. /*!< STAT_TX[1:0] STATus for TX transfer */
  12965. #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
  12966. #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
  12967. #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
  12968. #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
  12969. #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
  12970. #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
  12971. #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
  12972. /*!< STAT_RX[1:0] STATus for RX transfer */
  12973. #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
  12974. #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
  12975. #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
  12976. #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
  12977. #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
  12978. #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
  12979. #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
  12980. /******************************************************************************/
  12981. /* */
  12982. /* USB Device FS General registers */
  12983. /* */
  12984. /******************************************************************************/
  12985. #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
  12986. #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
  12987. #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
  12988. #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
  12989. #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
  12990. #define USB_LPMCSR (USB_BASE + 0x00000054U) /*!< LPM Control and Status register */
  12991. #define USB_BCDR (USB_BASE + 0x00000058U) /*!< Battery Charging detector register*/
  12992. /****************** Bits definition for USB_CNTR register *******************/
  12993. #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
  12994. #define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
  12995. #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
  12996. #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
  12997. #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
  12998. #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
  12999. #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
  13000. #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
  13001. #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
  13002. #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
  13003. #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
  13004. #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
  13005. #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
  13006. #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
  13007. #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
  13008. /****************** Bits definition for USB_ISTR register *******************/
  13009. #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
  13010. #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
  13011. #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
  13012. #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
  13013. #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
  13014. #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
  13015. #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
  13016. #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
  13017. #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
  13018. #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
  13019. #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
  13020. #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
  13021. #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
  13022. #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
  13023. #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
  13024. #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
  13025. #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
  13026. #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
  13027. #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
  13028. #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
  13029. /****************** Bits definition for USB_FNR register ********************/
  13030. #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
  13031. #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
  13032. #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
  13033. #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
  13034. #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
  13035. /****************** Bits definition for USB_DADDR register ****************/
  13036. #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */
  13037. #define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */
  13038. #define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */
  13039. #define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */
  13040. #define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */
  13041. #define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */
  13042. #define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */
  13043. #define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */
  13044. #define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */
  13045. /****************** Bit definition for USB_BTABLE register ******************/
  13046. #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */
  13047. /****************** Bits definition for USB_BCDR register *******************/
  13048. #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
  13049. #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
  13050. #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
  13051. #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
  13052. #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
  13053. #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
  13054. #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
  13055. #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
  13056. #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
  13057. /******************* Bit definition for LPMCSR register *********************/
  13058. #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
  13059. #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
  13060. #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
  13061. #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
  13062. /*!< Buffer descriptor table */
  13063. /***************** Bit definition for USB_ADDR0_TX register *****************/
  13064. #define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
  13065. #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
  13066. #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
  13067. /***************** Bit definition for USB_ADDR1_TX register *****************/
  13068. #define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
  13069. #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
  13070. #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
  13071. /***************** Bit definition for USB_ADDR2_TX register *****************/
  13072. #define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
  13073. #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
  13074. #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
  13075. /***************** Bit definition for USB_ADDR3_TX register *****************/
  13076. #define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
  13077. #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
  13078. #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
  13079. /***************** Bit definition for USB_ADDR4_TX register *****************/
  13080. #define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
  13081. #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
  13082. #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
  13083. /***************** Bit definition for USB_ADDR5_TX register *****************/
  13084. #define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
  13085. #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
  13086. #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
  13087. /***************** Bit definition for USB_ADDR6_TX register *****************/
  13088. #define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
  13089. #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
  13090. #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
  13091. /***************** Bit definition for USB_ADDR7_TX register *****************/
  13092. #define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
  13093. #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
  13094. #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
  13095. /*----------------------------------------------------------------------------*/
  13096. /***************** Bit definition for USB_COUNT0_TX register ****************/
  13097. #define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
  13098. #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
  13099. #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
  13100. /***************** Bit definition for USB_COUNT1_TX register ****************/
  13101. #define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
  13102. #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
  13103. #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
  13104. /***************** Bit definition for USB_COUNT2_TX register ****************/
  13105. #define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
  13106. #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
  13107. #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
  13108. /***************** Bit definition for USB_COUNT3_TX register ****************/
  13109. #define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
  13110. #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
  13111. #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
  13112. /***************** Bit definition for USB_COUNT4_TX register ****************/
  13113. #define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
  13114. #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
  13115. #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
  13116. /***************** Bit definition for USB_COUNT5_TX register ****************/
  13117. #define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
  13118. #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
  13119. #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
  13120. /***************** Bit definition for USB_COUNT6_TX register ****************/
  13121. #define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
  13122. #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
  13123. #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
  13124. /***************** Bit definition for USB_COUNT7_TX register ****************/
  13125. #define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
  13126. #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
  13127. #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
  13128. /*----------------------------------------------------------------------------*/
  13129. /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
  13130. #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
  13131. /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
  13132. #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
  13133. /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
  13134. #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
  13135. /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
  13136. #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
  13137. /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
  13138. #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
  13139. /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
  13140. #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
  13141. /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
  13142. #define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */
  13143. /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
  13144. #define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */
  13145. /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
  13146. #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
  13147. /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
  13148. #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
  13149. /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
  13150. #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
  13151. /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
  13152. #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
  13153. /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
  13154. #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
  13155. /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
  13156. #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
  13157. /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
  13158. #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
  13159. /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
  13160. #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
  13161. /*----------------------------------------------------------------------------*/
  13162. /***************** Bit definition for USB_ADDR0_RX register *****************/
  13163. #define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
  13164. #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
  13165. #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
  13166. /***************** Bit definition for USB_ADDR1_RX register *****************/
  13167. #define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
  13168. #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
  13169. #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
  13170. /***************** Bit definition for USB_ADDR2_RX register *****************/
  13171. #define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
  13172. #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
  13173. #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
  13174. /***************** Bit definition for USB_ADDR3_RX register *****************/
  13175. #define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
  13176. #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
  13177. #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
  13178. /***************** Bit definition for USB_ADDR4_RX register *****************/
  13179. #define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
  13180. #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
  13181. #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
  13182. /***************** Bit definition for USB_ADDR5_RX register *****************/
  13183. #define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
  13184. #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
  13185. #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
  13186. /***************** Bit definition for USB_ADDR6_RX register *****************/
  13187. #define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
  13188. #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
  13189. #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
  13190. /***************** Bit definition for USB_ADDR7_RX register *****************/
  13191. #define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
  13192. #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
  13193. #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
  13194. /*----------------------------------------------------------------------------*/
  13195. /***************** Bit definition for USB_COUNT0_RX register ****************/
  13196. #define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
  13197. #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
  13198. #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
  13199. #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
  13200. #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  13201. #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  13202. #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  13203. #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  13204. #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  13205. #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  13206. #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  13207. #define USB_COUNT0_RX_BLSIZE_Pos (15U)
  13208. #define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
  13209. #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
  13210. /***************** Bit definition for USB_COUNT1_RX register ****************/
  13211. #define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
  13212. #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
  13213. #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
  13214. #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
  13215. #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  13216. #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  13217. #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  13218. #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  13219. #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  13220. #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  13221. #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  13222. #define USB_COUNT1_RX_BLSIZE_Pos (15U)
  13223. #define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
  13224. #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
  13225. /***************** Bit definition for USB_COUNT2_RX register ****************/
  13226. #define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
  13227. #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
  13228. #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
  13229. #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
  13230. #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  13231. #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  13232. #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  13233. #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  13234. #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  13235. #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  13236. #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  13237. #define USB_COUNT2_RX_BLSIZE_Pos (15U)
  13238. #define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
  13239. #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
  13240. /***************** Bit definition for USB_COUNT3_RX register ****************/
  13241. #define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
  13242. #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
  13243. #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
  13244. #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
  13245. #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  13246. #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  13247. #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  13248. #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  13249. #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  13250. #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  13251. #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  13252. #define USB_COUNT3_RX_BLSIZE_Pos (15U)
  13253. #define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
  13254. #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
  13255. /***************** Bit definition for USB_COUNT4_RX register ****************/
  13256. #define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
  13257. #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
  13258. #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
  13259. #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
  13260. #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  13261. #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  13262. #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  13263. #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  13264. #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  13265. #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  13266. #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  13267. #define USB_COUNT4_RX_BLSIZE_Pos (15U)
  13268. #define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
  13269. #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
  13270. /***************** Bit definition for USB_COUNT5_RX register ****************/
  13271. #define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
  13272. #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
  13273. #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
  13274. #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
  13275. #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  13276. #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  13277. #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  13278. #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  13279. #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  13280. #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  13281. #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  13282. #define USB_COUNT5_RX_BLSIZE_Pos (15U)
  13283. #define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
  13284. #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
  13285. /***************** Bit definition for USB_COUNT6_RX register ****************/
  13286. #define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
  13287. #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
  13288. #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
  13289. #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
  13290. #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  13291. #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  13292. #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  13293. #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  13294. #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  13295. #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  13296. #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  13297. #define USB_COUNT6_RX_BLSIZE_Pos (15U)
  13298. #define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
  13299. #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
  13300. /***************** Bit definition for USB_COUNT7_RX register ****************/
  13301. #define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
  13302. #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
  13303. #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
  13304. #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
  13305. #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  13306. #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  13307. #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  13308. #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  13309. #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  13310. #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  13311. #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  13312. #define USB_COUNT7_RX_BLSIZE_Pos (15U)
  13313. #define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
  13314. #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
  13315. /*----------------------------------------------------------------------------*/
  13316. /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
  13317. #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
  13318. #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  13319. #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
  13320. #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
  13321. #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
  13322. #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
  13323. #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
  13324. #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
  13325. /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
  13326. #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
  13327. #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  13328. #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
  13329. #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
  13330. #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
  13331. #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
  13332. #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
  13333. #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
  13334. /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
  13335. #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
  13336. #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  13337. #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
  13338. #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
  13339. #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
  13340. #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
  13341. #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
  13342. #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
  13343. /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
  13344. #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
  13345. #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  13346. #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
  13347. #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
  13348. #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
  13349. #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
  13350. #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
  13351. #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
  13352. /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
  13353. #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
  13354. #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  13355. #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
  13356. #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
  13357. #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
  13358. #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
  13359. #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
  13360. #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
  13361. /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
  13362. #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
  13363. #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  13364. #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
  13365. #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
  13366. #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
  13367. #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
  13368. #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
  13369. #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
  13370. /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
  13371. #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
  13372. #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  13373. #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
  13374. #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
  13375. #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
  13376. #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
  13377. #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
  13378. #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
  13379. /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
  13380. #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
  13381. #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  13382. #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
  13383. #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
  13384. #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
  13385. #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
  13386. #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
  13387. #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
  13388. /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
  13389. #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
  13390. #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  13391. #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
  13392. #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
  13393. #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
  13394. #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
  13395. #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
  13396. #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
  13397. /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
  13398. #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
  13399. #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  13400. #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
  13401. #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
  13402. #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
  13403. #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
  13404. #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
  13405. #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
  13406. /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
  13407. #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
  13408. #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  13409. #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
  13410. #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
  13411. #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
  13412. #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
  13413. #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
  13414. #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
  13415. /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
  13416. #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
  13417. #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  13418. #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
  13419. #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
  13420. #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
  13421. #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
  13422. #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
  13423. #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
  13424. /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
  13425. #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
  13426. #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  13427. #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
  13428. #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
  13429. #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
  13430. #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
  13431. #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
  13432. #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
  13433. /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
  13434. #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
  13435. #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  13436. #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
  13437. #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
  13438. #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
  13439. #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
  13440. #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
  13441. #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
  13442. /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
  13443. #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
  13444. #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  13445. #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
  13446. #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
  13447. #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
  13448. #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
  13449. #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
  13450. #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
  13451. /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
  13452. #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
  13453. #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  13454. #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
  13455. #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
  13456. #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
  13457. #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
  13458. #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
  13459. #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
  13460. /**
  13461. * @}
  13462. */
  13463. /**
  13464. * @}
  13465. */
  13466. /** @addtogroup Exported_macros
  13467. * @{
  13468. */
  13469. /******************************* ADC Instances ********************************/
  13470. #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
  13471. #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
  13472. /******************************** CAN Instances ******************************/
  13473. #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
  13474. /******************************** COMP Instances ******************************/
  13475. #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
  13476. ((INSTANCE) == COMP2))
  13477. #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
  13478. /******************** COMP Instances with window mode capability **************/
  13479. #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
  13480. /******************************* CRC Instances ********************************/
  13481. #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
  13482. /******************************* DAC Instances ********************************/
  13483. #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
  13484. /******************************** DMA Instances *******************************/
  13485. #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
  13486. ((INSTANCE) == DMA1_Channel2) || \
  13487. ((INSTANCE) == DMA1_Channel3) || \
  13488. ((INSTANCE) == DMA1_Channel4) || \
  13489. ((INSTANCE) == DMA1_Channel5) || \
  13490. ((INSTANCE) == DMA1_Channel6) || \
  13491. ((INSTANCE) == DMA1_Channel7) || \
  13492. ((INSTANCE) == DMA2_Channel1) || \
  13493. ((INSTANCE) == DMA2_Channel2) || \
  13494. ((INSTANCE) == DMA2_Channel3) || \
  13495. ((INSTANCE) == DMA2_Channel4) || \
  13496. ((INSTANCE) == DMA2_Channel5) || \
  13497. ((INSTANCE) == DMA2_Channel6) || \
  13498. ((INSTANCE) == DMA2_Channel7))
  13499. /******************************* GPIO Instances *******************************/
  13500. #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
  13501. ((INSTANCE) == GPIOB) || \
  13502. ((INSTANCE) == GPIOC) || \
  13503. ((INSTANCE) == GPIOH))
  13504. /******************************* GPIO AF Instances ****************************/
  13505. /* On L4, all GPIO Bank support AF */
  13506. #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
  13507. /**************************** GPIO Lock Instances *****************************/
  13508. /* On L4, all GPIO Bank support the Lock mechanism */
  13509. #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
  13510. /******************************** I2C Instances *******************************/
  13511. #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
  13512. ((INSTANCE) == I2C3))
  13513. /****************** I2C Instances : wakeup capability from stop modes *********/
  13514. #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
  13515. /****************************** OPAMP Instances *******************************/
  13516. #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
  13517. #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP1_COMMON)
  13518. /******************************* QSPI Instances *******************************/
  13519. #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
  13520. /******************************* RNG Instances ********************************/
  13521. #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
  13522. /****************************** RTC Instances *********************************/
  13523. #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
  13524. /******************************** SAI Instances *******************************/
  13525. #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
  13526. ((INSTANCE) == SAI1_Block_B))
  13527. /****************************** SMBUS Instances *******************************/
  13528. #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
  13529. ((INSTANCE) == I2C3))
  13530. /******************************** SPI Instances *******************************/
  13531. #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
  13532. ((INSTANCE) == SPI3))
  13533. /******************************** SWPMI Instances *****************************/
  13534. #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
  13535. /****************** LPTIM Instances : All supported instances *****************/
  13536. #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
  13537. ((INSTANCE) == LPTIM2))
  13538. /****************** TIM Instances : All supported instances *******************/
  13539. #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13540. ((INSTANCE) == TIM2) || \
  13541. ((INSTANCE) == TIM6) || \
  13542. ((INSTANCE) == TIM7) || \
  13543. ((INSTANCE) == TIM15) || \
  13544. ((INSTANCE) == TIM16))
  13545. /****************** TIM Instances : supporting 32 bits counter ****************/
  13546. #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
  13547. /****************** TIM Instances : supporting the break function *************/
  13548. #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13549. ((INSTANCE) == TIM15) || \
  13550. ((INSTANCE) == TIM16))
  13551. /************** TIM Instances : supporting Break source selection *************/
  13552. #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13553. ((INSTANCE) == TIM15) || \
  13554. ((INSTANCE) == TIM16))
  13555. /****************** TIM Instances : supporting 2 break inputs *****************/
  13556. #define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  13557. /************* TIM Instances : at least 1 capture/compare channel *************/
  13558. #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13559. ((INSTANCE) == TIM2) || \
  13560. ((INSTANCE) == TIM15) || \
  13561. ((INSTANCE) == TIM16))
  13562. /************ TIM Instances : at least 2 capture/compare channels *************/
  13563. #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13564. ((INSTANCE) == TIM2) || \
  13565. ((INSTANCE) == TIM15))
  13566. /************ TIM Instances : at least 3 capture/compare channels *************/
  13567. #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13568. ((INSTANCE) == TIM2))
  13569. /************ TIM Instances : at least 4 capture/compare channels *************/
  13570. #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13571. ((INSTANCE) == TIM2))
  13572. /****************** TIM Instances : at least 5 capture/compare channels *******/
  13573. #define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  13574. /****************** TIM Instances : at least 6 capture/compare channels *******/
  13575. #define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  13576. /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
  13577. #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13578. ((INSTANCE) == TIM15) || \
  13579. ((INSTANCE) == TIM16))
  13580. /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
  13581. #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13582. ((INSTANCE) == TIM2) || \
  13583. ((INSTANCE) == TIM6) || \
  13584. ((INSTANCE) == TIM7) || \
  13585. ((INSTANCE) == TIM15) || \
  13586. ((INSTANCE) == TIM16))
  13587. /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
  13588. #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13589. ((INSTANCE) == TIM2) || \
  13590. ((INSTANCE) == TIM15) || \
  13591. ((INSTANCE) == TIM16))
  13592. /******************** TIM Instances : DMA burst feature ***********************/
  13593. #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13594. ((INSTANCE) == TIM2) || \
  13595. ((INSTANCE) == TIM15) || \
  13596. ((INSTANCE) == TIM16))
  13597. /******************* TIM Instances : output(s) available **********************/
  13598. #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
  13599. ((((INSTANCE) == TIM1) && \
  13600. (((CHANNEL) == TIM_CHANNEL_1) || \
  13601. ((CHANNEL) == TIM_CHANNEL_2) || \
  13602. ((CHANNEL) == TIM_CHANNEL_3) || \
  13603. ((CHANNEL) == TIM_CHANNEL_4) || \
  13604. ((CHANNEL) == TIM_CHANNEL_5) || \
  13605. ((CHANNEL) == TIM_CHANNEL_6))) \
  13606. || \
  13607. (((INSTANCE) == TIM2) && \
  13608. (((CHANNEL) == TIM_CHANNEL_1) || \
  13609. ((CHANNEL) == TIM_CHANNEL_2) || \
  13610. ((CHANNEL) == TIM_CHANNEL_3) || \
  13611. ((CHANNEL) == TIM_CHANNEL_4))) \
  13612. || \
  13613. (((INSTANCE) == TIM15) && \
  13614. (((CHANNEL) == TIM_CHANNEL_1) || \
  13615. ((CHANNEL) == TIM_CHANNEL_2))) \
  13616. || \
  13617. (((INSTANCE) == TIM16) && \
  13618. (((CHANNEL) == TIM_CHANNEL_1))))
  13619. /****************** TIM Instances : supporting complementary output(s) ********/
  13620. #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
  13621. ((((INSTANCE) == TIM1) && \
  13622. (((CHANNEL) == TIM_CHANNEL_1) || \
  13623. ((CHANNEL) == TIM_CHANNEL_2) || \
  13624. ((CHANNEL) == TIM_CHANNEL_3))) \
  13625. || \
  13626. (((INSTANCE) == TIM15) && \
  13627. ((CHANNEL) == TIM_CHANNEL_1)) \
  13628. || \
  13629. (((INSTANCE) == TIM16) && \
  13630. ((CHANNEL) == TIM_CHANNEL_1)))
  13631. /****************** TIM Instances : supporting clock division *****************/
  13632. #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13633. ((INSTANCE) == TIM2) || \
  13634. ((INSTANCE) == TIM15) || \
  13635. ((INSTANCE) == TIM16))
  13636. /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
  13637. #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13638. ((INSTANCE) == TIM2) || \
  13639. ((INSTANCE) == TIM15))
  13640. /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
  13641. #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13642. ((INSTANCE) == TIM2))
  13643. /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
  13644. #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13645. ((INSTANCE) == TIM2) || \
  13646. ((INSTANCE) == TIM15))
  13647. /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
  13648. #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13649. ((INSTANCE) == TIM2) || \
  13650. ((INSTANCE) == TIM15))
  13651. /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
  13652. #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  13653. /****************** TIM Instances : supporting commutation event generation ***/
  13654. #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13655. ((INSTANCE) == TIM15) || \
  13656. ((INSTANCE) == TIM16))
  13657. /****************** TIM Instances : supporting counting mode selection ********/
  13658. #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13659. ((INSTANCE) == TIM2))
  13660. /****************** TIM Instances : supporting encoder interface **************/
  13661. #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13662. ((INSTANCE) == TIM2))
  13663. /****************** TIM Instances : supporting Hall sensor interface **********/
  13664. #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13665. ((INSTANCE) == TIM2))
  13666. /**************** TIM Instances : external trigger input available ************/
  13667. #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13668. ((INSTANCE) == TIM2))
  13669. /************* TIM Instances : supporting ETR source selection ***************/
  13670. #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13671. ((INSTANCE) == TIM2))
  13672. /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
  13673. #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13674. ((INSTANCE) == TIM2) || \
  13675. ((INSTANCE) == TIM6) || \
  13676. ((INSTANCE) == TIM7) || \
  13677. ((INSTANCE) == TIM15))
  13678. /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
  13679. #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13680. ((INSTANCE) == TIM2) || \
  13681. ((INSTANCE) == TIM15))
  13682. /****************** TIM Instances : supporting OCxREF clear *******************/
  13683. #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13684. ((INSTANCE) == TIM2))
  13685. /****************** TIM Instances : remapping capability **********************/
  13686. #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13687. ((INSTANCE) == TIM2) || \
  13688. ((INSTANCE) == TIM15) || \
  13689. ((INSTANCE) == TIM16))
  13690. /****************** TIM Instances : supporting repetition counter *************/
  13691. #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13692. ((INSTANCE) == TIM15) || \
  13693. ((INSTANCE) == TIM16))
  13694. /****************** TIM Instances : supporting synchronization ****************/
  13695. #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
  13696. /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
  13697. #define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  13698. /******************* TIM Instances : Timer input XOR function *****************/
  13699. #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  13700. ((INSTANCE) == TIM2) || \
  13701. ((INSTANCE) == TIM15))
  13702. /****************** TIM Instances : Advanced timer instances *******************/
  13703. #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  13704. /****************************** TSC Instances *********************************/
  13705. #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
  13706. /******************** USART Instances : Synchronous mode **********************/
  13707. #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  13708. ((INSTANCE) == USART2))
  13709. /******************** UART Instances : Asynchronous mode **********************/
  13710. #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  13711. ((INSTANCE) == USART2))
  13712. /****************** UART Instances : Auto Baud Rate detection ****************/
  13713. #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  13714. ((INSTANCE) == USART2))
  13715. /****************** UART Instances : Driver Enable *****************/
  13716. #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  13717. ((INSTANCE) == USART2) || \
  13718. ((INSTANCE) == LPUART1))
  13719. /******************** UART Instances : Half-Duplex mode **********************/
  13720. #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  13721. ((INSTANCE) == USART2) || \
  13722. ((INSTANCE) == LPUART1))
  13723. /****************** UART Instances : Hardware Flow control ********************/
  13724. #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  13725. ((INSTANCE) == USART2) || \
  13726. ((INSTANCE) == LPUART1))
  13727. /******************** UART Instances : LIN mode **********************/
  13728. #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  13729. ((INSTANCE) == USART2))
  13730. /******************** UART Instances : Wake-up from Stop mode **********************/
  13731. #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  13732. ((INSTANCE) == USART2) || \
  13733. ((INSTANCE) == LPUART1))
  13734. /*********************** UART Instances : IRDA mode ***************************/
  13735. #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  13736. ((INSTANCE) == USART2))
  13737. /********************* USART Instances : Smard card mode ***********************/
  13738. #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  13739. ((INSTANCE) == USART2))
  13740. /******************** LPUART Instance *****************************************/
  13741. #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
  13742. /****************************** IWDG Instances ********************************/
  13743. #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
  13744. /****************************** WWDG Instances ********************************/
  13745. #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
  13746. /******************************* USB Instances *******************************/
  13747. #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
  13748. /**
  13749. * @}
  13750. */
  13751. /******************************************************************************/
  13752. /* For a painless codes migration between the STM32L4xx device product */
  13753. /* lines, the aliases defined below are put in place to overcome the */
  13754. /* differences in the interrupt handlers and IRQn definitions. */
  13755. /* No need to update developed interrupt code when moving across */
  13756. /* product lines within the same STM32L4 Family */
  13757. /******************************************************************************/
  13758. /* Aliases for __IRQn */
  13759. #define ADC1_2_IRQn ADC1_IRQn
  13760. #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
  13761. #define HASH_RNG_IRQn RNG_IRQn
  13762. #define HASH_CRS_IRQn CRS_IRQn
  13763. #define USB_FS_IRQn USB_IRQn
  13764. /* Aliases for __IRQHandler */
  13765. #define ADC1_2_IRQHandler ADC1_IRQHandler
  13766. #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
  13767. #define HASH_RNG_IRQHandler RNG_IRQHandler
  13768. #define HASH_CRS_IRQHandler CRS_IRQHandler
  13769. #define USB_FS_IRQHandler USB_IRQHandler
  13770. #ifdef __cplusplus
  13771. }
  13772. #endif /* __cplusplus */
  13773. #endif /* __STM32L432xx_H */
  13774. /**
  13775. * @}
  13776. */
  13777. /**
  13778. * @}
  13779. */
  13780. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/