nixie.rs 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651
  1. use core::ops::DerefMut;
  2. use cortex_m::interrupt::free;
  3. use stm32l4xx_hal::{
  4. prelude::{
  5. _embedded_hal_blocking_i2c_Read, _embedded_hal_blocking_i2c_Write,
  6. _embedded_hal_blocking_i2c_WriteRead,
  7. },
  8. timer::Event,
  9. };
  10. use crate::{ds3231, pca9685};
  11. pub const DS3231_ADDR: u8 = 0x68;
  12. pub const TUSB322_ADDR: u8 = 0x47;
  13. pub const PCA9685_ADDR_1: u8 = 0x41;
  14. pub const PCA9685_ADDR_2: u8 = 0x42;
  15. pub const PCA9685_ADDR_3: u8 = 0x43;
  16. pub const PCA9685_ALL_CALL: u8 = 0x70; // Default enabled
  17. pub const PCA9685_SUB_CALL_1: u8 = 0x71; // Default disabled
  18. pub const PCA9685_SUB_CALL_2: u8 = 0x72; // Default disabled
  19. pub const PCA9685_SUB_CALL_3: u8 = 0x73; // Default disabled
  20. const MAP_DOT_ADDR: u8 = PCA9685_ADDR_2;
  21. const MAP_DOT_PIN: u8 = 15;
  22. const MAP_ADDR: usize = 0;
  23. const MAP_PIN: usize = 1;
  24. const DIGIT_FADE_DURATION_US: u32 = 1_000_000;
  25. pub const REFRESH_RATE_HZ: u32 = 1000;
  26. const DIGIT_RNG_FADE_DURATION_US: u32 = 200_000;
  27. const DIGIT_RNG_FADE_ITERATIONS: usize = 20;
  28. const DIGIT_RNG_REFRESH_INTERVAL: usize = 60;
  29. const DIGIT_RNG_REFRESH_VARIANCE: usize = 30;
  30. const DOT_MIN_BRIGHTNESS: u32 = 256;
  31. const DOT_MAX_BRIGHTNESS: u32 = 640;
  32. const DOT_FADE_DURATION_US: u32 = 1_000_000;
  33. const DIGIT_MAX_BRIGHTNESS: u32 = 4096;
  34. const DIGIT_MIN_BRIGHTNESS: u32 = 0;
  35. const NUM_TUBES: usize = 4;
  36. const NUM_DIGITS: usize = 10;
  37. struct DigitToPin {
  38. address: u8,
  39. pin: usize,
  40. }
  41. struct PwmDriver {
  42. digit: [DigitToPin; 10],
  43. }
  44. struct PwmOutputMap {
  45. driver: [PwmDriver; 4],
  46. dot_address: u8,
  47. dot_pin: usize,
  48. }
  49. static TUBE_MAPPING: PwmOutputMap = {
  50. PwmOutputMap {
  51. driver: [
  52. PwmDriver {
  53. digit: [
  54. DigitToPin {
  55. address: PCA9685_ADDR_1,
  56. pin: 8,
  57. }, // Tube 0 Digit 0
  58. DigitToPin {
  59. address: PCA9685_ADDR_1,
  60. pin: 9,
  61. }, // Tube 0 Digit 1
  62. DigitToPin {
  63. address: PCA9685_ADDR_1,
  64. pin: 10,
  65. }, // Tube 0 Digit 2
  66. DigitToPin {
  67. address: PCA9685_ADDR_1,
  68. pin: 12,
  69. }, // Tube 0 Digit 3
  70. DigitToPin {
  71. address: PCA9685_ADDR_1,
  72. pin: 15,
  73. }, // Tube 0 Digit 4
  74. DigitToPin {
  75. address: PCA9685_ADDR_1,
  76. pin: 14,
  77. }, // Tube 0 Digit 5
  78. DigitToPin {
  79. address: PCA9685_ADDR_1,
  80. pin: 11,
  81. }, // Tube 0 Digit 6
  82. DigitToPin {
  83. address: PCA9685_ADDR_1,
  84. pin: 0,
  85. }, // Tube 0 Digit 7
  86. DigitToPin {
  87. address: PCA9685_ADDR_1,
  88. pin: 1,
  89. }, // Tube 0 Digit 8
  90. DigitToPin {
  91. address: PCA9685_ADDR_1,
  92. pin: 13,
  93. }, // Tube 0 Digit 9
  94. ],
  95. },
  96. PwmDriver {
  97. digit: [
  98. DigitToPin {
  99. address: PCA9685_ADDR_1,
  100. pin: 5,
  101. }, // Tube 1 Digit 0
  102. DigitToPin {
  103. address: PCA9685_ADDR_1,
  104. pin: 6,
  105. }, // Tube 1 Digit 1
  106. DigitToPin {
  107. address: PCA9685_ADDR_1,
  108. pin: 7,
  109. }, // Tube 1 Digit 2
  110. DigitToPin {
  111. address: PCA9685_ADDR_1,
  112. pin: 2,
  113. }, // Tube 1 Digit 3
  114. DigitToPin {
  115. address: PCA9685_ADDR_2,
  116. pin: 4,
  117. }, // Tube 1 Digit 4
  118. DigitToPin {
  119. address: PCA9685_ADDR_2,
  120. pin: 1,
  121. }, // Tube 1 Digit 5
  122. DigitToPin {
  123. address: PCA9685_ADDR_1,
  124. pin: 4,
  125. }, // Tube 1 Digit 6
  126. DigitToPin {
  127. address: PCA9685_ADDR_2,
  128. pin: 2,
  129. }, // Tube 1 Digit 7
  130. DigitToPin {
  131. address: PCA9685_ADDR_2,
  132. pin: 3,
  133. }, // Tube 1 Digit 8
  134. DigitToPin {
  135. address: PCA9685_ADDR_1,
  136. pin: 3,
  137. }, // Tube 1 Digit 9
  138. ],
  139. },
  140. PwmDriver {
  141. digit: [
  142. DigitToPin {
  143. address: PCA9685_ADDR_3,
  144. pin: 8,
  145. }, // Tube 2 Digit 0
  146. DigitToPin {
  147. address: PCA9685_ADDR_3,
  148. pin: 9,
  149. }, // Tube 2 Digit 1
  150. DigitToPin {
  151. address: PCA9685_ADDR_3,
  152. pin: 10,
  153. }, // Tube 2 Digit 2
  154. DigitToPin {
  155. address: PCA9685_ADDR_3,
  156. pin: 12,
  157. }, // Tube 2 Digit 3
  158. DigitToPin {
  159. address: PCA9685_ADDR_2,
  160. pin: 12,
  161. }, // Tube 2 Digit 4
  162. DigitToPin {
  163. address: PCA9685_ADDR_2,
  164. pin: 13,
  165. }, // Tube 2 Digit 5
  166. DigitToPin {
  167. address: PCA9685_ADDR_3,
  168. pin: 11,
  169. }, // Tube 2 Digit 6
  170. DigitToPin {
  171. address: PCA9685_ADDR_2,
  172. pin: 14,
  173. }, // Tube 2 Digit 7
  174. DigitToPin {
  175. address: PCA9685_ADDR_2,
  176. pin: 11,
  177. }, // Tube 2 Digit 8
  178. DigitToPin {
  179. address: PCA9685_ADDR_3,
  180. pin: 13,
  181. }, // Tube 2 Digit 9
  182. ],
  183. },
  184. PwmDriver {
  185. digit: [
  186. DigitToPin {
  187. address: PCA9685_ADDR_3,
  188. pin: 5,
  189. }, // Tube 3 Digit 0
  190. DigitToPin {
  191. address: PCA9685_ADDR_3,
  192. pin: 6,
  193. }, // Tube 3 Digit 1
  194. DigitToPin {
  195. address: PCA9685_ADDR_3,
  196. pin: 7,
  197. }, // Tube 3 Digit 2
  198. DigitToPin {
  199. address: PCA9685_ADDR_3,
  200. pin: 2,
  201. }, // Tube 3 Digit 3
  202. DigitToPin {
  203. address: PCA9685_ADDR_3,
  204. pin: 14,
  205. }, // Tube 3 Digit 4
  206. DigitToPin {
  207. address: PCA9685_ADDR_3,
  208. pin: 15,
  209. }, // Tube 3 Digit 5
  210. DigitToPin {
  211. address: PCA9685_ADDR_3,
  212. pin: 4,
  213. }, // Tube 3 Digit 6
  214. DigitToPin {
  215. address: PCA9685_ADDR_3,
  216. pin: 1,
  217. }, // Tube 3 Digit 7
  218. DigitToPin {
  219. address: PCA9685_ADDR_3,
  220. pin: 0,
  221. }, // Tube 3 Digit 8
  222. DigitToPin {
  223. address: PCA9685_ADDR_3,
  224. pin: 3,
  225. }, // Tube 3 Digit 9
  226. ],
  227. },
  228. ],
  229. dot_address: PCA9685_ADDR_2,
  230. dot_pin: 15,
  231. }
  232. };
  233. #[derive(PartialEq)]
  234. enum DigitState {
  235. Idle,
  236. Incrementing,
  237. Decrementing,
  238. }
  239. struct Digit {
  240. current_state: DigitState,
  241. value: u32,
  242. pwm_start: u32,
  243. pwm_end: u32,
  244. updated: bool,
  245. }
  246. impl Digit {
  247. const fn default() -> Self {
  248. Self {
  249. current_state: DigitState::Idle,
  250. value: 0,
  251. pwm_start: 0,
  252. pwm_end: 0,
  253. updated: false,
  254. }
  255. }
  256. }
  257. struct Tube {
  258. digits: [Digit; NUM_DIGITS],
  259. last_active_digit: Option<usize>,
  260. refresh_last_digit: Option<usize>,
  261. refresh_active: bool,
  262. }
  263. impl Tube {
  264. const fn default() -> Self {
  265. const DIGIT_INIT: Digit = Digit::default();
  266. Self {
  267. digits: [DIGIT_INIT; 10],
  268. last_active_digit: None,
  269. refresh_last_digit: None,
  270. refresh_active: false,
  271. }
  272. }
  273. }
  274. struct Clock {
  275. tubes: [Tube; NUM_TUBES],
  276. dot: Digit,
  277. fade_duration: u32,
  278. }
  279. impl Clock {
  280. const fn default() -> Self {
  281. const TUBE_INIT: Tube = Tube::default();
  282. Self {
  283. tubes: [TUBE_INIT; NUM_TUBES],
  284. dot: Digit::default(),
  285. fade_duration: 0,
  286. }
  287. }
  288. }
  289. static mut CLOCK: Clock = Clock::default();
  290. pub fn fade_in_out_digit(tube: usize, digit: Option<usize>, fade_duration: u32, refresh_cmd: bool) {
  291. // assert!(tube < NUM_TUBES);
  292. // assert!(Some(digit) < NUM_DIGITS);
  293. unsafe {
  294. // If the tube is in the middle of a refresh sequence and a call comes
  295. // in to update the tube digit (for time), override the last value of
  296. // the refresh sequence with the new digit.
  297. if CLOCK.tubes[tube].refresh_active && !refresh_cmd {
  298. CLOCK.tubes[tube].refresh_last_digit = digit;
  299. }
  300. // Dont update if actively refreshing tube unless RngUpdate is set
  301. if (!CLOCK.tubes[tube].refresh_active && !refresh_cmd) || refresh_cmd {
  302. // Fade out all digits
  303. for digit in 0..NUM_DIGITS {
  304. if CLOCK.tubes[tube].digits[digit].value != DIGIT_MIN_BRIGHTNESS {
  305. CLOCK.tubes[tube].digits[digit].current_state = DigitState::Decrementing;
  306. }
  307. }
  308. // Fade in the specified digit
  309. if let Some(digit) = digit {
  310. if CLOCK.tubes[tube].digits[digit].value != DIGIT_MAX_BRIGHTNESS {
  311. CLOCK.tubes[tube].digits[digit].current_state = DigitState::Incrementing;
  312. }
  313. }
  314. CLOCK.tubes[tube].last_active_digit = digit;
  315. CLOCK.fade_duration = fade_duration;
  316. }
  317. }
  318. }
  319. pub fn rtc_tick<T>(i2c: &mut T)
  320. where
  321. T: _embedded_hal_blocking_i2c_WriteRead
  322. + _embedded_hal_blocking_i2c_Read
  323. + _embedded_hal_blocking_i2c_Write,
  324. {
  325. static mut STARTUP: bool = true;
  326. static mut PREV_MINUTE: u32 = 0;
  327. static mut PREV_HOUR: u32 = 0;
  328. let (second, minute, hour) = ds3231::get_time(DS3231_ADDR, i2c);
  329. let (weekday, day, month, _, _) = ds3231::get_date(DS3231_ADDR, i2c);
  330. let hour = if ds3231::in_dst(weekday, day, month, hour) {
  331. (hour + 1) % 12
  332. } else {
  333. hour % 12
  334. };
  335. let hour = if hour == 0 { 12 } else { hour };
  336. unsafe {
  337. if STARTUP || PREV_HOUR / 10 != hour / 10 {
  338. fade_in_out_digit(
  339. 0,
  340. if hour / 10 != 0 {
  341. Some((hour / 10) as usize)
  342. } else {
  343. None
  344. },
  345. DIGIT_FADE_DURATION_US,
  346. false,
  347. )
  348. }
  349. if STARTUP || PREV_HOUR % 10 != hour % 10 {
  350. fade_in_out_digit(1, Some((hour % 10) as usize), DIGIT_FADE_DURATION_US, false);
  351. }
  352. if STARTUP || PREV_MINUTE / 10 != minute / 10 {
  353. fade_in_out_digit(
  354. 2,
  355. Some((minute / 10) as usize),
  356. DIGIT_FADE_DURATION_US,
  357. false,
  358. );
  359. }
  360. if STARTUP || PREV_MINUTE % 10 != minute % 10 {
  361. fade_in_out_digit(
  362. 3,
  363. Some((minute % 10) as usize),
  364. DIGIT_FADE_DURATION_US,
  365. false,
  366. );
  367. }
  368. CLOCK.dot.current_state = match second % 2 {
  369. 0 => DigitState::Incrementing,
  370. 1 => DigitState::Decrementing,
  371. _ => DigitState::Idle,
  372. };
  373. PREV_MINUTE = minute;
  374. PREV_HOUR = hour;
  375. STARTUP = false;
  376. free(|cs| {
  377. let mut timer_ref = super::REFRESH_TIMER.borrow(cs).borrow_mut();
  378. if let Some(ref mut timer) = timer_ref.deref_mut() {
  379. timer.listen(Event::TimeOut);
  380. }
  381. })
  382. }
  383. }
  384. pub fn refresh_tick<T>(i2c: &mut T)
  385. where
  386. T: _embedded_hal_blocking_i2c_WriteRead
  387. + _embedded_hal_blocking_i2c_Read
  388. + _embedded_hal_blocking_i2c_Write,
  389. {
  390. let mut pending_refresh: bool = false;
  391. unsafe {
  392. let ticks = CLOCK.fade_duration / REFRESH_RATE_HZ;
  393. let steps = ((DIGIT_MAX_BRIGHTNESS - DIGIT_MIN_BRIGHTNESS) + ticks - 1) / ticks;
  394. CLOCK.tubes.iter_mut().for_each(|tube| {
  395. tube.digits.iter_mut().for_each(|digit| {
  396. match digit.current_state {
  397. DigitState::Incrementing => {
  398. if digit.value >= DIGIT_MAX_BRIGHTNESS {
  399. digit.value = DIGIT_MAX_BRIGHTNESS;
  400. digit.current_state = DigitState::Idle;
  401. } else {
  402. digit.value = digit
  403. .value
  404. .saturating_add(steps)
  405. .clamp(DIGIT_MIN_BRIGHTNESS, DIGIT_MAX_BRIGHTNESS);
  406. digit.updated = true;
  407. pending_refresh = true;
  408. }
  409. }
  410. DigitState::Decrementing => {
  411. if digit.value <= DIGIT_MIN_BRIGHTNESS {
  412. digit.value = DIGIT_MIN_BRIGHTNESS;
  413. digit.current_state = DigitState::Idle;
  414. } else {
  415. digit.value = digit
  416. .value
  417. .saturating_sub(steps)
  418. .clamp(DIGIT_MIN_BRIGHTNESS, DIGIT_MAX_BRIGHTNESS);
  419. digit.updated = true;
  420. pending_refresh = true;
  421. }
  422. }
  423. DigitState::Idle => (),
  424. };
  425. });
  426. });
  427. // Handle dot
  428. let steps = ((DOT_MAX_BRIGHTNESS - DOT_MIN_BRIGHTNESS) + ticks - 1) / ticks;
  429. match CLOCK.dot.current_state {
  430. DigitState::Incrementing => {
  431. CLOCK.dot.value = CLOCK
  432. .dot
  433. .value
  434. .saturating_add(steps)
  435. .clamp(DOT_MIN_BRIGHTNESS, DOT_MAX_BRIGHTNESS);
  436. if CLOCK.dot.value >= DOT_MAX_BRIGHTNESS {
  437. CLOCK.dot.value = DOT_MAX_BRIGHTNESS;
  438. CLOCK.dot.current_state = DigitState::Idle;
  439. }
  440. CLOCK.dot.updated = true;
  441. pending_refresh = true;
  442. }
  443. DigitState::Decrementing => {
  444. CLOCK.dot.value = CLOCK
  445. .dot
  446. .value
  447. .saturating_sub(steps)
  448. .clamp(DOT_MIN_BRIGHTNESS, DOT_MAX_BRIGHTNESS);
  449. if CLOCK.dot.value <= DOT_MIN_BRIGHTNESS {
  450. CLOCK.dot.value = DOT_MIN_BRIGHTNESS;
  451. CLOCK.dot.current_state = DigitState::Idle;
  452. }
  453. CLOCK.dot.updated = true;
  454. pending_refresh = true;
  455. }
  456. DigitState::Idle => (),
  457. }
  458. }
  459. if !pending_refresh {
  460. free(|cs| {
  461. let mut timer_ref = super::REFRESH_TIMER.borrow(cs).borrow_mut();
  462. if let Some(ref mut timer) = timer_ref.deref_mut() {
  463. timer.unlisten(Event::TimeOut);
  464. }
  465. })
  466. } else {
  467. compute_pwm_offset();
  468. unsafe {
  469. for (t, tube) in CLOCK.tubes.iter().enumerate() {
  470. for (d, digit) in tube.digits.iter().enumerate() {
  471. if digit.updated {
  472. pca9685::set_digit(
  473. TUBE_MAPPING.driver[t].digit[d].address,
  474. i2c,
  475. TUBE_MAPPING.driver[t].digit[d].pin,
  476. digit.pwm_start,
  477. digit.pwm_end,
  478. );
  479. }
  480. }
  481. }
  482. if CLOCK.dot.updated {
  483. pca9685::set_digit(
  484. TUBE_MAPPING.dot_address,
  485. i2c,
  486. TUBE_MAPPING.dot_pin,
  487. CLOCK.dot.pwm_start,
  488. CLOCK.dot.pwm_end,
  489. );
  490. }
  491. }
  492. free(|cs| {
  493. let mut timer_ref = super::REFRESH_TIMER.borrow(cs).borrow_mut();
  494. if let Some(ref mut timer) = timer_ref.deref_mut() {
  495. timer.clear_interrupt(Event::TimeOut);
  496. }
  497. })
  498. }
  499. }
  500. pub fn rng_tick<T>(_i2c: &mut T)
  501. where
  502. T: _embedded_hal_blocking_i2c_WriteRead
  503. + _embedded_hal_blocking_i2c_Read
  504. + _embedded_hal_blocking_i2c_Write,
  505. {
  506. }
  507. // In the event that there are multiple PWM outputs at less than 100% duty cycle,
  508. // stagger the start time of each PWM to reduce the switch on surge current.
  509. fn compute_pwm_offset() {
  510. // let mut active_digits: u32 = 0;
  511. // let mut total_on_time: u32 = 0;
  512. // let mut last_pwm_end: u32 = 0;
  513. unsafe {
  514. CLOCK.tubes.iter_mut().for_each(|tube| {
  515. tube.digits.iter_mut().for_each(|digit| {
  516. digit.pwm_start = 0;
  517. digit.pwm_end = digit.value;
  518. });
  519. });
  520. CLOCK.dot.pwm_start = 0;
  521. CLOCK.dot.pwm_end = CLOCK.dot.value;
  522. }
  523. // Determine the number of active outputs as well as the total on-time across all outputs.
  524. // Ignore outputs that are off (min) or fully on (max) as they have no surge impact.
  525. // unsafe {
  526. // CLOCK.tubes.iter().for_each(|tube| {
  527. // tube.digits.iter().for_each(|digit| {
  528. // if digit.value != DIGIT_MAX_BRIGHTNESS && digit.value != DIGIT_MIN_BRIGHTNESS {
  529. // active_digits = active_digits + 1;
  530. // total_on_time = total_on_time + digit.value;
  531. // }
  532. // });
  533. // });
  534. // if CLOCK.dot.value != DIGIT_MAX_BRIGHTNESS && CLOCK.dot.value != DIGIT_MIN_BRIGHTNESS {
  535. // active_digits = active_digits + 1;
  536. // total_on_time = total_on_time + CLOCK.dot.value;
  537. // }
  538. // // If the total on-time across all outputs is less than one PWM period, stagger each
  539. // // output such that the rise of one pulse begins at the end of the previous pulse.
  540. // if total_on_time <= DIGIT_MAX_BRIGHTNESS {
  541. // CLOCK.tubes.iter_mut().for_each(|tube| {
  542. // tube.digits.iter_mut().for_each(|digit| {
  543. // if digit.value == DIGIT_MIN_BRIGHTNESS {
  544. // digit.pwm_start = 0;
  545. // digit.pwm_end = 0;
  546. // } else if digit.value == DIGIT_MAX_BRIGHTNESS {
  547. // digit.pwm_start = 0;
  548. // digit.pwm_end = DIGIT_MAX_BRIGHTNESS;
  549. // } else {
  550. // digit.pwm_start = last_pwm_end;
  551. // digit.pwm_end = last_pwm_end + digit.value;
  552. // last_pwm_end = digit.pwm_end;
  553. // digit.updated = true;
  554. // }
  555. // });
  556. // });
  557. // if CLOCK.dot.value == DIGIT_MIN_BRIGHTNESS {
  558. // CLOCK.dot.pwm_start = 0;
  559. // CLOCK.dot.pwm_end = 0;
  560. // } else if CLOCK.dot.value == DIGIT_MAX_BRIGHTNESS {
  561. // CLOCK.dot.pwm_start = 0;
  562. // CLOCK.dot.pwm_end = DIGIT_MAX_BRIGHTNESS;
  563. // } else {
  564. // CLOCK.dot.pwm_start = last_pwm_end;
  565. // CLOCK.dot.pwm_end = last_pwm_end + CLOCK.dot.value;
  566. // CLOCK.dot.updated = true;
  567. // }
  568. // } else {
  569. // // Compute the amount of overlap between all outputs
  570. // let overlap = (total_on_time - DIGIT_MAX_BRIGHTNESS) / (active_digits - 1);
  571. // // Compute the staggered output period for each output
  572. // CLOCK.tubes.iter_mut().for_each(|tube| {
  573. // tube.digits.iter_mut().for_each(|digit| {
  574. // if digit.value == DIGIT_MIN_BRIGHTNESS {
  575. // digit.pwm_start = 0;
  576. // digit.pwm_end = 0;
  577. // } else if digit.value == DIGIT_MAX_BRIGHTNESS {
  578. // digit.pwm_start = 0;
  579. // digit.pwm_end = DIGIT_MAX_BRIGHTNESS;
  580. // } else {
  581. // digit.pwm_start = last_pwm_end.saturating_sub(overlap);
  582. // digit.pwm_end = digit.pwm_start + digit.value;
  583. // last_pwm_end = digit.pwm_end;
  584. // digit.updated = true;
  585. // }
  586. // });
  587. // });
  588. // if CLOCK.dot.value == DIGIT_MIN_BRIGHTNESS {
  589. // CLOCK.dot.pwm_start = 0;
  590. // CLOCK.dot.pwm_end = 0;
  591. // } else if CLOCK.dot.value == DIGIT_MAX_BRIGHTNESS {
  592. // CLOCK.dot.pwm_start = 0;
  593. // CLOCK.dot.pwm_end = DIGIT_MAX_BRIGHTNESS;
  594. // } else {
  595. // CLOCK.dot.pwm_start = last_pwm_end.saturating_sub(overlap);
  596. // CLOCK.dot.pwm_end = CLOCK.dot.pwm_start + CLOCK.dot.value;
  597. // CLOCK.dot.updated = true;
  598. // }
  599. // }
  600. // }
  601. }