NixieTubeClock/Nixie_IN8_Breakout/Nixie_IN8_Breakout.kicad_pcb-bak

(kicad_pcb (version 4) (host pcbnew 4.0.6)

  (general
    (links 12)
    (no_connects 0)
    (area 133.909999 92.6876 165.908401 111.8824)
    (thickness 1.6)
    (drawings 18)
    (tracks 48)
    (zones 0)
    (modules 2)
    (nets 12)
  )

  (page A4)
  (layers
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    (31 B.Cu signal)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (44 Edge.Cuts user)
  )

  (setup
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    (zone_clearance 0.381)
    (zone_45_only yes)
    (trace_min 0.1524)
    (segment_width 0.2)
    (edge_width 0.15)
    (via_size 0.508)
    (via_drill 0.254)
    (via_min_size 0.508)
    (via_min_drill 0.254)
    (uvia_size 0.254)
    (uvia_drill 0.127)
    (uvias_allowed no)
    (uvia_min_size 0.254)
    (uvia_min_drill 0.127)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.5 1.5)
    (pad_drill 1)
    (pad_to_mask_clearance 0.2)
    (aux_axis_origin 0 0)
    (visible_elements 7FFFFF7F)
    (pcbplotparams
      (layerselection 0x00030_80000001)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )

  (net 0 "")
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  (net 2 /9)
  (net 3 /8)
  (net 4 /7)
  (net 5 /6)
  (net 6 /5)
  (net 7 /4)
  (net 8 /3)
  (net 9 /2)
  (net 10 /1)
  (net 11 /A)

  (net_class Default "This is the default net class."
    (clearance 0.1524)
    (trace_width 0.508)
    (via_dia 0.508)
    (via_drill 0.254)
    (uvia_dia 0.254)
    (uvia_drill 0.127)
    (add_net /A)
  )

  (net_class Cathode ""
    (clearance 0.1524)
    (trace_width 0.254)
    (via_dia 0.508)
    (via_drill 0.254)
    (uvia_dia 0.254)
    (uvia_drill 0.127)
    (add_net /0)
    (add_net /1)
    (add_net /2)
    (add_net /3)
    (add_net /4)
    (add_net /5)
    (add_net /6)
    (add_net /7)
    (add_net /8)
    (add_net /9)
  )

  (module "Custom Parts:IN-8" (layer F.Cu) (tedit 5913FEA4) (tstamp 59101982)
    (at 142.875 102.235)
    (path /590F8FF1)
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    (fp_text user 6 (at 0 6) (layer F.SilkS)
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    (fp_text user A (at -3 -5.2) (layer F.SilkS)
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    (pad 3 thru_hole circle (at 4.25 0) (size 2 2) (drill 1.6) (layers *.Cu *.Mask)
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  )

  (module Pin_Headers:Pin_Header_Angled_2x06_Pitch2.54mm (layer F.Cu) (tedit 5913FEA6) (tstamp 59101967)
    (at 152.781 95.885)
    (descr "Through hole angled pin header, 2x06, 2.54mm pitch, 6mm pin length, double rows")
    (tags "Through hole angled pin header THT 2x06 2.54mm double row")
    (path /591006B6)
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