stm32l4xx_hal_spi.c 121 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32l4xx_hal_spi.c
  4. * @author MCD Application Team
  5. * @brief SPI HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the Serial Peripheral Interface (SPI) peripheral:
  8. * + Initialization and de-initialization functions
  9. * + IO operation functions
  10. * + Peripheral Control functions
  11. * + Peripheral State functions
  12. *
  13. @verbatim
  14. ==============================================================================
  15. ##### How to use this driver #####
  16. ==============================================================================
  17. [..]
  18. The SPI HAL driver can be used as follows:
  19. (#) Declare a SPI_HandleTypeDef handle structure, for example:
  20. SPI_HandleTypeDef hspi;
  21. (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
  22. (##) Enable the SPIx interface clock
  23. (##) SPI pins configuration
  24. (+++) Enable the clock for the SPI GPIOs
  25. (+++) Configure these SPI pins as alternate function push-pull
  26. (##) NVIC configuration if you need to use interrupt process
  27. (+++) Configure the SPIx interrupt priority
  28. (+++) Enable the NVIC SPI IRQ handle
  29. (##) DMA Configuration if you need to use DMA process
  30. (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
  31. (+++) Enable the DMAx clock
  32. (+++) Configure the DMA handle parameters
  33. (+++) Configure the DMA Tx or Rx Stream/Channel
  34. (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
  35. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
  36. (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
  37. management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
  38. (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
  39. (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
  40. by calling the customized HAL_SPI_MspInit() API.
  41. [..]
  42. Circular mode restriction:
  43. (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
  44. (##) Master 2Lines RxOnly
  45. (##) Master 1Line Rx
  46. (#) The CRC feature is not managed when the DMA circular mode is enabled
  47. (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
  48. the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
  49. [..]
  50. Master Receive mode restriction:
  51. (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
  52. bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
  53. does not initiate a new transfer the following procedure has to be respected:
  54. (##) HAL_SPI_DeInit()
  55. (##) HAL_SPI_Init()
  56. [..]
  57. Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
  58. the following table resume the max SPI frequency reached with data size 8bits/16bits,
  59. according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
  60. @endverbatim
  61. Additional table :
  62. DataSize = SPI_DATASIZE_8BIT:
  63. +----------------------------------------------------------------------------------------------+
  64. | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
  65. | Process | Tranfert mode |---------------------|----------------------|----------------------|
  66. | | | Master | Slave | Master | Slave | Master | Slave |
  67. |==============================================================================================|
  68. | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
  69. | X |----------------|----------|----------|-----------|----------|-----------|----------|
  70. | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
  71. | R |----------------|----------|----------|-----------|----------|-----------|----------|
  72. | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
  73. |=========|================|==========|==========|===========|==========|===========|==========|
  74. | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
  75. | |----------------|----------|----------|-----------|----------|-----------|----------|
  76. | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
  77. | X |----------------|----------|----------|-----------|----------|-----------|----------|
  78. | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
  79. |=========|================|==========|==========|===========|==========|===========|==========|
  80. | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
  81. | |----------------|----------|----------|-----------|----------|-----------|----------|
  82. | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
  83. | X |----------------|----------|----------|-----------|----------|-----------|----------|
  84. | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
  85. +----------------------------------------------------------------------------------------------+
  86. DataSize = SPI_DATASIZE_16BIT:
  87. +----------------------------------------------------------------------------------------------+
  88. | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
  89. | Process | Tranfert mode |---------------------|----------------------|----------------------|
  90. | | | Master | Slave | Master | Slave | Master | Slave |
  91. |==============================================================================================|
  92. | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
  93. | X |----------------|----------|----------|-----------|----------|-----------|----------|
  94. | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
  95. | R |----------------|----------|----------|-----------|----------|-----------|----------|
  96. | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
  97. |=========|================|==========|==========|===========|==========|===========|==========|
  98. | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
  99. | |----------------|----------|----------|-----------|----------|-----------|----------|
  100. | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
  101. | X |----------------|----------|----------|-----------|----------|-----------|----------|
  102. | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
  103. |=========|================|==========|==========|===========|==========|===========|==========|
  104. | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
  105. | |----------------|----------|----------|-----------|----------|-----------|----------|
  106. | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
  107. | X |----------------|----------|----------|-----------|----------|-----------|----------|
  108. | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
  109. +----------------------------------------------------------------------------------------------+
  110. @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
  111. SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
  112. @note
  113. (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
  114. (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
  115. (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
  116. ******************************************************************************
  117. * @attention
  118. *
  119. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  120. *
  121. * Redistribution and use in source and binary forms, with or without modification,
  122. * are permitted provided that the following conditions are met:
  123. * 1. Redistributions of source code must retain the above copyright notice,
  124. * this list of conditions and the following disclaimer.
  125. * 2. Redistributions in binary form must reproduce the above copyright notice,
  126. * this list of conditions and the following disclaimer in the documentation
  127. * and/or other materials provided with the distribution.
  128. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  129. * may be used to endorse or promote products derived from this software
  130. * without specific prior written permission.
  131. *
  132. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  133. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  134. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  135. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  136. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  137. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  138. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  139. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  140. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  141. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  142. *
  143. ******************************************************************************
  144. */
  145. /* Includes ------------------------------------------------------------------*/
  146. #include "stm32l4xx_hal.h"
  147. /** @addtogroup STM32L4xx_HAL_Driver
  148. * @{
  149. */
  150. /** @defgroup SPI SPI
  151. * @brief SPI HAL module driver
  152. * @{
  153. */
  154. #ifdef HAL_SPI_MODULE_ENABLED
  155. /* Private typedef -----------------------------------------------------------*/
  156. /* Private defines -----------------------------------------------------------*/
  157. /** @defgroup SPI_Private_Constants SPI Private Constants
  158. * @{
  159. */
  160. #define SPI_DEFAULT_TIMEOUT 100U
  161. /**
  162. * @}
  163. */
  164. /* Private macros ------------------------------------------------------------*/
  165. /* Private variables ---------------------------------------------------------*/
  166. /* Private function prototypes -----------------------------------------------*/
  167. /** @defgroup SPI_Private_Functions SPI Private Functions
  168. * @{
  169. */
  170. static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
  171. static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
  172. static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
  173. static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
  174. static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
  175. static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
  176. static void SPI_DMAError(DMA_HandleTypeDef *hdma);
  177. static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
  178. static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
  179. static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
  180. static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
  181. uint32_t Timeout, uint32_t Tickstart);
  182. static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
  183. uint32_t Timeout, uint32_t Tickstart);
  184. static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
  185. static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
  186. static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
  187. static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
  188. static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
  189. static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
  190. static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
  191. static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
  192. #if (USE_SPI_CRC != 0U)
  193. static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
  194. static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
  195. static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
  196. static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
  197. #endif /* USE_SPI_CRC */
  198. static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
  199. static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
  200. static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
  201. static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
  202. static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
  203. static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
  204. static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
  205. /**
  206. * @}
  207. */
  208. /* Exported functions --------------------------------------------------------*/
  209. /** @defgroup SPI_Exported_Functions SPI Exported Functions
  210. * @{
  211. */
  212. /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
  213. * @brief Initialization and Configuration functions
  214. *
  215. @verbatim
  216. ===============================================================================
  217. ##### Initialization and de-initialization functions #####
  218. ===============================================================================
  219. [..] This subsection provides a set of functions allowing to initialize and
  220. de-initialize the SPIx peripheral:
  221. (+) User must implement HAL_SPI_MspInit() function in which he configures
  222. all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
  223. (+) Call the function HAL_SPI_Init() to configure the selected device with
  224. the selected configuration:
  225. (++) Mode
  226. (++) Direction
  227. (++) Data Size
  228. (++) Clock Polarity and Phase
  229. (++) NSS Management
  230. (++) BaudRate Prescaler
  231. (++) FirstBit
  232. (++) TIMode
  233. (++) CRC Calculation
  234. (++) CRC Polynomial if CRC enabled
  235. (++) CRC Length, used only with Data8 and Data16
  236. (++) FIFO reception threshold
  237. (+) Call the function HAL_SPI_DeInit() to restore the default configuration
  238. of the selected SPIx peripheral.
  239. @endverbatim
  240. * @{
  241. */
  242. /**
  243. * @brief Initialize the SPI according to the specified parameters
  244. * in the SPI_InitTypeDef and initialize the associated handle.
  245. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  246. * the configuration information for SPI module.
  247. * @retval HAL status
  248. */
  249. HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
  250. {
  251. uint32_t frxth;
  252. /* Check the SPI handle allocation */
  253. if (hspi == NULL)
  254. {
  255. return HAL_ERROR;
  256. }
  257. /* Check the parameters */
  258. assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
  259. assert_param(IS_SPI_MODE(hspi->Init.Mode));
  260. assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
  261. assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
  262. assert_param(IS_SPI_NSS(hspi->Init.NSS));
  263. assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
  264. assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
  265. assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
  266. assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
  267. if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
  268. {
  269. assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
  270. assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
  271. }
  272. #if (USE_SPI_CRC != 0U)
  273. assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
  274. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  275. {
  276. assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
  277. assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
  278. }
  279. #else
  280. hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
  281. #endif /* USE_SPI_CRC */
  282. if (hspi->State == HAL_SPI_STATE_RESET)
  283. {
  284. /* Allocate lock resource and initialize it */
  285. hspi->Lock = HAL_UNLOCKED;
  286. /* Init the low level hardware : GPIO, CLOCK, NVIC... */
  287. HAL_SPI_MspInit(hspi);
  288. }
  289. hspi->State = HAL_SPI_STATE_BUSY;
  290. /* Disable the selected SPI peripheral */
  291. __HAL_SPI_DISABLE(hspi);
  292. /* Align by default the rs fifo threshold on the data size */
  293. if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  294. {
  295. frxth = SPI_RXFIFO_THRESHOLD_HF;
  296. }
  297. else
  298. {
  299. frxth = SPI_RXFIFO_THRESHOLD_QF;
  300. }
  301. /* CRC calculation is valid only for 16Bit and 8 Bit */
  302. if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
  303. {
  304. /* CRC must be disabled */
  305. hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
  306. }
  307. /* Align the CRC Length on the data size */
  308. if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
  309. {
  310. /* CRC Length aligned on the data size : value set by default */
  311. if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  312. {
  313. hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
  314. }
  315. else
  316. {
  317. hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
  318. }
  319. }
  320. /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
  321. /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
  322. Communication speed, First bit and CRC calculation state */
  323. WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
  324. hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
  325. hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
  326. #if (USE_SPI_CRC != 0U)
  327. /* Configure : CRC Length */
  328. if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
  329. {
  330. hspi->Instance->CR1 |= SPI_CR1_CRCL;
  331. }
  332. #endif /* USE_SPI_CRC */
  333. /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
  334. WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
  335. hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
  336. #if (USE_SPI_CRC != 0U)
  337. /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
  338. /* Configure : CRC Polynomial */
  339. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  340. {
  341. WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
  342. }
  343. #endif /* USE_SPI_CRC */
  344. #if defined(SPI_I2SCFGR_I2SMOD)
  345. /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
  346. CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
  347. #endif /* SPI_I2SCFGR_I2SMOD */
  348. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  349. hspi->State = HAL_SPI_STATE_READY;
  350. return HAL_OK;
  351. }
  352. /**
  353. * @brief De-Initialize the SPI peripheral.
  354. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  355. * the configuration information for SPI module.
  356. * @retval HAL status
  357. */
  358. HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
  359. {
  360. /* Check the SPI handle allocation */
  361. if (hspi == NULL)
  362. {
  363. return HAL_ERROR;
  364. }
  365. /* Check SPI Instance parameter */
  366. assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
  367. hspi->State = HAL_SPI_STATE_BUSY;
  368. /* Disable the SPI Peripheral Clock */
  369. __HAL_SPI_DISABLE(hspi);
  370. /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
  371. HAL_SPI_MspDeInit(hspi);
  372. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  373. hspi->State = HAL_SPI_STATE_RESET;
  374. /* Release Lock */
  375. __HAL_UNLOCK(hspi);
  376. return HAL_OK;
  377. }
  378. /**
  379. * @brief Initialize the SPI MSP.
  380. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  381. * the configuration information for SPI module.
  382. * @retval None
  383. */
  384. __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
  385. {
  386. /* Prevent unused argument(s) compilation warning */
  387. UNUSED(hspi);
  388. /* NOTE : This function should not be modified, when the callback is needed,
  389. the HAL_SPI_MspInit should be implemented in the user file
  390. */
  391. }
  392. /**
  393. * @brief De-Initialize the SPI MSP.
  394. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  395. * the configuration information for SPI module.
  396. * @retval None
  397. */
  398. __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
  399. {
  400. /* Prevent unused argument(s) compilation warning */
  401. UNUSED(hspi);
  402. /* NOTE : This function should not be modified, when the callback is needed,
  403. the HAL_SPI_MspDeInit should be implemented in the user file
  404. */
  405. }
  406. /**
  407. * @}
  408. */
  409. /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
  410. * @brief Data transfers functions
  411. *
  412. @verbatim
  413. ==============================================================================
  414. ##### IO operation functions #####
  415. ===============================================================================
  416. [..]
  417. This subsection provides a set of functions allowing to manage the SPI
  418. data transfers.
  419. [..] The SPI supports master and slave mode :
  420. (#) There are two modes of transfer:
  421. (++) Blocking mode: The communication is performed in polling mode.
  422. The HAL status of all data processing is returned by the same function
  423. after finishing transfer.
  424. (++) No-Blocking mode: The communication is performed using Interrupts
  425. or DMA, These APIs return the HAL status.
  426. The end of the data processing will be indicated through the
  427. dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
  428. using DMA mode.
  429. The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
  430. will be executed respectively at the end of the transmit or Receive process
  431. The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
  432. (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
  433. exist for 1Line (simplex) and 2Lines (full duplex) modes.
  434. @endverbatim
  435. * @{
  436. */
  437. /**
  438. * @brief Transmit an amount of data in blocking mode.
  439. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  440. * the configuration information for SPI module.
  441. * @param pData pointer to data buffer
  442. * @param Size amount of data to be sent
  443. * @param Timeout Timeout duration
  444. * @retval HAL status
  445. */
  446. HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
  447. {
  448. uint32_t tickstart = 0U;
  449. HAL_StatusTypeDef errorcode = HAL_OK;
  450. /* Check Direction parameter */
  451. assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
  452. /* Process Locked */
  453. __HAL_LOCK(hspi);
  454. /* Init tickstart for timeout management*/
  455. tickstart = HAL_GetTick();
  456. if (hspi->State != HAL_SPI_STATE_READY)
  457. {
  458. errorcode = HAL_BUSY;
  459. goto error;
  460. }
  461. if ((pData == NULL) || (Size == 0U))
  462. {
  463. errorcode = HAL_ERROR;
  464. goto error;
  465. }
  466. /* Set the transaction information */
  467. hspi->State = HAL_SPI_STATE_BUSY_TX;
  468. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  469. hspi->pTxBuffPtr = (uint8_t *)pData;
  470. hspi->TxXferSize = Size;
  471. hspi->TxXferCount = Size;
  472. /*Init field not used in handle to zero */
  473. hspi->pRxBuffPtr = (uint8_t *)NULL;
  474. hspi->RxXferSize = 0U;
  475. hspi->RxXferCount = 0U;
  476. hspi->TxISR = NULL;
  477. hspi->RxISR = NULL;
  478. /* Configure communication direction : 1Line */
  479. if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
  480. {
  481. SPI_1LINE_TX(hspi);
  482. }
  483. #if (USE_SPI_CRC != 0U)
  484. /* Reset CRC Calculation */
  485. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  486. {
  487. SPI_RESET_CRC(hspi);
  488. }
  489. #endif /* USE_SPI_CRC */
  490. /* Check if the SPI is already enabled */
  491. if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  492. {
  493. /* Enable SPI peripheral */
  494. __HAL_SPI_ENABLE(hspi);
  495. }
  496. /* Transmit data in 16 Bit mode */
  497. if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  498. {
  499. if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
  500. {
  501. hspi->Instance->DR = *((uint16_t *)pData);
  502. pData += sizeof(uint16_t);
  503. hspi->TxXferCount--;
  504. }
  505. /* Transmit data in 16 Bit mode */
  506. while (hspi->TxXferCount > 0U)
  507. {
  508. /* Wait until TXE flag is set to send data */
  509. if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
  510. {
  511. hspi->Instance->DR = *((uint16_t *)pData);
  512. pData += sizeof(uint16_t);
  513. hspi->TxXferCount--;
  514. }
  515. else
  516. {
  517. /* Timeout management */
  518. if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
  519. {
  520. errorcode = HAL_TIMEOUT;
  521. goto error;
  522. }
  523. }
  524. }
  525. }
  526. /* Transmit data in 8 Bit mode */
  527. else
  528. {
  529. if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
  530. {
  531. if (hspi->TxXferCount > 1U)
  532. {
  533. /* write on the data register in packing mode */
  534. hspi->Instance->DR = *((uint16_t *)pData);
  535. pData += sizeof(uint16_t);
  536. hspi->TxXferCount -= 2U;
  537. }
  538. else
  539. {
  540. *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
  541. hspi->TxXferCount--;
  542. }
  543. }
  544. while (hspi->TxXferCount > 0U)
  545. {
  546. /* Wait until TXE flag is set to send data */
  547. if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
  548. {
  549. if (hspi->TxXferCount > 1U)
  550. {
  551. /* write on the data register in packing mode */
  552. hspi->Instance->DR = *((uint16_t *)pData);
  553. pData += sizeof(uint16_t);
  554. hspi->TxXferCount -= 2U;
  555. }
  556. else
  557. {
  558. *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
  559. hspi->TxXferCount--;
  560. }
  561. }
  562. else
  563. {
  564. /* Timeout management */
  565. if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
  566. {
  567. errorcode = HAL_TIMEOUT;
  568. goto error;
  569. }
  570. }
  571. }
  572. }
  573. #if (USE_SPI_CRC != 0U)
  574. /* Enable CRC Transmission */
  575. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  576. {
  577. SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  578. }
  579. #endif /* USE_SPI_CRC */
  580. /* Check the end of the transaction */
  581. if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
  582. {
  583. hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
  584. }
  585. /* Clear overrun flag in 2 Lines communication mode because received is not read */
  586. if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
  587. {
  588. __HAL_SPI_CLEAR_OVRFLAG(hspi);
  589. }
  590. if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  591. {
  592. errorcode = HAL_ERROR;
  593. }
  594. error:
  595. hspi->State = HAL_SPI_STATE_READY;
  596. /* Process Unlocked */
  597. __HAL_UNLOCK(hspi);
  598. return errorcode;
  599. }
  600. /**
  601. * @brief Receive an amount of data in blocking mode.
  602. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  603. * the configuration information for SPI module.
  604. * @param pData pointer to data buffer
  605. * @param Size amount of data to be received
  606. * @param Timeout Timeout duration
  607. * @retval HAL status
  608. */
  609. HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
  610. {
  611. #if (USE_SPI_CRC != 0U)
  612. __IO uint16_t tmpreg = 0U;
  613. #endif /* USE_SPI_CRC */
  614. uint32_t tickstart = 0U;
  615. HAL_StatusTypeDef errorcode = HAL_OK;
  616. if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
  617. {
  618. hspi->State = HAL_SPI_STATE_BUSY_RX;
  619. /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
  620. return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
  621. }
  622. /* Process Locked */
  623. __HAL_LOCK(hspi);
  624. /* Init tickstart for timeout management*/
  625. tickstart = HAL_GetTick();
  626. if (hspi->State != HAL_SPI_STATE_READY)
  627. {
  628. errorcode = HAL_BUSY;
  629. goto error;
  630. }
  631. if ((pData == NULL) || (Size == 0U))
  632. {
  633. errorcode = HAL_ERROR;
  634. goto error;
  635. }
  636. /* Set the transaction information */
  637. hspi->State = HAL_SPI_STATE_BUSY_RX;
  638. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  639. hspi->pRxBuffPtr = (uint8_t *)pData;
  640. hspi->RxXferSize = Size;
  641. hspi->RxXferCount = Size;
  642. /*Init field not used in handle to zero */
  643. hspi->pTxBuffPtr = (uint8_t *)NULL;
  644. hspi->TxXferSize = 0U;
  645. hspi->TxXferCount = 0U;
  646. hspi->RxISR = NULL;
  647. hspi->TxISR = NULL;
  648. #if (USE_SPI_CRC != 0U)
  649. /* Reset CRC Calculation */
  650. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  651. {
  652. SPI_RESET_CRC(hspi);
  653. /* this is done to handle the CRCNEXT before the latest data */
  654. hspi->RxXferCount--;
  655. }
  656. #endif /* USE_SPI_CRC */
  657. /* Set the Rx Fifo threshold */
  658. if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  659. {
  660. /* Set RX Fifo threshold according the reception data length: 16bit */
  661. CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  662. }
  663. else
  664. {
  665. /* Set RX Fifo threshold according the reception data length: 8bit */
  666. SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  667. }
  668. /* Configure communication direction: 1Line */
  669. if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
  670. {
  671. SPI_1LINE_RX(hspi);
  672. }
  673. /* Check if the SPI is already enabled */
  674. if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  675. {
  676. /* Enable SPI peripheral */
  677. __HAL_SPI_ENABLE(hspi);
  678. }
  679. /* Receive data in 8 Bit mode */
  680. if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
  681. {
  682. /* Transfer loop */
  683. while (hspi->RxXferCount > 0U)
  684. {
  685. /* Check the RXNE flag */
  686. if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
  687. {
  688. /* read the received data */
  689. (* (uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
  690. pData += sizeof(uint8_t);
  691. hspi->RxXferCount--;
  692. }
  693. else
  694. {
  695. /* Timeout management */
  696. if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
  697. {
  698. errorcode = HAL_TIMEOUT;
  699. goto error;
  700. }
  701. }
  702. }
  703. }
  704. else
  705. {
  706. /* Transfer loop */
  707. while (hspi->RxXferCount > 0U)
  708. {
  709. /* Check the RXNE flag */
  710. if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
  711. {
  712. *((uint16_t *)pData) = hspi->Instance->DR;
  713. pData += sizeof(uint16_t);
  714. hspi->RxXferCount--;
  715. }
  716. else
  717. {
  718. /* Timeout management */
  719. if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
  720. {
  721. errorcode = HAL_TIMEOUT;
  722. goto error;
  723. }
  724. }
  725. }
  726. }
  727. #if (USE_SPI_CRC != 0U)
  728. /* Handle the CRC Transmission */
  729. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  730. {
  731. /* freeze the CRC before the latest data */
  732. SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  733. /* Read the latest data */
  734. if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
  735. {
  736. /* the latest data has not been received */
  737. errorcode = HAL_TIMEOUT;
  738. goto error;
  739. }
  740. /* Receive last data in 16 Bit mode */
  741. if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  742. {
  743. *((uint16_t *)pData) = hspi->Instance->DR;
  744. }
  745. /* Receive last data in 8 Bit mode */
  746. else
  747. {
  748. (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
  749. }
  750. /* Wait the CRC data */
  751. if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
  752. {
  753. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  754. errorcode = HAL_TIMEOUT;
  755. goto error;
  756. }
  757. /* Read CRC to Flush DR and RXNE flag */
  758. if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
  759. {
  760. tmpreg = hspi->Instance->DR;
  761. /* To avoid GCC warning */
  762. UNUSED(tmpreg);
  763. }
  764. else
  765. {
  766. tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
  767. /* To avoid GCC warning */
  768. UNUSED(tmpreg);
  769. if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
  770. {
  771. if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
  772. {
  773. /* Error on the CRC reception */
  774. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  775. errorcode = HAL_TIMEOUT;
  776. goto error;
  777. }
  778. tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
  779. /* To avoid GCC warning */
  780. UNUSED(tmpreg);
  781. }
  782. }
  783. }
  784. #endif /* USE_SPI_CRC */
  785. /* Check the end of the transaction */
  786. if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
  787. {
  788. hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
  789. }
  790. #if (USE_SPI_CRC != 0U)
  791. /* Check if CRC error occurred */
  792. if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
  793. {
  794. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  795. __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
  796. }
  797. #endif /* USE_SPI_CRC */
  798. if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  799. {
  800. errorcode = HAL_ERROR;
  801. }
  802. error :
  803. hspi->State = HAL_SPI_STATE_READY;
  804. __HAL_UNLOCK(hspi);
  805. return errorcode;
  806. }
  807. /**
  808. * @brief Transmit and Receive an amount of data in blocking mode.
  809. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  810. * the configuration information for SPI module.
  811. * @param pTxData pointer to transmission data buffer
  812. * @param pRxData pointer to reception data buffer
  813. * @param Size amount of data to be sent and received
  814. * @param Timeout Timeout duration
  815. * @retval HAL status
  816. */
  817. HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
  818. uint32_t Timeout)
  819. {
  820. uint32_t tmp = 0U, tmp1 = 0U;
  821. #if (USE_SPI_CRC != 0U)
  822. __IO uint16_t tmpreg = 0U;
  823. #endif /* USE_SPI_CRC */
  824. uint32_t tickstart = 0U;
  825. /* Variable used to alternate Rx and Tx during transfer */
  826. uint32_t txallowed = 1U;
  827. HAL_StatusTypeDef errorcode = HAL_OK;
  828. /* Check Direction parameter */
  829. assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
  830. /* Process Locked */
  831. __HAL_LOCK(hspi);
  832. /* Init tickstart for timeout management*/
  833. tickstart = HAL_GetTick();
  834. tmp = hspi->State;
  835. tmp1 = hspi->Init.Mode;
  836. if (!((tmp == HAL_SPI_STATE_READY) || \
  837. ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
  838. {
  839. errorcode = HAL_BUSY;
  840. goto error;
  841. }
  842. if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
  843. {
  844. errorcode = HAL_ERROR;
  845. goto error;
  846. }
  847. /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
  848. if (hspi->State != HAL_SPI_STATE_BUSY_RX)
  849. {
  850. hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
  851. }
  852. /* Set the transaction information */
  853. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  854. hspi->pRxBuffPtr = (uint8_t *)pRxData;
  855. hspi->RxXferCount = Size;
  856. hspi->RxXferSize = Size;
  857. hspi->pTxBuffPtr = (uint8_t *)pTxData;
  858. hspi->TxXferCount = Size;
  859. hspi->TxXferSize = Size;
  860. /*Init field not used in handle to zero */
  861. hspi->RxISR = NULL;
  862. hspi->TxISR = NULL;
  863. #if (USE_SPI_CRC != 0U)
  864. /* Reset CRC Calculation */
  865. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  866. {
  867. SPI_RESET_CRC(hspi);
  868. }
  869. #endif /* USE_SPI_CRC */
  870. /* Set the Rx Fifo threshold */
  871. if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U))
  872. {
  873. /* Set fiforxthreshold according the reception data length: 16bit */
  874. CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  875. }
  876. else
  877. {
  878. /* Set fiforxthreshold according the reception data length: 8bit */
  879. SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  880. }
  881. /* Check if the SPI is already enabled */
  882. if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  883. {
  884. /* Enable SPI peripheral */
  885. __HAL_SPI_ENABLE(hspi);
  886. }
  887. /* Transmit and Receive data in 16 Bit mode */
  888. if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  889. {
  890. if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
  891. {
  892. hspi->Instance->DR = *((uint16_t *)pTxData);
  893. pTxData += sizeof(uint16_t);
  894. hspi->TxXferCount--;
  895. }
  896. while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
  897. {
  898. /* Check TXE flag */
  899. if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
  900. {
  901. hspi->Instance->DR = *((uint16_t *)pTxData);
  902. pTxData += sizeof(uint16_t);
  903. hspi->TxXferCount--;
  904. /* Next Data is a reception (Rx). Tx not allowed */
  905. txallowed = 0U;
  906. #if (USE_SPI_CRC != 0U)
  907. /* Enable CRC Transmission */
  908. if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
  909. {
  910. /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
  911. if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
  912. {
  913. SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
  914. }
  915. SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  916. }
  917. #endif /* USE_SPI_CRC */
  918. }
  919. /* Check RXNE flag */
  920. if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
  921. {
  922. *((uint16_t *)pRxData) = hspi->Instance->DR;
  923. pRxData += sizeof(uint16_t);
  924. hspi->RxXferCount--;
  925. /* Next Data is a Transmission (Tx). Tx is allowed */
  926. txallowed = 1U;
  927. }
  928. if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
  929. {
  930. errorcode = HAL_TIMEOUT;
  931. goto error;
  932. }
  933. }
  934. }
  935. /* Transmit and Receive data in 8 Bit mode */
  936. else
  937. {
  938. if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
  939. {
  940. if (hspi->TxXferCount > 1U)
  941. {
  942. hspi->Instance->DR = *((uint16_t *)pTxData);
  943. pTxData += sizeof(uint16_t);
  944. hspi->TxXferCount -= 2U;
  945. }
  946. else
  947. {
  948. *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
  949. hspi->TxXferCount--;
  950. }
  951. }
  952. while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
  953. {
  954. /* Check TXE flag */
  955. if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
  956. {
  957. if (hspi->TxXferCount > 1U)
  958. {
  959. hspi->Instance->DR = *((uint16_t *)pTxData);
  960. pTxData += sizeof(uint16_t);
  961. hspi->TxXferCount -= 2U;
  962. }
  963. else
  964. {
  965. *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
  966. hspi->TxXferCount--;
  967. }
  968. /* Next Data is a reception (Rx). Tx not allowed */
  969. txallowed = 0U;
  970. #if (USE_SPI_CRC != 0U)
  971. /* Enable CRC Transmission */
  972. if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
  973. {
  974. /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
  975. if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
  976. {
  977. SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
  978. }
  979. SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  980. }
  981. #endif /* USE_SPI_CRC */
  982. }
  983. /* Wait until RXNE flag is reset */
  984. if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
  985. {
  986. if (hspi->RxXferCount > 1U)
  987. {
  988. *((uint16_t *)pRxData) = hspi->Instance->DR;
  989. pRxData += sizeof(uint16_t);
  990. hspi->RxXferCount -= 2U;
  991. if (hspi->RxXferCount <= 1U)
  992. {
  993. /* Set RX Fifo threshold before to switch on 8 bit data size */
  994. SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  995. }
  996. }
  997. else
  998. {
  999. (*(uint8_t *)pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
  1000. hspi->RxXferCount--;
  1001. }
  1002. /* Next Data is a Transmission (Tx). Tx is allowed */
  1003. txallowed = 1U;
  1004. }
  1005. if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
  1006. {
  1007. errorcode = HAL_TIMEOUT;
  1008. goto error;
  1009. }
  1010. }
  1011. }
  1012. #if (USE_SPI_CRC != 0U)
  1013. /* Read CRC from DR to close CRC calculation process */
  1014. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1015. {
  1016. /* Wait until TXE flag */
  1017. if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
  1018. {
  1019. /* Error on the CRC reception */
  1020. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  1021. errorcode = HAL_TIMEOUT;
  1022. goto error;
  1023. }
  1024. /* Read CRC */
  1025. if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
  1026. {
  1027. tmpreg = hspi->Instance->DR;
  1028. /* To avoid GCC warning */
  1029. UNUSED(tmpreg);
  1030. }
  1031. else
  1032. {
  1033. tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
  1034. /* To avoid GCC warning */
  1035. UNUSED(tmpreg);
  1036. if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
  1037. {
  1038. if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
  1039. {
  1040. /* Error on the CRC reception */
  1041. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  1042. errorcode = HAL_TIMEOUT;
  1043. goto error;
  1044. }
  1045. tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
  1046. /* To avoid GCC warning */
  1047. UNUSED(tmpreg);
  1048. }
  1049. }
  1050. }
  1051. /* Check if CRC error occurred */
  1052. if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
  1053. {
  1054. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  1055. /* Clear CRC Flag */
  1056. __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
  1057. errorcode = HAL_ERROR;
  1058. }
  1059. #endif /* USE_SPI_CRC */
  1060. /* Check the end of the transaction */
  1061. if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
  1062. {
  1063. errorcode = HAL_ERROR;
  1064. hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
  1065. }
  1066. error :
  1067. hspi->State = HAL_SPI_STATE_READY;
  1068. __HAL_UNLOCK(hspi);
  1069. return errorcode;
  1070. }
  1071. /**
  1072. * @brief Transmit an amount of data in non-blocking mode with Interrupt.
  1073. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  1074. * the configuration information for SPI module.
  1075. * @param pData pointer to data buffer
  1076. * @param Size amount of data to be sent
  1077. * @retval HAL status
  1078. */
  1079. HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
  1080. {
  1081. HAL_StatusTypeDef errorcode = HAL_OK;
  1082. /* Check Direction parameter */
  1083. assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
  1084. /* Process Locked */
  1085. __HAL_LOCK(hspi);
  1086. if ((pData == NULL) || (Size == 0U))
  1087. {
  1088. errorcode = HAL_ERROR;
  1089. goto error;
  1090. }
  1091. if (hspi->State != HAL_SPI_STATE_READY)
  1092. {
  1093. errorcode = HAL_BUSY;
  1094. goto error;
  1095. }
  1096. /* Set the transaction information */
  1097. hspi->State = HAL_SPI_STATE_BUSY_TX;
  1098. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  1099. hspi->pTxBuffPtr = (uint8_t *)pData;
  1100. hspi->TxXferSize = Size;
  1101. hspi->TxXferCount = Size;
  1102. /* Init field not used in handle to zero */
  1103. hspi->pRxBuffPtr = (uint8_t *)NULL;
  1104. hspi->RxXferSize = 0U;
  1105. hspi->RxXferCount = 0U;
  1106. hspi->RxISR = NULL;
  1107. /* Set the function for IT treatment */
  1108. if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  1109. {
  1110. hspi->TxISR = SPI_TxISR_16BIT;
  1111. }
  1112. else
  1113. {
  1114. hspi->TxISR = SPI_TxISR_8BIT;
  1115. }
  1116. /* Configure communication direction : 1Line */
  1117. if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
  1118. {
  1119. SPI_1LINE_TX(hspi);
  1120. }
  1121. #if (USE_SPI_CRC != 0U)
  1122. /* Reset CRC Calculation */
  1123. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1124. {
  1125. SPI_RESET_CRC(hspi);
  1126. }
  1127. #endif /* USE_SPI_CRC */
  1128. /* Enable TXE and ERR interrupt */
  1129. __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
  1130. /* Check if the SPI is already enabled */
  1131. if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  1132. {
  1133. /* Enable SPI peripheral */
  1134. __HAL_SPI_ENABLE(hspi);
  1135. }
  1136. error :
  1137. __HAL_UNLOCK(hspi);
  1138. return errorcode;
  1139. }
  1140. /**
  1141. * @brief Receive an amount of data in non-blocking mode with Interrupt.
  1142. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  1143. * the configuration information for SPI module.
  1144. * @param pData pointer to data buffer
  1145. * @param Size amount of data to be sent
  1146. * @retval HAL status
  1147. */
  1148. HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
  1149. {
  1150. HAL_StatusTypeDef errorcode = HAL_OK;
  1151. if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
  1152. {
  1153. hspi->State = HAL_SPI_STATE_BUSY_RX;
  1154. /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
  1155. return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
  1156. }
  1157. /* Process Locked */
  1158. __HAL_LOCK(hspi);
  1159. if (hspi->State != HAL_SPI_STATE_READY)
  1160. {
  1161. errorcode = HAL_BUSY;
  1162. goto error;
  1163. }
  1164. if ((pData == NULL) || (Size == 0U))
  1165. {
  1166. errorcode = HAL_ERROR;
  1167. goto error;
  1168. }
  1169. /* Set the transaction information */
  1170. hspi->State = HAL_SPI_STATE_BUSY_RX;
  1171. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  1172. hspi->pRxBuffPtr = (uint8_t *)pData;
  1173. hspi->RxXferSize = Size;
  1174. hspi->RxXferCount = Size;
  1175. /* Init field not used in handle to zero */
  1176. hspi->pTxBuffPtr = (uint8_t *)NULL;
  1177. hspi->TxXferSize = 0U;
  1178. hspi->TxXferCount = 0U;
  1179. hspi->TxISR = NULL;
  1180. /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
  1181. if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  1182. {
  1183. /* Set RX Fifo threshold according the reception data length: 16 bit */
  1184. CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1185. hspi->RxISR = SPI_RxISR_16BIT;
  1186. }
  1187. else
  1188. {
  1189. /* Set RX Fifo threshold according the reception data length: 8 bit */
  1190. SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1191. hspi->RxISR = SPI_RxISR_8BIT;
  1192. }
  1193. /* Configure communication direction : 1Line */
  1194. if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
  1195. {
  1196. SPI_1LINE_RX(hspi);
  1197. }
  1198. #if (USE_SPI_CRC != 0U)
  1199. /* Reset CRC Calculation */
  1200. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1201. {
  1202. hspi->CRCSize = 1U;
  1203. if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
  1204. {
  1205. hspi->CRCSize = 2U;
  1206. }
  1207. SPI_RESET_CRC(hspi);
  1208. }
  1209. else
  1210. {
  1211. hspi->CRCSize = 0U;
  1212. }
  1213. #endif /* USE_SPI_CRC */
  1214. /* Enable TXE and ERR interrupt */
  1215. __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
  1216. /* Note : The SPI must be enabled after unlocking current process
  1217. to avoid the risk of SPI interrupt handle execution before current
  1218. process unlock */
  1219. /* Check if the SPI is already enabled */
  1220. if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  1221. {
  1222. /* Enable SPI peripheral */
  1223. __HAL_SPI_ENABLE(hspi);
  1224. }
  1225. error :
  1226. /* Process Unlocked */
  1227. __HAL_UNLOCK(hspi);
  1228. return errorcode;
  1229. }
  1230. /**
  1231. * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
  1232. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  1233. * the configuration information for SPI module.
  1234. * @param pTxData pointer to transmission data buffer
  1235. * @param pRxData pointer to reception data buffer
  1236. * @param Size amount of data to be sent and received
  1237. * @retval HAL status
  1238. */
  1239. HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
  1240. {
  1241. uint32_t tmp = 0U, tmp1 = 0U;
  1242. HAL_StatusTypeDef errorcode = HAL_OK;
  1243. /* Check Direction parameter */
  1244. assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
  1245. /* Process locked */
  1246. __HAL_LOCK(hspi);
  1247. tmp = hspi->State;
  1248. tmp1 = hspi->Init.Mode;
  1249. if (!((tmp == HAL_SPI_STATE_READY) || \
  1250. ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
  1251. {
  1252. errorcode = HAL_BUSY;
  1253. goto error;
  1254. }
  1255. if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
  1256. {
  1257. errorcode = HAL_ERROR;
  1258. goto error;
  1259. }
  1260. /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
  1261. if (hspi->State != HAL_SPI_STATE_BUSY_RX)
  1262. {
  1263. hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
  1264. }
  1265. /* Set the transaction information */
  1266. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  1267. hspi->pTxBuffPtr = (uint8_t *)pTxData;
  1268. hspi->TxXferSize = Size;
  1269. hspi->TxXferCount = Size;
  1270. hspi->pRxBuffPtr = (uint8_t *)pRxData;
  1271. hspi->RxXferSize = Size;
  1272. hspi->RxXferCount = Size;
  1273. /* Set the function for IT treatment */
  1274. if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  1275. {
  1276. hspi->RxISR = SPI_2linesRxISR_16BIT;
  1277. hspi->TxISR = SPI_2linesTxISR_16BIT;
  1278. }
  1279. else
  1280. {
  1281. hspi->RxISR = SPI_2linesRxISR_8BIT;
  1282. hspi->TxISR = SPI_2linesTxISR_8BIT;
  1283. }
  1284. #if (USE_SPI_CRC != 0U)
  1285. /* Reset CRC Calculation */
  1286. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1287. {
  1288. hspi->CRCSize = 1U;
  1289. if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
  1290. {
  1291. hspi->CRCSize = 2U;
  1292. }
  1293. SPI_RESET_CRC(hspi);
  1294. }
  1295. else
  1296. {
  1297. hspi->CRCSize = 0U;
  1298. }
  1299. #endif /* USE_SPI_CRC */
  1300. /* Check if packing mode is enabled and if there is more than 2 data to receive */
  1301. if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
  1302. {
  1303. /* Set RX Fifo threshold according the reception data length: 16 bit */
  1304. CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1305. }
  1306. else
  1307. {
  1308. /* Set RX Fifo threshold according the reception data length: 8 bit */
  1309. SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1310. }
  1311. /* Enable TXE, RXNE and ERR interrupt */
  1312. __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
  1313. /* Check if the SPI is already enabled */
  1314. if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  1315. {
  1316. /* Enable SPI peripheral */
  1317. __HAL_SPI_ENABLE(hspi);
  1318. }
  1319. error :
  1320. /* Process Unlocked */
  1321. __HAL_UNLOCK(hspi);
  1322. return errorcode;
  1323. }
  1324. /**
  1325. * @brief Transmit an amount of data in non-blocking mode with DMA.
  1326. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  1327. * the configuration information for SPI module.
  1328. * @param pData pointer to data buffer
  1329. * @param Size amount of data to be sent
  1330. * @retval HAL status
  1331. */
  1332. HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
  1333. {
  1334. HAL_StatusTypeDef errorcode = HAL_OK;
  1335. /* Check tx dma handle */
  1336. assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
  1337. /* Check Direction parameter */
  1338. assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
  1339. /* Process Locked */
  1340. __HAL_LOCK(hspi);
  1341. if (hspi->State != HAL_SPI_STATE_READY)
  1342. {
  1343. errorcode = HAL_BUSY;
  1344. goto error;
  1345. }
  1346. if ((pData == NULL) || (Size == 0U))
  1347. {
  1348. errorcode = HAL_ERROR;
  1349. goto error;
  1350. }
  1351. /* Set the transaction information */
  1352. hspi->State = HAL_SPI_STATE_BUSY_TX;
  1353. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  1354. hspi->pTxBuffPtr = (uint8_t *)pData;
  1355. hspi->TxXferSize = Size;
  1356. hspi->TxXferCount = Size;
  1357. /* Init field not used in handle to zero */
  1358. hspi->pRxBuffPtr = (uint8_t *)NULL;
  1359. hspi->TxISR = NULL;
  1360. hspi->RxISR = NULL;
  1361. hspi->RxXferSize = 0U;
  1362. hspi->RxXferCount = 0U;
  1363. /* Configure communication direction : 1Line */
  1364. if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
  1365. {
  1366. SPI_1LINE_TX(hspi);
  1367. }
  1368. #if (USE_SPI_CRC != 0U)
  1369. /* Reset CRC Calculation */
  1370. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1371. {
  1372. SPI_RESET_CRC(hspi);
  1373. }
  1374. #endif /* USE_SPI_CRC */
  1375. /* Set the SPI TxDMA Half transfer complete callback */
  1376. hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
  1377. /* Set the SPI TxDMA transfer complete callback */
  1378. hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
  1379. /* Set the DMA error callback */
  1380. hspi->hdmatx->XferErrorCallback = SPI_DMAError;
  1381. /* Set the DMA AbortCpltCallback */
  1382. hspi->hdmatx->XferAbortCallback = NULL;
  1383. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
  1384. /* Packing mode is enabled only if the DMA setting is HALWORD */
  1385. if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
  1386. {
  1387. /* Check the even/odd of the data size + crc if enabled */
  1388. if ((hspi->TxXferCount & 0x1U) == 0U)
  1389. {
  1390. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
  1391. hspi->TxXferCount = (hspi->TxXferCount >> 1U);
  1392. }
  1393. else
  1394. {
  1395. SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
  1396. hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
  1397. }
  1398. }
  1399. /* Enable the Tx DMA Stream/Channel */
  1400. HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
  1401. /* Check if the SPI is already enabled */
  1402. if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  1403. {
  1404. /* Enable SPI peripheral */
  1405. __HAL_SPI_ENABLE(hspi);
  1406. }
  1407. /* Enable the SPI Error Interrupt Bit */
  1408. __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
  1409. /* Enable Tx DMA Request */
  1410. SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
  1411. error :
  1412. /* Process Unlocked */
  1413. __HAL_UNLOCK(hspi);
  1414. return errorcode;
  1415. }
  1416. /**
  1417. * @brief Receive an amount of data in non-blocking mode with DMA.
  1418. * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
  1419. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  1420. * the configuration information for SPI module.
  1421. * @param pData pointer to data buffer
  1422. * @note When the CRC feature is enabled the pData Length must be Size + 1.
  1423. * @param Size amount of data to be sent
  1424. * @retval HAL status
  1425. */
  1426. HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
  1427. {
  1428. HAL_StatusTypeDef errorcode = HAL_OK;
  1429. /* Check rx dma handle */
  1430. assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
  1431. if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
  1432. {
  1433. hspi->State = HAL_SPI_STATE_BUSY_RX;
  1434. /* Check tx dma handle */
  1435. assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
  1436. /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
  1437. return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
  1438. }
  1439. /* Process Locked */
  1440. __HAL_LOCK(hspi);
  1441. if (hspi->State != HAL_SPI_STATE_READY)
  1442. {
  1443. errorcode = HAL_BUSY;
  1444. goto error;
  1445. }
  1446. if ((pData == NULL) || (Size == 0U))
  1447. {
  1448. errorcode = HAL_ERROR;
  1449. goto error;
  1450. }
  1451. /* Set the transaction information */
  1452. hspi->State = HAL_SPI_STATE_BUSY_RX;
  1453. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  1454. hspi->pRxBuffPtr = (uint8_t *)pData;
  1455. hspi->RxXferSize = Size;
  1456. hspi->RxXferCount = Size;
  1457. /*Init field not used in handle to zero */
  1458. hspi->RxISR = NULL;
  1459. hspi->TxISR = NULL;
  1460. hspi->TxXferSize = 0U;
  1461. hspi->TxXferCount = 0U;
  1462. /* Configure communication direction : 1Line */
  1463. if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
  1464. {
  1465. SPI_1LINE_RX(hspi);
  1466. }
  1467. #if (USE_SPI_CRC != 0U)
  1468. /* Reset CRC Calculation */
  1469. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1470. {
  1471. SPI_RESET_CRC(hspi);
  1472. }
  1473. #endif /* USE_SPI_CRC */
  1474. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
  1475. if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  1476. {
  1477. /* Set RX Fifo threshold according the reception data length: 16bit */
  1478. CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1479. }
  1480. else
  1481. {
  1482. /* Set RX Fifo threshold according the reception data length: 8bit */
  1483. SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1484. if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
  1485. {
  1486. /* Set RX Fifo threshold according the reception data length: 16bit */
  1487. CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1488. if ((hspi->RxXferCount & 0x1U) == 0x0U)
  1489. {
  1490. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
  1491. hspi->RxXferCount = hspi->RxXferCount >> 1U;
  1492. }
  1493. else
  1494. {
  1495. SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
  1496. hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
  1497. }
  1498. }
  1499. }
  1500. /* Set the SPI RxDMA Half transfer complete callback */
  1501. hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
  1502. /* Set the SPI Rx DMA transfer complete callback */
  1503. hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
  1504. /* Set the DMA error callback */
  1505. hspi->hdmarx->XferErrorCallback = SPI_DMAError;
  1506. /* Set the DMA AbortCpltCallback */
  1507. hspi->hdmarx->XferAbortCallback = NULL;
  1508. /* Enable the Rx DMA Stream/Channel */
  1509. HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
  1510. /* Check if the SPI is already enabled */
  1511. if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  1512. {
  1513. /* Enable SPI peripheral */
  1514. __HAL_SPI_ENABLE(hspi);
  1515. }
  1516. /* Enable the SPI Error Interrupt Bit */
  1517. __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
  1518. /* Enable Rx DMA Request */
  1519. SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
  1520. error:
  1521. /* Process Unlocked */
  1522. __HAL_UNLOCK(hspi);
  1523. return errorcode;
  1524. }
  1525. /**
  1526. * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
  1527. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  1528. * the configuration information for SPI module.
  1529. * @param pTxData pointer to transmission data buffer
  1530. * @param pRxData pointer to reception data buffer
  1531. * @note When the CRC feature is enabled the pRxData Length must be Size + 1
  1532. * @param Size amount of data to be sent
  1533. * @retval HAL status
  1534. */
  1535. HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
  1536. uint16_t Size)
  1537. {
  1538. uint32_t tmp = 0U, tmp1 = 0U;
  1539. HAL_StatusTypeDef errorcode = HAL_OK;
  1540. /* Check rx & tx dma handles */
  1541. assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
  1542. assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
  1543. /* Check Direction parameter */
  1544. assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
  1545. /* Process locked */
  1546. __HAL_LOCK(hspi);
  1547. tmp = hspi->State;
  1548. tmp1 = hspi->Init.Mode;
  1549. if (!((tmp == HAL_SPI_STATE_READY) ||
  1550. ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
  1551. {
  1552. errorcode = HAL_BUSY;
  1553. goto error;
  1554. }
  1555. if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
  1556. {
  1557. errorcode = HAL_ERROR;
  1558. goto error;
  1559. }
  1560. /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
  1561. if (hspi->State != HAL_SPI_STATE_BUSY_RX)
  1562. {
  1563. hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
  1564. }
  1565. /* Set the transaction information */
  1566. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  1567. hspi->pTxBuffPtr = (uint8_t *)pTxData;
  1568. hspi->TxXferSize = Size;
  1569. hspi->TxXferCount = Size;
  1570. hspi->pRxBuffPtr = (uint8_t *)pRxData;
  1571. hspi->RxXferSize = Size;
  1572. hspi->RxXferCount = Size;
  1573. /* Init field not used in handle to zero */
  1574. hspi->RxISR = NULL;
  1575. hspi->TxISR = NULL;
  1576. #if (USE_SPI_CRC != 0U)
  1577. /* Reset CRC Calculation */
  1578. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1579. {
  1580. SPI_RESET_CRC(hspi);
  1581. }
  1582. #endif /* USE_SPI_CRC */
  1583. /* Reset the threshold bit */
  1584. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
  1585. /* The packing mode management is enabled by the DMA settings according the spi data size */
  1586. if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  1587. {
  1588. /* Set fiforxthreshold according the reception data length: 16bit */
  1589. CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1590. }
  1591. else
  1592. {
  1593. /* Set RX Fifo threshold according the reception data length: 8bit */
  1594. SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1595. if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
  1596. {
  1597. if ((hspi->TxXferSize & 0x1U) == 0x0U)
  1598. {
  1599. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
  1600. hspi->TxXferCount = hspi->TxXferCount >> 1U;
  1601. }
  1602. else
  1603. {
  1604. SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
  1605. hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
  1606. }
  1607. }
  1608. if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
  1609. {
  1610. /* Set RX Fifo threshold according the reception data length: 16bit */
  1611. CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1612. if ((hspi->RxXferCount & 0x1U) == 0x0U)
  1613. {
  1614. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
  1615. hspi->RxXferCount = hspi->RxXferCount >> 1U;
  1616. }
  1617. else
  1618. {
  1619. SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
  1620. hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
  1621. }
  1622. }
  1623. }
  1624. /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
  1625. if (hspi->State == HAL_SPI_STATE_BUSY_RX)
  1626. {
  1627. /* Set the SPI Rx DMA Half transfer complete callback */
  1628. hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
  1629. hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
  1630. }
  1631. else
  1632. {
  1633. /* Set the SPI Tx/Rx DMA Half transfer complete callback */
  1634. hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
  1635. hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
  1636. }
  1637. /* Set the DMA error callback */
  1638. hspi->hdmarx->XferErrorCallback = SPI_DMAError;
  1639. /* Set the DMA AbortCpltCallback */
  1640. hspi->hdmarx->XferAbortCallback = NULL;
  1641. /* Enable the Rx DMA Stream/Channel */
  1642. HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
  1643. /* Enable Rx DMA Request */
  1644. SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
  1645. /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
  1646. is performed in DMA reception complete callback */
  1647. hspi->hdmatx->XferHalfCpltCallback = NULL;
  1648. hspi->hdmatx->XferCpltCallback = NULL;
  1649. hspi->hdmatx->XferErrorCallback = NULL;
  1650. hspi->hdmatx->XferAbortCallback = NULL;
  1651. /* Enable the Tx DMA Stream/Channel */
  1652. HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
  1653. /* Check if the SPI is already enabled */
  1654. if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  1655. {
  1656. /* Enable SPI peripheral */
  1657. __HAL_SPI_ENABLE(hspi);
  1658. }
  1659. /* Enable the SPI Error Interrupt Bit */
  1660. __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
  1661. /* Enable Tx DMA Request */
  1662. SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
  1663. error :
  1664. /* Process Unlocked */
  1665. __HAL_UNLOCK(hspi);
  1666. return errorcode;
  1667. }
  1668. /**
  1669. * @brief Abort ongoing transfer (blocking mode).
  1670. * @param hspi SPI handle.
  1671. * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
  1672. * started in Interrupt or DMA mode.
  1673. * This procedure performs following operations :
  1674. * - Disable SPI Interrupts (depending of transfer direction)
  1675. * - Disable the DMA transfer in the peripheral register (if enabled)
  1676. * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  1677. * - Set handle State to READY
  1678. * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
  1679. * @retval HAL status
  1680. */
  1681. HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
  1682. {
  1683. HAL_StatusTypeDef errorcode;
  1684. __IO uint32_t count, resetcount;
  1685. /* Initialized local variable */
  1686. errorcode = HAL_OK;
  1687. resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
  1688. count = resetcount;
  1689. /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
  1690. if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
  1691. {
  1692. hspi->TxISR = SPI_AbortTx_ISR;
  1693. /* Wait HAL_SPI_STATE_ABORT state */
  1694. do
  1695. {
  1696. if (count-- == 0U)
  1697. {
  1698. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  1699. break;
  1700. }
  1701. }
  1702. while (hspi->State != HAL_SPI_STATE_ABORT);
  1703. /* Reset Timeout Counter */
  1704. count = resetcount;
  1705. }
  1706. if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
  1707. {
  1708. hspi->RxISR = SPI_AbortRx_ISR;
  1709. /* Wait HAL_SPI_STATE_ABORT state */
  1710. do
  1711. {
  1712. if (count-- == 0U)
  1713. {
  1714. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  1715. break;
  1716. }
  1717. }
  1718. while (hspi->State != HAL_SPI_STATE_ABORT);
  1719. /* Reset Timeout Counter */
  1720. count = resetcount;
  1721. }
  1722. /* Clear ERRIE interrupts in case of DMA Mode */
  1723. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
  1724. /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
  1725. if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
  1726. {
  1727. /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
  1728. if (hspi->hdmatx != NULL)
  1729. {
  1730. /* Set the SPI DMA Abort callback :
  1731. will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
  1732. hspi->hdmatx->XferAbortCallback = NULL;
  1733. /* Abort DMA Tx Handle linked to SPI Peripheral */
  1734. if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
  1735. {
  1736. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  1737. }
  1738. /* Disable Tx DMA Request */
  1739. CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
  1740. if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  1741. {
  1742. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  1743. }
  1744. /* Disable SPI Peripheral */
  1745. __HAL_SPI_DISABLE(hspi);
  1746. /* Empty the FRLVL fifo */
  1747. if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  1748. {
  1749. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  1750. }
  1751. }
  1752. /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
  1753. if (hspi->hdmarx != NULL)
  1754. {
  1755. /* Set the SPI DMA Abort callback :
  1756. will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
  1757. hspi->hdmarx->XferAbortCallback = NULL;
  1758. /* Abort DMA Rx Handle linked to SPI Peripheral */
  1759. if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
  1760. {
  1761. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  1762. }
  1763. /* Disable peripheral */
  1764. __HAL_SPI_DISABLE(hspi);
  1765. /* Control the BSY flag */
  1766. if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  1767. {
  1768. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  1769. }
  1770. /* Empty the FRLVL fifo */
  1771. if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  1772. {
  1773. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  1774. }
  1775. /* Disable Rx DMA Request */
  1776. CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
  1777. }
  1778. }
  1779. /* Reset Tx and Rx transfer counters */
  1780. hspi->RxXferCount = 0U;
  1781. hspi->TxXferCount = 0U;
  1782. /* Check error during Abort procedure */
  1783. if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
  1784. {
  1785. /* return HAL_Error in case of error during Abort procedure */
  1786. errorcode = HAL_ERROR;
  1787. }
  1788. else
  1789. {
  1790. /* Reset errorCode */
  1791. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  1792. }
  1793. /* Clear the Error flags in the SR register */
  1794. __HAL_SPI_CLEAR_OVRFLAG(hspi);
  1795. __HAL_SPI_CLEAR_FREFLAG(hspi);
  1796. /* Restore hspi->state to ready */
  1797. hspi->State = HAL_SPI_STATE_READY;
  1798. return errorcode;
  1799. }
  1800. /**
  1801. * @brief Abort ongoing transfer (Interrupt mode).
  1802. * @param hspi SPI handle.
  1803. * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
  1804. * started in Interrupt or DMA mode.
  1805. * This procedure performs following operations :
  1806. * - Disable SPI Interrupts (depending of transfer direction)
  1807. * - Disable the DMA transfer in the peripheral register (if enabled)
  1808. * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  1809. * - Set handle State to READY
  1810. * - At abort completion, call user abort complete callback
  1811. * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
  1812. * considered as completed only when user abort complete callback is executed (not when exiting function).
  1813. * @retval HAL status
  1814. */
  1815. HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
  1816. {
  1817. HAL_StatusTypeDef errorcode;
  1818. uint32_t abortcplt ;
  1819. __IO uint32_t count, resetcount;
  1820. /* Initialized local variable */
  1821. errorcode = HAL_OK;
  1822. abortcplt = 1U;
  1823. resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
  1824. count = resetcount;
  1825. /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
  1826. if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
  1827. {
  1828. hspi->TxISR = SPI_AbortTx_ISR;
  1829. /* Wait HAL_SPI_STATE_ABORT state */
  1830. do
  1831. {
  1832. if (count-- == 0U)
  1833. {
  1834. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  1835. break;
  1836. }
  1837. }
  1838. while (hspi->State != HAL_SPI_STATE_ABORT);
  1839. /* Reset Timeout Counter */
  1840. count = resetcount;
  1841. }
  1842. if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
  1843. {
  1844. hspi->RxISR = SPI_AbortRx_ISR;
  1845. /* Wait HAL_SPI_STATE_ABORT state */
  1846. do
  1847. {
  1848. if (count-- == 0U)
  1849. {
  1850. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  1851. break;
  1852. }
  1853. }
  1854. while (hspi->State != HAL_SPI_STATE_ABORT);
  1855. /* Reset Timeout Counter */
  1856. count = resetcount;
  1857. }
  1858. /* Clear ERRIE interrupts in case of DMA Mode */
  1859. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
  1860. /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
  1861. before any call to DMA Abort functions */
  1862. /* DMA Tx Handle is valid */
  1863. if (hspi->hdmatx != NULL)
  1864. {
  1865. /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
  1866. Otherwise, set it to NULL */
  1867. if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
  1868. {
  1869. hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
  1870. }
  1871. else
  1872. {
  1873. hspi->hdmatx->XferAbortCallback = NULL;
  1874. }
  1875. }
  1876. /* DMA Rx Handle is valid */
  1877. if (hspi->hdmarx != NULL)
  1878. {
  1879. /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
  1880. Otherwise, set it to NULL */
  1881. if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
  1882. {
  1883. hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
  1884. }
  1885. else
  1886. {
  1887. hspi->hdmarx->XferAbortCallback = NULL;
  1888. }
  1889. }
  1890. /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
  1891. if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
  1892. {
  1893. /* Abort the SPI DMA Tx Stream/Channel */
  1894. if (hspi->hdmatx != NULL)
  1895. {
  1896. /* Abort DMA Tx Handle linked to SPI Peripheral */
  1897. if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
  1898. {
  1899. hspi->hdmatx->XferAbortCallback = NULL;
  1900. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  1901. }
  1902. else
  1903. {
  1904. abortcplt = 0U;
  1905. }
  1906. }
  1907. /* Abort the SPI DMA Rx Stream/Channel */
  1908. if (hspi->hdmarx != NULL)
  1909. {
  1910. /* Abort DMA Rx Handle linked to SPI Peripheral */
  1911. if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
  1912. {
  1913. hspi->hdmarx->XferAbortCallback = NULL;
  1914. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  1915. abortcplt = 1U;
  1916. }
  1917. else
  1918. {
  1919. abortcplt = 0U;
  1920. }
  1921. }
  1922. }
  1923. /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
  1924. if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
  1925. {
  1926. /* Abort the SPI DMA Tx Stream/Channel */
  1927. if (hspi->hdmatx != NULL)
  1928. {
  1929. /* Abort DMA Tx Handle linked to SPI Peripheral */
  1930. if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
  1931. {
  1932. hspi->hdmatx->XferAbortCallback = NULL;
  1933. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  1934. }
  1935. else
  1936. {
  1937. abortcplt = 0U;
  1938. }
  1939. }
  1940. }
  1941. /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
  1942. if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
  1943. {
  1944. /* Abort the SPI DMA Rx Stream/Channel */
  1945. if (hspi->hdmarx != NULL)
  1946. {
  1947. /* Abort DMA Rx Handle linked to SPI Peripheral */
  1948. if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
  1949. {
  1950. hspi->hdmarx->XferAbortCallback = NULL;
  1951. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  1952. }
  1953. else
  1954. {
  1955. abortcplt = 0U;
  1956. }
  1957. }
  1958. }
  1959. if (abortcplt == 1U)
  1960. {
  1961. /* Reset Tx and Rx transfer counters */
  1962. hspi->RxXferCount = 0U;
  1963. hspi->TxXferCount = 0U;
  1964. /* Check error during Abort procedure */
  1965. if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
  1966. {
  1967. /* return HAL_Error in case of error during Abort procedure */
  1968. errorcode = HAL_ERROR;
  1969. }
  1970. else
  1971. {
  1972. /* Reset errorCode */
  1973. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  1974. }
  1975. /* Clear the Error flags in the SR register */
  1976. __HAL_SPI_CLEAR_OVRFLAG(hspi);
  1977. __HAL_SPI_CLEAR_FREFLAG(hspi);
  1978. /* Restore hspi->State to Ready */
  1979. hspi->State = HAL_SPI_STATE_READY;
  1980. /* As no DMA to be aborted, call directly user Abort complete callback */
  1981. HAL_SPI_AbortCpltCallback(hspi);
  1982. }
  1983. return errorcode;
  1984. }
  1985. /**
  1986. * @brief Pause the DMA Transfer.
  1987. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  1988. * the configuration information for the specified SPI module.
  1989. * @retval HAL status
  1990. */
  1991. HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
  1992. {
  1993. /* Process Locked */
  1994. __HAL_LOCK(hspi);
  1995. /* Disable the SPI DMA Tx & Rx requests */
  1996. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
  1997. /* Process Unlocked */
  1998. __HAL_UNLOCK(hspi);
  1999. return HAL_OK;
  2000. }
  2001. /**
  2002. * @brief Resume the DMA Transfer.
  2003. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2004. * the configuration information for the specified SPI module.
  2005. * @retval HAL status
  2006. */
  2007. HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
  2008. {
  2009. /* Process Locked */
  2010. __HAL_LOCK(hspi);
  2011. /* Enable the SPI DMA Tx & Rx requests */
  2012. SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
  2013. /* Process Unlocked */
  2014. __HAL_UNLOCK(hspi);
  2015. return HAL_OK;
  2016. }
  2017. /**
  2018. * @brief Stop the DMA Transfer.
  2019. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2020. * the configuration information for the specified SPI module.
  2021. * @retval HAL status
  2022. */
  2023. HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
  2024. {
  2025. /* The Lock is not implemented on this API to allow the user application
  2026. to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
  2027. when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
  2028. and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
  2029. */
  2030. /* Abort the SPI DMA tx Stream/Channel */
  2031. if (hspi->hdmatx != NULL)
  2032. {
  2033. HAL_DMA_Abort(hspi->hdmatx);
  2034. }
  2035. /* Abort the SPI DMA rx Stream/Channel */
  2036. if (hspi->hdmarx != NULL)
  2037. {
  2038. HAL_DMA_Abort(hspi->hdmarx);
  2039. }
  2040. /* Disable the SPI DMA Tx & Rx requests */
  2041. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
  2042. hspi->State = HAL_SPI_STATE_READY;
  2043. return HAL_OK;
  2044. }
  2045. /**
  2046. * @brief Handle SPI interrupt request.
  2047. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2048. * the configuration information for the specified SPI module.
  2049. * @retval None
  2050. */
  2051. void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
  2052. {
  2053. uint32_t itsource = hspi->Instance->CR2;
  2054. uint32_t itflag = hspi->Instance->SR;
  2055. /* SPI in mode Receiver ----------------------------------------------------*/
  2056. if (((itflag & SPI_FLAG_OVR) == RESET) &&
  2057. ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
  2058. {
  2059. hspi->RxISR(hspi);
  2060. return;
  2061. }
  2062. /* SPI in mode Transmitter -------------------------------------------------*/
  2063. if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
  2064. {
  2065. hspi->TxISR(hspi);
  2066. return;
  2067. }
  2068. /* SPI in Error Treatment --------------------------------------------------*/
  2069. if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
  2070. {
  2071. /* SPI Overrun error interrupt occurred ----------------------------------*/
  2072. if ((itflag & SPI_FLAG_OVR) != RESET)
  2073. {
  2074. if (hspi->State != HAL_SPI_STATE_BUSY_TX)
  2075. {
  2076. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
  2077. __HAL_SPI_CLEAR_OVRFLAG(hspi);
  2078. }
  2079. else
  2080. {
  2081. __HAL_SPI_CLEAR_OVRFLAG(hspi);
  2082. return;
  2083. }
  2084. }
  2085. /* SPI Mode Fault error interrupt occurred -------------------------------*/
  2086. if ((itflag & SPI_FLAG_MODF) != RESET)
  2087. {
  2088. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
  2089. __HAL_SPI_CLEAR_MODFFLAG(hspi);
  2090. }
  2091. /* SPI Frame error interrupt occurred ------------------------------------*/
  2092. if ((itflag & SPI_FLAG_FRE) != RESET)
  2093. {
  2094. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
  2095. __HAL_SPI_CLEAR_FREFLAG(hspi);
  2096. }
  2097. if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  2098. {
  2099. /* Disable all interrupts */
  2100. __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
  2101. hspi->State = HAL_SPI_STATE_READY;
  2102. /* Disable the SPI DMA requests if enabled */
  2103. if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
  2104. {
  2105. CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
  2106. /* Abort the SPI DMA Rx channel */
  2107. if (hspi->hdmarx != NULL)
  2108. {
  2109. /* Set the SPI DMA Abort callback :
  2110. will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
  2111. hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
  2112. HAL_DMA_Abort_IT(hspi->hdmarx);
  2113. }
  2114. /* Abort the SPI DMA Tx channel */
  2115. if (hspi->hdmatx != NULL)
  2116. {
  2117. /* Set the SPI DMA Abort callback :
  2118. will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
  2119. hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
  2120. HAL_DMA_Abort_IT(hspi->hdmatx);
  2121. }
  2122. }
  2123. else
  2124. {
  2125. /* Call user error callback */
  2126. HAL_SPI_ErrorCallback(hspi);
  2127. }
  2128. }
  2129. return;
  2130. }
  2131. }
  2132. /**
  2133. * @brief Tx Transfer completed callback.
  2134. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2135. * the configuration information for SPI module.
  2136. * @retval None
  2137. */
  2138. __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
  2139. {
  2140. /* Prevent unused argument(s) compilation warning */
  2141. UNUSED(hspi);
  2142. /* NOTE : This function should not be modified, when the callback is needed,
  2143. the HAL_SPI_TxCpltCallback should be implemented in the user file
  2144. */
  2145. }
  2146. /**
  2147. * @brief Rx Transfer completed callback.
  2148. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2149. * the configuration information for SPI module.
  2150. * @retval None
  2151. */
  2152. __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
  2153. {
  2154. /* Prevent unused argument(s) compilation warning */
  2155. UNUSED(hspi);
  2156. /* NOTE : This function should not be modified, when the callback is needed,
  2157. the HAL_SPI_RxCpltCallback should be implemented in the user file
  2158. */
  2159. }
  2160. /**
  2161. * @brief Tx and Rx Transfer completed callback.
  2162. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2163. * the configuration information for SPI module.
  2164. * @retval None
  2165. */
  2166. __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
  2167. {
  2168. /* Prevent unused argument(s) compilation warning */
  2169. UNUSED(hspi);
  2170. /* NOTE : This function should not be modified, when the callback is needed,
  2171. the HAL_SPI_TxRxCpltCallback should be implemented in the user file
  2172. */
  2173. }
  2174. /**
  2175. * @brief Tx Half Transfer completed callback.
  2176. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2177. * the configuration information for SPI module.
  2178. * @retval None
  2179. */
  2180. __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
  2181. {
  2182. /* Prevent unused argument(s) compilation warning */
  2183. UNUSED(hspi);
  2184. /* NOTE : This function should not be modified, when the callback is needed,
  2185. the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
  2186. */
  2187. }
  2188. /**
  2189. * @brief Rx Half Transfer completed callback.
  2190. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2191. * the configuration information for SPI module.
  2192. * @retval None
  2193. */
  2194. __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
  2195. {
  2196. /* Prevent unused argument(s) compilation warning */
  2197. UNUSED(hspi);
  2198. /* NOTE : This function should not be modified, when the callback is needed,
  2199. the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
  2200. */
  2201. }
  2202. /**
  2203. * @brief Tx and Rx Half Transfer callback.
  2204. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2205. * the configuration information for SPI module.
  2206. * @retval None
  2207. */
  2208. __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
  2209. {
  2210. /* Prevent unused argument(s) compilation warning */
  2211. UNUSED(hspi);
  2212. /* NOTE : This function should not be modified, when the callback is needed,
  2213. the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
  2214. */
  2215. }
  2216. /**
  2217. * @brief SPI error callback.
  2218. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2219. * the configuration information for SPI module.
  2220. * @retval None
  2221. */
  2222. __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
  2223. {
  2224. /* Prevent unused argument(s) compilation warning */
  2225. UNUSED(hspi);
  2226. /* NOTE : This function should not be modified, when the callback is needed,
  2227. the HAL_SPI_ErrorCallback should be implemented in the user file
  2228. */
  2229. /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
  2230. and user can use HAL_SPI_GetError() API to check the latest error occurred
  2231. */
  2232. }
  2233. /**
  2234. * @brief SPI Abort Complete callback.
  2235. * @param hspi SPI handle.
  2236. * @retval None
  2237. */
  2238. __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
  2239. {
  2240. /* Prevent unused argument(s) compilation warning */
  2241. UNUSED(hspi);
  2242. /* NOTE : This function should not be modified, when the callback is needed,
  2243. the HAL_SPI_AbortCpltCallback can be implemented in the user file.
  2244. */
  2245. }
  2246. /**
  2247. * @}
  2248. */
  2249. /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
  2250. * @brief SPI control functions
  2251. *
  2252. @verbatim
  2253. ===============================================================================
  2254. ##### Peripheral State and Errors functions #####
  2255. ===============================================================================
  2256. [..]
  2257. This subsection provides a set of functions allowing to control the SPI.
  2258. (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
  2259. (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
  2260. @endverbatim
  2261. * @{
  2262. */
  2263. /**
  2264. * @brief Return the SPI handle state.
  2265. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2266. * the configuration information for SPI module.
  2267. * @retval SPI state
  2268. */
  2269. HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
  2270. {
  2271. /* Return SPI handle state */
  2272. return hspi->State;
  2273. }
  2274. /**
  2275. * @brief Return the SPI error code.
  2276. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2277. * the configuration information for SPI module.
  2278. * @retval SPI error code in bitmap format
  2279. */
  2280. uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
  2281. {
  2282. /* Return SPI ErrorCode */
  2283. return hspi->ErrorCode;
  2284. }
  2285. /**
  2286. * @}
  2287. */
  2288. /**
  2289. * @}
  2290. */
  2291. /** @addtogroup SPI_Private_Functions
  2292. * @brief Private functions
  2293. * @{
  2294. */
  2295. /**
  2296. * @brief DMA SPI transmit process complete callback.
  2297. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  2298. * the configuration information for the specified DMA module.
  2299. * @retval None
  2300. */
  2301. static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
  2302. {
  2303. SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2304. uint32_t tickstart = 0U;
  2305. /* Init tickstart for timeout managment*/
  2306. tickstart = HAL_GetTick();
  2307. /* DMA Normal Mode */
  2308. if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
  2309. {
  2310. /* Disable ERR interrupt */
  2311. __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
  2312. /* Disable Tx DMA Request */
  2313. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
  2314. /* Check the end of the transaction */
  2315. if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  2316. {
  2317. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  2318. }
  2319. /* Clear overrun flag in 2 Lines communication mode because received data is not read */
  2320. if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
  2321. {
  2322. __HAL_SPI_CLEAR_OVRFLAG(hspi);
  2323. }
  2324. hspi->TxXferCount = 0U;
  2325. hspi->State = HAL_SPI_STATE_READY;
  2326. if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  2327. {
  2328. HAL_SPI_ErrorCallback(hspi);
  2329. return;
  2330. }
  2331. }
  2332. HAL_SPI_TxCpltCallback(hspi);
  2333. }
  2334. /**
  2335. * @brief DMA SPI receive process complete callback.
  2336. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  2337. * the configuration information for the specified DMA module.
  2338. * @retval None
  2339. */
  2340. static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
  2341. {
  2342. SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2343. uint32_t tickstart = 0U;
  2344. #if (USE_SPI_CRC != 0U)
  2345. __IO uint16_t tmpreg = 0U;
  2346. #endif /* USE_SPI_CRC */
  2347. /* Init tickstart for timeout management*/
  2348. tickstart = HAL_GetTick();
  2349. /* DMA Normal Mode */
  2350. if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
  2351. {
  2352. /* Disable ERR interrupt */
  2353. __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
  2354. #if (USE_SPI_CRC != 0U)
  2355. /* CRC handling */
  2356. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  2357. {
  2358. /* Wait until RXNE flag */
  2359. if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  2360. {
  2361. /* Error on the CRC reception */
  2362. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  2363. }
  2364. /* Read CRC */
  2365. if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  2366. {
  2367. tmpreg = hspi->Instance->DR;
  2368. /* To avoid GCC warning */
  2369. UNUSED(tmpreg);
  2370. }
  2371. else
  2372. {
  2373. tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
  2374. /* To avoid GCC warning */
  2375. UNUSED(tmpreg);
  2376. if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
  2377. {
  2378. if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  2379. {
  2380. /* Error on the CRC reception */
  2381. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  2382. }
  2383. tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
  2384. /* To avoid GCC warning */
  2385. UNUSED(tmpreg);
  2386. }
  2387. }
  2388. }
  2389. #endif /* USE_SPI_CRC */
  2390. /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
  2391. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
  2392. /* Check the end of the transaction */
  2393. if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  2394. {
  2395. hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
  2396. }
  2397. hspi->RxXferCount = 0U;
  2398. hspi->State = HAL_SPI_STATE_READY;
  2399. #if (USE_SPI_CRC != 0U)
  2400. /* Check if CRC error occurred */
  2401. if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
  2402. {
  2403. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  2404. __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
  2405. }
  2406. #endif /* USE_SPI_CRC */
  2407. if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  2408. {
  2409. HAL_SPI_ErrorCallback(hspi);
  2410. return;
  2411. }
  2412. }
  2413. HAL_SPI_RxCpltCallback(hspi);
  2414. }
  2415. /**
  2416. * @brief DMA SPI transmit receive process complete callback.
  2417. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  2418. * the configuration information for the specified DMA module.
  2419. * @retval None
  2420. */
  2421. static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
  2422. {
  2423. SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2424. uint32_t tickstart = 0U;
  2425. #if (USE_SPI_CRC != 0U)
  2426. __IO int16_t tmpreg = 0U;
  2427. #endif /* USE_SPI_CRC */
  2428. /* Init tickstart for timeout management*/
  2429. tickstart = HAL_GetTick();
  2430. /* DMA Normal Mode */
  2431. if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
  2432. {
  2433. /* Disable ERR interrupt */
  2434. __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
  2435. #if (USE_SPI_CRC != 0U)
  2436. /* CRC handling */
  2437. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  2438. {
  2439. if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
  2440. {
  2441. if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
  2442. tickstart) != HAL_OK)
  2443. {
  2444. /* Error on the CRC reception */
  2445. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  2446. }
  2447. /* Read CRC to Flush DR and RXNE flag */
  2448. tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
  2449. /* To avoid GCC warning */
  2450. UNUSED(tmpreg);
  2451. }
  2452. else
  2453. {
  2454. if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  2455. {
  2456. /* Error on the CRC reception */
  2457. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  2458. }
  2459. /* Read CRC to Flush DR and RXNE flag */
  2460. tmpreg = hspi->Instance->DR;
  2461. /* To avoid GCC warning */
  2462. UNUSED(tmpreg);
  2463. }
  2464. }
  2465. #endif /* USE_SPI_CRC */
  2466. /* Check the end of the transaction */
  2467. if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  2468. {
  2469. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  2470. }
  2471. /* Disable Rx/Tx DMA Request */
  2472. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
  2473. hspi->TxXferCount = 0U;
  2474. hspi->RxXferCount = 0U;
  2475. hspi->State = HAL_SPI_STATE_READY;
  2476. #if (USE_SPI_CRC != 0U)
  2477. /* Check if CRC error occurred */
  2478. if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
  2479. {
  2480. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  2481. __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
  2482. }
  2483. #endif /* USE_SPI_CRC */
  2484. if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  2485. {
  2486. HAL_SPI_ErrorCallback(hspi);
  2487. return;
  2488. }
  2489. }
  2490. HAL_SPI_TxRxCpltCallback(hspi);
  2491. }
  2492. /**
  2493. * @brief DMA SPI half transmit process complete callback.
  2494. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  2495. * the configuration information for the specified DMA module.
  2496. * @retval None
  2497. */
  2498. static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
  2499. {
  2500. SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2501. HAL_SPI_TxHalfCpltCallback(hspi);
  2502. }
  2503. /**
  2504. * @brief DMA SPI half receive process complete callback
  2505. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  2506. * the configuration information for the specified DMA module.
  2507. * @retval None
  2508. */
  2509. static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
  2510. {
  2511. SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2512. HAL_SPI_RxHalfCpltCallback(hspi);
  2513. }
  2514. /**
  2515. * @brief DMA SPI half transmit receive process complete callback.
  2516. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  2517. * the configuration information for the specified DMA module.
  2518. * @retval None
  2519. */
  2520. static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
  2521. {
  2522. SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2523. HAL_SPI_TxRxHalfCpltCallback(hspi);
  2524. }
  2525. /**
  2526. * @brief DMA SPI communication error callback.
  2527. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  2528. * the configuration information for the specified DMA module.
  2529. * @retval None
  2530. */
  2531. static void SPI_DMAError(DMA_HandleTypeDef *hdma)
  2532. {
  2533. SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2534. /* Stop the disable DMA transfer on SPI side */
  2535. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
  2536. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
  2537. hspi->State = HAL_SPI_STATE_READY;
  2538. HAL_SPI_ErrorCallback(hspi);
  2539. }
  2540. /**
  2541. * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
  2542. * (To be called at end of DMA Abort procedure following error occurrence).
  2543. * @param hdma DMA handle.
  2544. * @retval None
  2545. */
  2546. static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
  2547. {
  2548. SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2549. hspi->RxXferCount = 0U;
  2550. hspi->TxXferCount = 0U;
  2551. HAL_SPI_ErrorCallback(hspi);
  2552. }
  2553. /**
  2554. * @brief DMA SPI Tx communication abort callback, when initiated by user
  2555. * (To be called at end of DMA Tx Abort procedure following user abort request).
  2556. * @note When this callback is executed, User Abort complete call back is called only if no
  2557. * Abort still ongoing for Rx DMA Handle.
  2558. * @param hdma DMA handle.
  2559. * @retval None
  2560. */
  2561. static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
  2562. {
  2563. SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2564. hspi->hdmatx->XferAbortCallback = NULL;
  2565. /* Disable Tx DMA Request */
  2566. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
  2567. if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  2568. {
  2569. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  2570. }
  2571. /* Disable SPI Peripheral */
  2572. __HAL_SPI_DISABLE(hspi);
  2573. /* Empty the FRLVL fifo */
  2574. if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  2575. {
  2576. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  2577. }
  2578. /* Check if an Abort process is still ongoing */
  2579. if (hspi->hdmarx != NULL)
  2580. {
  2581. if (hspi->hdmarx->XferAbortCallback != NULL)
  2582. {
  2583. return;
  2584. }
  2585. }
  2586. /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
  2587. hspi->RxXferCount = 0U;
  2588. hspi->TxXferCount = 0U;
  2589. /* Check no error during Abort procedure */
  2590. if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
  2591. {
  2592. /* Reset errorCode */
  2593. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  2594. }
  2595. /* Clear the Error flags in the SR register */
  2596. __HAL_SPI_CLEAR_OVRFLAG(hspi);
  2597. __HAL_SPI_CLEAR_FREFLAG(hspi);
  2598. /* Restore hspi->State to Ready */
  2599. hspi->State = HAL_SPI_STATE_READY;
  2600. /* Call user Abort complete callback */
  2601. HAL_SPI_AbortCpltCallback(hspi);
  2602. }
  2603. /**
  2604. * @brief DMA SPI Rx communication abort callback, when initiated by user
  2605. * (To be called at end of DMA Rx Abort procedure following user abort request).
  2606. * @note When this callback is executed, User Abort complete call back is called only if no
  2607. * Abort still ongoing for Tx DMA Handle.
  2608. * @param hdma DMA handle.
  2609. * @retval None
  2610. */
  2611. static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
  2612. {
  2613. SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2614. /* Disable SPI Peripheral */
  2615. __HAL_SPI_DISABLE(hspi);
  2616. hspi->hdmarx->XferAbortCallback = NULL;
  2617. /* Disable Rx DMA Request */
  2618. CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
  2619. /* Control the BSY flag */
  2620. if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  2621. {
  2622. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  2623. }
  2624. /* Empty the FRLVL fifo */
  2625. if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  2626. {
  2627. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  2628. }
  2629. /* Check if an Abort process is still ongoing */
  2630. if (hspi->hdmatx != NULL)
  2631. {
  2632. if (hspi->hdmatx->XferAbortCallback != NULL)
  2633. {
  2634. return;
  2635. }
  2636. }
  2637. /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
  2638. hspi->RxXferCount = 0U;
  2639. hspi->TxXferCount = 0U;
  2640. /* Check no error during Abort procedure */
  2641. if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
  2642. {
  2643. /* Reset errorCode */
  2644. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  2645. }
  2646. /* Clear the Error flags in the SR register */
  2647. __HAL_SPI_CLEAR_OVRFLAG(hspi);
  2648. __HAL_SPI_CLEAR_FREFLAG(hspi);
  2649. /* Restore hspi->State to Ready */
  2650. hspi->State = HAL_SPI_STATE_READY;
  2651. /* Call user Abort complete callback */
  2652. HAL_SPI_AbortCpltCallback(hspi);
  2653. }
  2654. /**
  2655. * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
  2656. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2657. * the configuration information for SPI module.
  2658. * @retval None
  2659. */
  2660. static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
  2661. {
  2662. /* Receive data in packing mode */
  2663. if (hspi->RxXferCount > 1U)
  2664. {
  2665. *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
  2666. hspi->pRxBuffPtr += sizeof(uint16_t);
  2667. hspi->RxXferCount -= 2U;
  2668. if (hspi->RxXferCount == 1U)
  2669. {
  2670. /* Set RX Fifo threshold according the reception data length: 8bit */
  2671. SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  2672. }
  2673. }
  2674. /* Receive data in 8 Bit mode */
  2675. else
  2676. {
  2677. *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
  2678. hspi->RxXferCount--;
  2679. }
  2680. /* Check end of the reception */
  2681. if (hspi->RxXferCount == 0U)
  2682. {
  2683. #if (USE_SPI_CRC != 0U)
  2684. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  2685. {
  2686. SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  2687. hspi->RxISR = SPI_2linesRxISR_8BITCRC;
  2688. return;
  2689. }
  2690. #endif /* USE_SPI_CRC */
  2691. /* Disable RXNE and ERR interrupt */
  2692. __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
  2693. if (hspi->TxXferCount == 0U)
  2694. {
  2695. SPI_CloseRxTx_ISR(hspi);
  2696. }
  2697. }
  2698. }
  2699. #if (USE_SPI_CRC != 0U)
  2700. /**
  2701. * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
  2702. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2703. * the configuration information for SPI module.
  2704. * @retval None
  2705. */
  2706. static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
  2707. {
  2708. __IO uint8_t tmpreg = 0U;
  2709. /* Read data register to flush CRC */
  2710. tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
  2711. /* To avoid GCC warning */
  2712. UNUSED(tmpreg);
  2713. hspi->CRCSize--;
  2714. /* Check end of the reception */
  2715. if (hspi->CRCSize == 0U)
  2716. {
  2717. /* Disable RXNE and ERR interrupt */
  2718. __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
  2719. if (hspi->TxXferCount == 0U)
  2720. {
  2721. SPI_CloseRxTx_ISR(hspi);
  2722. }
  2723. }
  2724. }
  2725. #endif /* USE_SPI_CRC */
  2726. /**
  2727. * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
  2728. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2729. * the configuration information for SPI module.
  2730. * @retval None
  2731. */
  2732. static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
  2733. {
  2734. /* Transmit data in packing Bit mode */
  2735. if (hspi->TxXferCount >= 2U)
  2736. {
  2737. hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
  2738. hspi->pTxBuffPtr += sizeof(uint16_t);
  2739. hspi->TxXferCount -= 2U;
  2740. }
  2741. /* Transmit data in 8 Bit mode */
  2742. else
  2743. {
  2744. *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
  2745. hspi->TxXferCount--;
  2746. }
  2747. /* Check the end of the transmission */
  2748. if (hspi->TxXferCount == 0U)
  2749. {
  2750. #if (USE_SPI_CRC != 0U)
  2751. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  2752. {
  2753. /* Set CRC Next Bit to send CRC */
  2754. SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  2755. /* Disable TXE interrupt */
  2756. __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
  2757. return;
  2758. }
  2759. #endif /* USE_SPI_CRC */
  2760. /* Disable TXE interrupt */
  2761. __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
  2762. if (hspi->RxXferCount == 0U)
  2763. {
  2764. SPI_CloseRxTx_ISR(hspi);
  2765. }
  2766. }
  2767. }
  2768. /**
  2769. * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
  2770. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2771. * the configuration information for SPI module.
  2772. * @retval None
  2773. */
  2774. static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
  2775. {
  2776. /* Receive data in 16 Bit mode */
  2777. *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
  2778. hspi->pRxBuffPtr += sizeof(uint16_t);
  2779. hspi->RxXferCount--;
  2780. if (hspi->RxXferCount == 0U)
  2781. {
  2782. #if (USE_SPI_CRC != 0U)
  2783. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  2784. {
  2785. hspi->RxISR = SPI_2linesRxISR_16BITCRC;
  2786. return;
  2787. }
  2788. #endif /* USE_SPI_CRC */
  2789. /* Disable RXNE interrupt */
  2790. __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
  2791. if (hspi->TxXferCount == 0U)
  2792. {
  2793. SPI_CloseRxTx_ISR(hspi);
  2794. }
  2795. }
  2796. }
  2797. #if (USE_SPI_CRC != 0U)
  2798. /**
  2799. * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
  2800. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2801. * the configuration information for SPI module.
  2802. * @retval None
  2803. */
  2804. static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
  2805. {
  2806. /* Receive data in 16 Bit mode */
  2807. __IO uint16_t tmpreg = 0U;
  2808. /* Read data register to flush CRC */
  2809. tmpreg = hspi->Instance->DR;
  2810. /* To avoid GCC warning */
  2811. UNUSED(tmpreg);
  2812. /* Disable RXNE interrupt */
  2813. __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
  2814. SPI_CloseRxTx_ISR(hspi);
  2815. }
  2816. #endif /* USE_SPI_CRC */
  2817. /**
  2818. * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
  2819. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2820. * the configuration information for SPI module.
  2821. * @retval None
  2822. */
  2823. static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
  2824. {
  2825. /* Transmit data in 16 Bit mode */
  2826. hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
  2827. hspi->pTxBuffPtr += sizeof(uint16_t);
  2828. hspi->TxXferCount--;
  2829. /* Enable CRC Transmission */
  2830. if (hspi->TxXferCount == 0U)
  2831. {
  2832. #if (USE_SPI_CRC != 0U)
  2833. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  2834. {
  2835. /* Set CRC Next Bit to send CRC */
  2836. SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  2837. /* Disable TXE interrupt */
  2838. __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
  2839. return;
  2840. }
  2841. #endif /* USE_SPI_CRC */
  2842. /* Disable TXE interrupt */
  2843. __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
  2844. if (hspi->RxXferCount == 0U)
  2845. {
  2846. SPI_CloseRxTx_ISR(hspi);
  2847. }
  2848. }
  2849. }
  2850. #if (USE_SPI_CRC != 0U)
  2851. /**
  2852. * @brief Manage the CRC 8-bit receive in Interrupt context.
  2853. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2854. * the configuration information for SPI module.
  2855. * @retval None
  2856. */
  2857. static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
  2858. {
  2859. __IO uint8_t tmpreg = 0U;
  2860. /* Read data register to flush CRC */
  2861. tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
  2862. /* To avoid GCC warning */
  2863. UNUSED(tmpreg);
  2864. hspi->CRCSize--;
  2865. if (hspi->CRCSize == 0U)
  2866. {
  2867. SPI_CloseRx_ISR(hspi);
  2868. }
  2869. }
  2870. #endif /* USE_SPI_CRC */
  2871. /**
  2872. * @brief Manage the receive 8-bit in Interrupt context.
  2873. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2874. * the configuration information for SPI module.
  2875. * @retval None
  2876. */
  2877. static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
  2878. {
  2879. *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
  2880. hspi->RxXferCount--;
  2881. #if (USE_SPI_CRC != 0U)
  2882. /* Enable CRC Transmission */
  2883. if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
  2884. {
  2885. SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  2886. }
  2887. #endif /* USE_SPI_CRC */
  2888. if (hspi->RxXferCount == 0U)
  2889. {
  2890. #if (USE_SPI_CRC != 0U)
  2891. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  2892. {
  2893. hspi->RxISR = SPI_RxISR_8BITCRC;
  2894. return;
  2895. }
  2896. #endif /* USE_SPI_CRC */
  2897. SPI_CloseRx_ISR(hspi);
  2898. }
  2899. }
  2900. #if (USE_SPI_CRC != 0U)
  2901. /**
  2902. * @brief Manage the CRC 16-bit receive in Interrupt context.
  2903. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2904. * the configuration information for SPI module.
  2905. * @retval None
  2906. */
  2907. static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
  2908. {
  2909. __IO uint16_t tmpreg = 0U;
  2910. /* Read data register to flush CRC */
  2911. tmpreg = hspi->Instance->DR;
  2912. /* To avoid GCC warning */
  2913. UNUSED(tmpreg);
  2914. /* Disable RXNE and ERR interrupt */
  2915. __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
  2916. SPI_CloseRx_ISR(hspi);
  2917. }
  2918. #endif /* USE_SPI_CRC */
  2919. /**
  2920. * @brief Manage the 16-bit receive in Interrupt context.
  2921. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2922. * the configuration information for SPI module.
  2923. * @retval None
  2924. */
  2925. static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
  2926. {
  2927. *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
  2928. hspi->pRxBuffPtr += sizeof(uint16_t);
  2929. hspi->RxXferCount--;
  2930. #if (USE_SPI_CRC != 0U)
  2931. /* Enable CRC Transmission */
  2932. if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
  2933. {
  2934. SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  2935. }
  2936. #endif /* USE_SPI_CRC */
  2937. if (hspi->RxXferCount == 0U)
  2938. {
  2939. #if (USE_SPI_CRC != 0U)
  2940. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  2941. {
  2942. hspi->RxISR = SPI_RxISR_16BITCRC;
  2943. return;
  2944. }
  2945. #endif /* USE_SPI_CRC */
  2946. SPI_CloseRx_ISR(hspi);
  2947. }
  2948. }
  2949. /**
  2950. * @brief Handle the data 8-bit transmit in Interrupt mode.
  2951. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2952. * the configuration information for SPI module.
  2953. * @retval None
  2954. */
  2955. static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
  2956. {
  2957. *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
  2958. hspi->TxXferCount--;
  2959. if (hspi->TxXferCount == 0U)
  2960. {
  2961. #if (USE_SPI_CRC != 0U)
  2962. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  2963. {
  2964. /* Enable CRC Transmission */
  2965. SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  2966. }
  2967. #endif /* USE_SPI_CRC */
  2968. SPI_CloseTx_ISR(hspi);
  2969. }
  2970. }
  2971. /**
  2972. * @brief Handle the data 16-bit transmit in Interrupt mode.
  2973. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2974. * the configuration information for SPI module.
  2975. * @retval None
  2976. */
  2977. static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
  2978. {
  2979. /* Transmit data in 16 Bit mode */
  2980. hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
  2981. hspi->pTxBuffPtr += sizeof(uint16_t);
  2982. hspi->TxXferCount--;
  2983. if (hspi->TxXferCount == 0U)
  2984. {
  2985. #if (USE_SPI_CRC != 0U)
  2986. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  2987. {
  2988. /* Enable CRC Transmission */
  2989. SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  2990. }
  2991. #endif /* USE_SPI_CRC */
  2992. SPI_CloseTx_ISR(hspi);
  2993. }
  2994. }
  2995. /**
  2996. * @brief Handle SPI Communication Timeout.
  2997. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  2998. * the configuration information for SPI module.
  2999. * @param Flag SPI flag to check
  3000. * @param State flag state to check
  3001. * @param Timeout Timeout duration
  3002. * @param Tickstart tick start value
  3003. * @retval HAL status
  3004. */
  3005. static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
  3006. uint32_t Timeout, uint32_t Tickstart)
  3007. {
  3008. while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
  3009. {
  3010. if (Timeout != HAL_MAX_DELAY)
  3011. {
  3012. if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
  3013. {
  3014. /* Disable the SPI and reset the CRC: the CRC value should be cleared
  3015. on both master and slave sides in order to resynchronize the master
  3016. and slave for their respective CRC calculation */
  3017. /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
  3018. __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
  3019. if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
  3020. || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
  3021. {
  3022. /* Disable SPI peripheral */
  3023. __HAL_SPI_DISABLE(hspi);
  3024. }
  3025. /* Reset CRC Calculation */
  3026. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  3027. {
  3028. SPI_RESET_CRC(hspi);
  3029. }
  3030. hspi->State = HAL_SPI_STATE_READY;
  3031. /* Process Unlocked */
  3032. __HAL_UNLOCK(hspi);
  3033. return HAL_TIMEOUT;
  3034. }
  3035. }
  3036. }
  3037. return HAL_OK;
  3038. }
  3039. /**
  3040. * @brief Handle SPI FIFO Communication Timeout.
  3041. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  3042. * the configuration information for SPI module.
  3043. * @param Fifo Fifo to check
  3044. * @param State Fifo state to check
  3045. * @param Timeout Timeout duration
  3046. * @param Tickstart tick start value
  3047. * @retval HAL status
  3048. */
  3049. static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
  3050. uint32_t Timeout, uint32_t Tickstart)
  3051. {
  3052. __IO uint8_t tmpreg;
  3053. while ((hspi->Instance->SR & Fifo) != State)
  3054. {
  3055. if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
  3056. {
  3057. tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
  3058. /* To avoid GCC warning */
  3059. UNUSED(tmpreg);
  3060. }
  3061. if (Timeout != HAL_MAX_DELAY)
  3062. {
  3063. if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
  3064. {
  3065. /* Disable the SPI and reset the CRC: the CRC value should be cleared
  3066. on both master and slave sides in order to resynchronize the master
  3067. and slave for their respective CRC calculation */
  3068. /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
  3069. __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
  3070. if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
  3071. || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
  3072. {
  3073. /* Disable SPI peripheral */
  3074. __HAL_SPI_DISABLE(hspi);
  3075. }
  3076. /* Reset CRC Calculation */
  3077. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  3078. {
  3079. SPI_RESET_CRC(hspi);
  3080. }
  3081. hspi->State = HAL_SPI_STATE_READY;
  3082. /* Process Unlocked */
  3083. __HAL_UNLOCK(hspi);
  3084. return HAL_TIMEOUT;
  3085. }
  3086. }
  3087. }
  3088. return HAL_OK;
  3089. }
  3090. /**
  3091. * @brief Handle the check of the RX transaction complete.
  3092. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  3093. * the configuration information for SPI module.
  3094. * @param Timeout Timeout duration
  3095. * @param Tickstart tick start value
  3096. * @retval HAL status
  3097. */
  3098. static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
  3099. {
  3100. if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
  3101. || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
  3102. {
  3103. /* Disable SPI peripheral */
  3104. __HAL_SPI_DISABLE(hspi);
  3105. }
  3106. /* Control the BSY flag */
  3107. if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
  3108. {
  3109. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  3110. return HAL_TIMEOUT;
  3111. }
  3112. if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
  3113. || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
  3114. {
  3115. /* Empty the FRLVL fifo */
  3116. if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
  3117. {
  3118. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  3119. return HAL_TIMEOUT;
  3120. }
  3121. }
  3122. return HAL_OK;
  3123. }
  3124. /**
  3125. * @brief Handle the check of the RXTX or TX transaction complete.
  3126. * @param hspi SPI handle
  3127. * @param Timeout Timeout duration
  3128. * @param Tickstart tick start value
  3129. * @retval HAL status
  3130. */
  3131. static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
  3132. {
  3133. /* Control if the TX fifo is empty */
  3134. if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
  3135. {
  3136. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  3137. return HAL_TIMEOUT;
  3138. }
  3139. /* Control the BSY flag */
  3140. if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
  3141. {
  3142. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  3143. return HAL_TIMEOUT;
  3144. }
  3145. /* Control if the RX fifo is empty */
  3146. if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
  3147. {
  3148. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  3149. return HAL_TIMEOUT;
  3150. }
  3151. return HAL_OK;
  3152. }
  3153. /**
  3154. * @brief Handle the end of the RXTX transaction.
  3155. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  3156. * the configuration information for SPI module.
  3157. * @retval None
  3158. */
  3159. static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
  3160. {
  3161. uint32_t tickstart = 0U;
  3162. /* Init tickstart for timeout managment*/
  3163. tickstart = HAL_GetTick();
  3164. /* Disable ERR interrupt */
  3165. __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
  3166. /* Check the end of the transaction */
  3167. if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  3168. {
  3169. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  3170. }
  3171. #if (USE_SPI_CRC != 0U)
  3172. /* Check if CRC error occurred */
  3173. if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
  3174. {
  3175. hspi->State = HAL_SPI_STATE_READY;
  3176. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  3177. __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
  3178. HAL_SPI_ErrorCallback(hspi);
  3179. }
  3180. else
  3181. {
  3182. #endif /* USE_SPI_CRC */
  3183. if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
  3184. {
  3185. if (hspi->State == HAL_SPI_STATE_BUSY_RX)
  3186. {
  3187. hspi->State = HAL_SPI_STATE_READY;
  3188. HAL_SPI_RxCpltCallback(hspi);
  3189. }
  3190. else
  3191. {
  3192. hspi->State = HAL_SPI_STATE_READY;
  3193. HAL_SPI_TxRxCpltCallback(hspi);
  3194. }
  3195. }
  3196. else
  3197. {
  3198. hspi->State = HAL_SPI_STATE_READY;
  3199. HAL_SPI_ErrorCallback(hspi);
  3200. }
  3201. #if (USE_SPI_CRC != 0U)
  3202. }
  3203. #endif /* USE_SPI_CRC */
  3204. }
  3205. /**
  3206. * @brief Handle the end of the RX transaction.
  3207. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  3208. * the configuration information for SPI module.
  3209. * @retval None
  3210. */
  3211. static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
  3212. {
  3213. /* Disable RXNE and ERR interrupt */
  3214. __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
  3215. /* Check the end of the transaction */
  3216. if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  3217. {
  3218. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  3219. }
  3220. hspi->State = HAL_SPI_STATE_READY;
  3221. #if (USE_SPI_CRC != 0U)
  3222. /* Check if CRC error occurred */
  3223. if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
  3224. {
  3225. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  3226. __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
  3227. HAL_SPI_ErrorCallback(hspi);
  3228. }
  3229. else
  3230. {
  3231. #endif /* USE_SPI_CRC */
  3232. if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
  3233. {
  3234. HAL_SPI_RxCpltCallback(hspi);
  3235. }
  3236. else
  3237. {
  3238. HAL_SPI_ErrorCallback(hspi);
  3239. }
  3240. #if (USE_SPI_CRC != 0U)
  3241. }
  3242. #endif /* USE_SPI_CRC */
  3243. }
  3244. /**
  3245. * @brief Handle the end of the TX transaction.
  3246. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  3247. * the configuration information for SPI module.
  3248. * @retval None
  3249. */
  3250. static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
  3251. {
  3252. uint32_t tickstart = 0U;
  3253. /* Init tickstart for timeout management*/
  3254. tickstart = HAL_GetTick();
  3255. /* Disable TXE and ERR interrupt */
  3256. __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
  3257. /* Check the end of the transaction */
  3258. if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  3259. {
  3260. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  3261. }
  3262. /* Clear overrun flag in 2 Lines communication mode because received is not read */
  3263. if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
  3264. {
  3265. __HAL_SPI_CLEAR_OVRFLAG(hspi);
  3266. }
  3267. hspi->State = HAL_SPI_STATE_READY;
  3268. if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  3269. {
  3270. HAL_SPI_ErrorCallback(hspi);
  3271. }
  3272. else
  3273. {
  3274. HAL_SPI_TxCpltCallback(hspi);
  3275. }
  3276. }
  3277. /**
  3278. * @brief Handle abort a Rx transaction.
  3279. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  3280. * the configuration information for SPI module.
  3281. * @retval None
  3282. */
  3283. static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
  3284. {
  3285. __IO uint32_t count;
  3286. /* Disable SPI Peripheral */
  3287. __HAL_SPI_DISABLE(hspi);
  3288. count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
  3289. /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
  3290. CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
  3291. /* Check RXNEIE is disabled */
  3292. do
  3293. {
  3294. if (count-- == 0U)
  3295. {
  3296. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  3297. break;
  3298. }
  3299. }
  3300. while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
  3301. /* Control the BSY flag */
  3302. if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  3303. {
  3304. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  3305. }
  3306. /* Empty the FRLVL fifo */
  3307. if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  3308. {
  3309. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  3310. }
  3311. hspi->State = HAL_SPI_STATE_ABORT;
  3312. }
  3313. /**
  3314. * @brief Handle abort a Tx or Rx/Tx transaction.
  3315. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  3316. * the configuration information for SPI module.
  3317. * @retval None
  3318. */
  3319. static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
  3320. {
  3321. __IO uint32_t count;
  3322. count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
  3323. /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
  3324. CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
  3325. /* Check TXEIE is disabled */
  3326. do
  3327. {
  3328. if (count-- == 0U)
  3329. {
  3330. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  3331. break;
  3332. }
  3333. }
  3334. while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
  3335. if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  3336. {
  3337. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  3338. }
  3339. /* Disable SPI Peripheral */
  3340. __HAL_SPI_DISABLE(hspi);
  3341. /* Empty the FRLVL fifo */
  3342. if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  3343. {
  3344. hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  3345. }
  3346. hspi->State = HAL_SPI_STATE_ABORT;
  3347. }
  3348. /**
  3349. * @}
  3350. */
  3351. #endif /* HAL_SPI_MODULE_ENABLED */
  3352. /**
  3353. * @}
  3354. */
  3355. /**
  3356. * @}
  3357. */
  3358. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/