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@@ -59,7 +59,6 @@ enum class States : uint8_t {
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RISE, ///< 16 fast PWM cycles with increasing duty up to steady ON
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RISE, ///< 16 fast PWM cycles with increasing duty up to steady ON
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RISE_TO_ONE, ///< metastate allowing the timer change its state atomically without artefacts on the output pin
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RISE_TO_ONE, ///< metastate allowing the timer change its state atomically without artefacts on the output pin
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ONE, ///< steady 1 (ON), no change for the whole period
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ONE, ///< steady 1 (ON), no change for the whole period
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- ONE_TO_FALL, ///< metastate allowing the timer change its state atomically without artefacts on the output pin
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FALL, ///< 16 fast PWM cycles with decreasing duty down to steady OFF
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FALL, ///< 16 fast PWM cycles with decreasing duty down to steady OFF
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FALL_TO_ZERO ///< metastate allowing the timer change its state atomically without artefacts on the output pin
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FALL_TO_ZERO ///< metastate allowing the timer change its state atomically without artefacts on the output pin
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};
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};
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@@ -155,12 +154,7 @@ ISR(TIMER0_OVF_vect) // timer compare interrupt service routine
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return; // want full duty for the next ONE cycle again - so keep on heating and just wait for the next timer ovf
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return; // want full duty for the next ONE cycle again - so keep on heating and just wait for the next timer ovf
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}
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}
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// otherwise moving towards FALL
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// otherwise moving towards FALL
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- // @@TODO it looks like ONE_TO_FALL isn't necessary, there are no artefacts at all
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state = States::ONE;//_TO_FALL;
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state = States::ONE;//_TO_FALL;
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-// TCCR0B = (1 << CS00); // change prescaler to 1, i.e. 62.5kHz
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-// break;
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-// case States::ONE_TO_FALL:
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-// OCR0B = 255; // zero duty
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state=States::FALL;
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state=States::FALL;
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fastCounter = fastMax - 1;// we'll do 16-1 cycles of RISE
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fastCounter = fastMax - 1;// we'll do 16-1 cycles of RISE
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TCNT0 = 255; // force overflow on the next clock cycle
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TCNT0 = 255; // force overflow on the next clock cycle
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