u8g_dev_st7565_dogm132.c 6.0 KB

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  1. /*
  2. u8g_dev_st7565_dogm132.c
  3. Universal 8bit Graphics Library
  4. Copyright (c) 2011, olikraus@gmail.com
  5. All rights reserved.
  6. Redistribution and use in source and binary forms, with or without modification,
  7. are permitted provided that the following conditions are met:
  8. * Redistributions of source code must retain the above copyright notice, this list
  9. of conditions and the following disclaimer.
  10. * Redistributions in binary form must reproduce the above copyright notice, this
  11. list of conditions and the following disclaimer in the documentation and/or other
  12. materials provided with the distribution.
  13. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
  14. CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  15. INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  16. MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  17. DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
  18. CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  19. SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20. NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  21. LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  22. CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23. STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  25. ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26. */
  27. #include "u8g.h"
  28. #define WIDTH 132
  29. #define HEIGHT 32
  30. #define PAGE_HEIGHT 8
  31. static const uint8_t u8g_dev_st7565_dogm132_init_seq[] PROGMEM = {
  32. U8G_ESC_CS(0), /* disable chip */
  33. U8G_ESC_ADR(0), /* instruction mode */
  34. U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
  35. U8G_ESC_CS(1), /* enable chip */
  36. 0x040, /* set display start line to 0 */
  37. 0x0a1, /* ADC set to reverse */
  38. 0x0c0, /* common output mode */
  39. 0x0a6, /* display normal, bit val 0: LCD pixel off. */
  40. 0x0a2, /* LCD bias 1/9 */
  41. 0x02f, /* all power control circuits on */
  42. 0x0f8, /* set booster ratio to */
  43. 0x000, /* 4x */
  44. 0x023, /* set V0 voltage resistor ratio to large */
  45. 0x081, /* set contrast */
  46. 0x01f, /* contrast value, EA default: 0x01f */
  47. 0x0ac, /* indicator */
  48. 0x000, /* disable */
  49. 0x0af, /* display on */
  50. #ifdef OBSOLETE_DOGM128
  51. 0x040, /* set display start line */
  52. 0x0c8, /* set scan direction inverse operation */
  53. 0x0a2, /* LCD bias 1/9 */
  54. 0x02f, /* all power control circuits on */
  55. 0x0f8, /* set booster ratio to */
  56. 0x000, /* 4x */
  57. 0x027, /* set V0 voltage resistor ratio to large */
  58. 0x081, /* set contrast */
  59. 0x018, /* contrast value, EA default: 0x016 */
  60. 0x0ac, /* indicator */
  61. 0x000, /* disable */
  62. 0x0af, /* display on */
  63. #endif
  64. U8G_ESC_DLY(100), /* delay 100 ms */
  65. 0x0a5, /* display all points, ST7565 */
  66. U8G_ESC_DLY(100), /* delay 100 ms */
  67. U8G_ESC_DLY(100), /* delay 100 ms */
  68. 0x0a4, /* normal display */
  69. U8G_ESC_CS(0), /* disable chip */
  70. U8G_ESC_END /* end of sequence */
  71. };
  72. static const uint8_t u8g_dev_st7565_dogm132_data_start[] PROGMEM = {
  73. U8G_ESC_ADR(0), /* instruction mode */
  74. U8G_ESC_CS(1), /* enable chip */
  75. 0x010, /* set upper 4 bit of the col adr to 0 */
  76. 0x000, /* set lower 4 bit of the col adr to 0 */
  77. U8G_ESC_END /* end of sequence */
  78. };
  79. static const uint8_t u8g_dev_st7565_dogm132_sleep_on[] PROGMEM = {
  80. U8G_ESC_ADR(0), /* instruction mode */
  81. U8G_ESC_CS(1), /* enable chip */
  82. 0x0ac, /* static indicator off */
  83. 0x000, /* indicator register set (not sure if this is required) */
  84. 0x0ae, /* display off */
  85. 0x0a5, /* all points on */
  86. U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
  87. U8G_ESC_END /* end of sequence */
  88. };
  89. static const uint8_t u8g_dev_st7565_dogm132_sleep_off[] PROGMEM = {
  90. U8G_ESC_ADR(0), /* instruction mode */
  91. U8G_ESC_CS(1), /* enable chip */
  92. 0x0a4, /* all points off */
  93. 0x0af, /* display on */
  94. U8G_ESC_DLY(50), /* delay 50 ms */
  95. U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
  96. U8G_ESC_END /* end of sequence */
  97. };
  98. uint8_t u8g_dev_st7565_dogm132_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
  99. {
  100. switch(msg)
  101. {
  102. case U8G_DEV_MSG_INIT:
  103. u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
  104. u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm132_init_seq);
  105. break;
  106. case U8G_DEV_MSG_STOP:
  107. break;
  108. case U8G_DEV_MSG_PAGE_NEXT:
  109. {
  110. u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
  111. u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm132_data_start);
  112. u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (ST7565R) */
  113. u8g_SetAddress(u8g, dev, 1); /* data mode */
  114. if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
  115. return 0;
  116. u8g_SetChipSelect(u8g, dev, 0);
  117. }
  118. break;
  119. case U8G_DEV_MSG_CONTRAST:
  120. u8g_SetChipSelect(u8g, dev, 1);
  121. u8g_SetAddress(u8g, dev, 0); /* instruction mode */
  122. u8g_WriteByte(u8g, dev, 0x081);
  123. u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
  124. u8g_SetChipSelect(u8g, dev, 0);
  125. return 1;
  126. case U8G_DEV_MSG_SLEEP_ON:
  127. u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm132_sleep_on);
  128. return 1;
  129. case U8G_DEV_MSG_SLEEP_OFF:
  130. u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm132_sleep_off);
  131. return 1;
  132. }
  133. return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
  134. }
  135. U8G_PB_DEV(u8g_dev_st7565_dogm132_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_dogm132_fn, U8G_COM_SW_SPI);
  136. U8G_PB_DEV(u8g_dev_st7565_dogm132_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_dogm132_fn, U8G_COM_HW_SPI);