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Historique des commits

Auteur SHA1 Message Date
  D.R.racer 4d3a5433ad Implement read/write registers for M707/M708 il y a 1 an
  D.R.racer 2f0ceabce5 Upgrade protocol to v2.1 - read/write registers + CRC il y a 1 an
  VintagePC 9a20c85a5d First pass, improving the error recovery. il y a 2 ans
  D.R.racer 2e293e90a0 MMU2 interface overhaul il y a 2 ans