Commit History

Autor SHA1 Mensaxe Data
  D.R.racer 4d3a5433ad Implement read/write registers for M707/M708 hai 1 ano
  D.R.racer 2f0ceabce5 Upgrade protocol to v2.1 - read/write registers + CRC hai 1 ano
  VintagePC 9a20c85a5d First pass, improving the error recovery. %!s(int64=2) %!d(string=hai) anos
  D.R.racer 2e293e90a0 MMU2 interface overhaul %!s(int64=2) %!d(string=hai) anos